JPH0476272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to an apparatus for correcting time axis fluctuations of a video signal.

(Background of the Invention) In a magnetic recording/playback device such as a VTR or a video playback device such as a video disk, relative positional fluctuations between a signal detection medium such as a magnetic head or pick-up head and a recording medium such as a magnetic tape or disk are detected. This causes time axis fluctuations in the reproduced video signal. If such time axis fluctuations are gradual, it will appear as fluctuations (so-called jitters) on the playback screen, while on the other hand, if there are sudden changes in the time axis (so-called skew),
This inherently has the problem of causing phenomena such as bending, which significantly impairs the stability of the reproduced image.

As a method for correcting this time axis fluctuation, for example, as described in the literature (Japan Broadcasting Publishing Association, Broadcasting Technology Bisho Vol. 5 VTR Technology Chapter 6), a time axis correction device as shown in Fig. 2 is used. It is conventionally known.

In FIG. 2, 10 is an input terminal for a video signal having time axis fluctuations, and 20 is an output terminal for a video signal whose time axis fluctuations have been corrected. Further, 1 is an A/D conversion circuit that converts an input video signal into a digital signal, and 2 is a memory composed of RAM and the like.
Reference numeral 30 denotes a horizontal synchronization signal separation circuit, and the horizontal synchronization signal having time base fluctuations extracted from the horizontal synchronization separation circuit 30 is input to a write clock generation circuit 40 and a write address control circuit 50.

The write clock generation circuit 40 generates a write clock that matches the time axis fluctuation of the input video signal from the terminal 10 in synchronization with the horizontal synchronization signal. Further, the write address control circuit 50 outputs a write address using the write clock.

Therefore, the video signal input from the terminal 10 and having time axis fluctuations is sequentially converted into a digital signal by the A/D conversion circuit 1 in synchronization with the write clock output from the write clock generation circuit 40. The data is written into the memory 2 according to the address from the write address control circuit 50.

On the other hand, a stable reference synchronization signal with no time axis fluctuation is applied from the terminal 80, and the read clock generation circuit 70 generates a read clock synchronized with the reference synchronization signal. Read address control circuit 60 outputs an address synchronized with the read clock.

Therefore, the data of the video signal stored in the memory 2 is read out sequentially in each horizontal scanning period according to the address from the read address control circuit 60, and the read data is converted into an analog signal. The D/A conversion circuit 3 converts the signal into an analog signal in synchronization with the read clock output from the read clock generation circuit 70. Therefore, from the terminal 20, a stable video signal without time axis fluctuation is output.

As is clear from the above explanation of the operation, the performance of this time base correction device depends on the write clock generation circuit 40.
depends on how the write clock is generated.
An important deciding factor for the device is how to generate a write clock that accurately follows the time axis fluctuations of the input video signal.

Regarding the conventional example of this write clock generation circuit 40, as described in the above-mentioned document,
A system configured with a so-called AFC circuit shown in the figure is well known.

In FIG. 3, a horizontal synchronizing signal from a horizontal synchronizing signal separation circuit 30 is inputted to one side of a phase comparator circuit 43 via a terminal 41. 45 is a voltage controlled oscillation circuit whose center frequency is the same as the circuit 70 in FIG.
The frequency is set to be the same as the frequency of the read clock from the The output of the voltage controlled oscillation circuit 45 is divided by the frequency dividing circuit 46, and a signal having the same frequency as the horizontal scanning frequency of the input video signal is sent to the frequency dividing circuit 4.
It is output from 6. The horizontal synchronizing signal from the terminal 41 and the output from the frequency dividing circuit 46 are sent to the phase comparator circuit 43.
The phases are compared, and an error voltage corresponding to the phase difference between the two is supplied as a control voltage to the voltage controlled oscillation circuit 45 via the phase compensation circuit 44 outputted from the phase comparison circuit 43.

The above circuit constitutes a so-called AFC circuit, and its negative feedback control action allows the voltage controlled oscillator circuit 45 to obtain an output that follows the time axis fluctuations of the horizontal synchronizing signal of the input video signal, and this output is clocked by the write clock. It is output from the terminal 42 as.

The above is a conventionally known write clock generation method. However, since this conventional method uses negative feedback control, it is inherently difficult to use when the frequency of time axis fluctuations is high or when sudden time axis fluctuations such as skew occur. This causes a tracking error in the AFC system, and there is a problem that the time axis fluctuation remains without being corrected. In addition, attempts have been made to increase the response speed of the AFC system in order to improve its correction ability, but this has resulted in the AFC system becoming more sensitive to noise contained in the input video signal.
There is a problem that the AFC system is disturbed and the operation becomes extremely unstable. Furthermore, when the response speed of the AFC system is increased, when the amount of time axis fluctuation increases,
The AFC system deviates from the synchronous pull-in range,
This has caused problems such as time axis correction being no longer possible.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art and to provide a time axis fluctuation correction device that can stably and reliably eliminate any time axis fluctuations.

(Summary of the Invention) The present invention is characterized in that an oscillation output of a constant frequency that is instantaneously phase synchronized with horizontal synchronization information such as a horizontal synchronization signal or a burst signal included in an input video signal is outputted from an oscillation circuit, and The input video signal is used as a sampling clock and a memory write clock, and during a redundant blanking period in which no video information is included in the input video signal, such as a vertical blanking period, the oscillation output or its frequency is divided as appropriate. A phase error signal is generated by comparing the phase of the output with the output of a generation circuit that generates a reference signal of a predetermined frequency or an output obtained by dividing the frequency appropriately, and thereby voltage-controls the oscillation frequency of the oscillation circuit. By providing negative feedback to the voltage control means, the oscillation frequency can be stabilized without using negative feedback control such as AFC, and any time axis fluctuations in the input video signal can be stably and reliably removed. This is what I did.

(Examples of the invention) Hereinafter, the present invention will be explained in detail with reference to examples.
FIG. 1 is a block diagram showing one embodiment of a time axis correction device according to the present invention, and FIGS. 4 and 5 are waveform diagrams for explaining its operation. Note that FIG. 4 shows a part of the horizontal scanning period of the input video signal including the horizontal synchronization signal S as the horizontal synchronization information, and FIG. 5 shows the vertical blanking period of the input video signal as the redundant blanking period. Shows a part of.

In FIG. 1, block 400 shown in broken lines represents one embodiment of a write clock generation circuit according to the present invention.

In the figure, 1 is an A/D conversion circuit, 2 is a memory, and 3 is a D/A conversion circuit, which are the same as those in the conventional example shown in FIG. 2, and are designated by the same reference numerals. Further, 300 is a synchronous separation circuit, and 500 is a synchronous separation circuit.
is a write address control circuit, 600 is a read address control circuit, 700 is a reference synchronization signal generation circuit,
800 is a synchronous insertion circuit.

Next, the operation of write clock generation circuit 400 will be explained using the waveform diagrams of FIGS. 4 and 5.

From the input video signal from the terminal 10 (a in Fig. 4, a in Fig. 5), the synchronization information contained therein (a in Fig. 5) is
S in Figure a, S ₁ , S ₂ in Figure 5 a) is the synchronous separation circuit 3.
It is separated and output at 00. The synchronous separation circuit 300
The horizontal synchronization information contained therein is separated and outputted by the horizontal synchronization separation circuit 401 (b in FIG. 4, b in FIG. 5). In addition, the synchronous separation circuit 3
From the output from 00, the vertical synchronization information contained therein is separated and output (fifth
Figure c) is done. The monostable multi-circuit 403 is triggered by the output from the vertical synchronization separation circuit 402, and outputs a pulse width of a predetermined time _T0 based on the vertical blanking period of the input video signal (d in FIG. 5).
is obtained from the monostable multicircuit 403.

The output d from the monostable multi-circuit 403 is synchronized by the output b (for example, the falling edge of b) from the horizontal sync separation circuit 401 in the latch circuit 404, and the output e is shown as e in FIG. As shown, the signal is "L" for a predetermined time period _T1 , and is, so to speak, a signal that detects the vertical blanking period of the input video signal. Output b from horizontal sync separation circuit 401
is due to the output e from the latch circuit 404,
It is gated by an AND gate circuit 405, and its output (f in FIG. 5, b in FIG. 4) triggers a monostable multi-circuit 406 to generate a write start pulse (c in FIG. 4, g) in the figure is output.

As a result, the write start pulse g output from the monostable multi-circuit 406 corresponds to the above vertical blanking period, as shown in FIG.
During the period _T1 , it is inhibited and the write start pulse is not output.

The oscillation circuit 407 starts and stops oscillation in synchronization with the write start pulse from the monostable multi-circuit 406 input to the enable terminal E, and oscillates in synchronization with the control voltage input to the voltage control input terminal V. The oscillation circuit 407 is an oscillation circuit whose oscillation frequency is variable, and as a specific example, an astable multi-type oscillation circuit IC (SN74124N) with an enable terminal manufactured by Texas Instruments, Inc. can be used as the oscillation circuit 407.

By inputting the write start pulse to the enable terminal E of this oscillation circuit 407,
As shown in d in Figure 4 (or the shaded area h in Figure 5), during the period when the start pulse is "H", oscillation stops and the output becomes "L", and the start pulse changes from "H" to " Oscillation starts in synchronization with the transition of "L", and continuous oscillation output is obtained during the period when the start pulse is "L".

Furthermore, since the start pulse from the monostable multi-circuit 406 is output only during periods other than the vertical blanking period _T1 , as described above, the oscillation circuit 406
As shown in h in Fig. 5, the output from 7 is synchronized with the start pulse immediately before (x in g in Fig. 5) during the vertical blanking period _T1 , as shown in h in Fig. 5. .

This embodiment is characterized in that during this vertical blanking period _T1 , a so-called PLL circuit synchronizes its oscillation output with an external stable oscillation output in phase to ensure a stable oscillation frequency that does not cause frequency deviation. It is something to do.

That is, a reference clock with a stable frequency is obtained in a crystal oscillator circuit 408, and a frequency divider circuit 409, a phase comparison circuit 410, a gate circuit 411, a phase compensation circuit 412, an oscillation circuit 407, and a frequency divider circuit 413 are used.
A PLL circuit is configured by the oscillation circuit 407.
The oscillation output from the crystal oscillation circuit 408 is phase-synchronized with the reference clock from the crystal oscillation circuit 408.

The output from the crystal oscillator circuit 408 is the frequency divider circuit 4
09, the frequency is appropriately divided by 1/n, and its output is supplied to one side of the phase comparator circuit 410. The other side of the phase comparator circuit 410 is supplied with an output obtained by appropriately dividing the output from the oscillation circuit 407 into 1/m by a frequency dividing circuit 413. Note that each frequency dividing stage of the frequency dividing circuit 413 is reset by the write start pulse g from the monostable multicircuit 406.

In the phase comparison circuit 410, the phases of these 1/n and 1/m divided outputs are compared, and an error signal corresponding to the phase difference between the two is outputted from the phase comparison circuit 410. Gate circuit 411 is latch circuit 4
04, the output from the phase comparison circuit 410 is gated and supplied to the phase compensation circuit 412 only during the vertical blanking period _T1 , and during other periods, the gate circuit 411 is off. , from the phase comparator circuit 410 to the phase compensation circuit 412
The supply to the gate circuit 41 is cut off, and the gate circuit 41
The output impedance of 1 becomes sufficiently high.

As a result, the phase error signal from the phase comparison circuit 410 is supplied to the phase compensation circuit 412 via the gate circuit 411 only during the period of vertical blanking T ₁ , and in other periods, the phase error signal is supplied to the phase compensation circuit 412. 412. Phase compensation circuit 4
The phase error signal is sufficiently smoothed by the phase compensation circuit 412, and the characteristics of the PLL circuit are compensated so that the characteristics of the PLL circuit described above are sufficiently stable. The output of this phase compensation circuit 412 is input to the voltage control input terminal V of the oscillation circuit 407.

By the PLL negative feedback control configured as described above, the oscillation output of the oscillation circuit 407 is coupled in phase synchronization with the stable reference clock from the crystal oscillation circuit 408.
The oscillation frequency f _W can be calculated using the following formula, where f _W is the frequency of the reference clock from the crystal oscillation circuit 408, f _W =m/n・f ₀ (1) m, n, The value of f _W can be set arbitrarily by the value of f ₀ ,
A stable oscillation output can be obtained without deviation from the set value.

Furthermore, unlike the value control type AFC described in FIG. Sufficient response speed can be obtained because it can be made small (that is, m of the frequency divider circuit 413 can be brought close to 1) and the maximum value of the phase shift during phase synchronization pull-in is at most one cycle of the oscillation output. Therefore, phase fluctuations in the oscillation output are less likely to occur, and even if they occur, they are slight. Moreover, since the phase of the oscillation output is instantaneously aligned with the write start pulse g from the monostable multi-circuit 406 corresponding to the synchronization information included in the input video signal, the influence of the phase fluctuation is greatly reduced.

The output h from this oscillation circuit 407 is used as a sampling clock for the input video signal and a write clock for the memory 2.

Input video signal a from terminal 10 (a in Fig. 4,
5a) is the A/D conversion circuit 1 and the oscillation circuit 40.
The signal is sequentially sampled by the output clock from 7 and converted into a digital signal. The write address control circuit 500 is composed of a counter, etc., and starts counting by a write start pulse for each horizontal scanning period from the monostable multi-circuit 406, and counts a predetermined number of clocks from the oscillator circuit 407 to make time. During the period T (see FIG. 4), an address signal corresponding to the counted value is outputted and supplied as a write address signal to the memory 2.
Also, this address signal is used by the monostable multi-circuit 40.
The A/D is sequentially updated every horizontal scanning period by the write start pulse g from
The output from the conversion circuit 1 is sequentially written into the memory 2 in units of horizontal scanning periods.

Here, the start point (A in Figure 4a) and end point (B in Figure 4a) of writing to the memory for each horizontal scanning period
The value of T and the value of the pulse width τ of the write start pulse are set so that both are included within the horizontal blanking period based on horizontal scanning of the input video signal. Therefore, only necessary and sufficient video information of the input video signal can be written into the memory.

Also, as is clear from the above operation, the sampling clock h (or the memory write clock) is generated in instantaneous phase synchronization with the synchronization information included in the input video signal, so the time axis due to the sampling quantization without any fluctuations,
In addition, it is stable without being affected by time axis fluctuations included in the input video signal, and the above-mentioned
PLL negative feedback control allows an accurate sampling clock to be obtained without frequency deviation.

Next, in FIG. 1, the reference clock from the crystal oscillator circuit 408 is converted to
The output is used as a read clock by the read address control circuit 600 and the D/A conversion circuit 3.
and to the reference synchronization signal generation circuit 700. The frequency f _R of the read clock from this circuit 414 is given by:

f _R =m/n・f ₀ ... (2) From the above equation (2) and the previous equation (1), the frequency of the read clock from the circuit 414 (f _R ) and the frequency of the write clock from the circuit 407 ( f _W ) is equal.

In the reference synchronization signal generation circuit 700, the circuit 414
The clock from is divided appropriately to obtain the synchronization signal of the input video signal (S in Fig. 4a, S ₁ and S ₂ in Fig. 5a)
a reference synchronization signal CS of the same format and frequency as
A read start pulse HS is generated at the same timing as the write start pulse in FIG. 4C for the horizontal synchronization signal of the reference synchronization signal CS,
Further, a reference vertical synchronization signal VS is generated.

The read address control circuit 600 is composed of a counter, etc., like the write address control circuit 500 described above, and starts counting in response to a read start pulse HS from the reference synchronization signal generation circuit 700 in each horizontal scanning period. Thereafter, a predetermined number of clocks are counted from the frequency divider circuit 414, and an address signal corresponding to the counted value is output for a time T, as shown in FIG. 4, and is supplied as a read address signal to the memory 2. Ru.

Further, this address signal is sequentially updated every horizontal scanning period by the read start pulse HS from the reference synchronization signal generation circuit 700, and therefore the written video information is transferred from the memory 2 every horizontal scanning period. It is read out sequentially, and the output is converted into an analog signal by the D/A conversion circuit 3.

As is clear from the above operation, both the write address signal from the write address control circuit 500 and the read address signal from the read address control circuit 600 are output only during the period T excluding the horizontal blanking period of the input video signal. Therefore, the outputs of the memory 2 and the D/A conversion circuit 3 do not include horizontal blanking and synchronization signals. In order to restore the signal in the same format as the input video signal, the synchronization insertion circuit 800 adds the reference synchronization signal CS from the reference synchronization signal generation circuit 700 to the output from the D/A conversion circuit 3.
(Composite sync) is inserted and added.

Note that the reference vertical synchronization signal VS from the reference synchronization signal generation circuit 700 is outputted as a reference signal to a servo control device (not shown) via the terminal 100.

This servo control device is used with a signal detection medium such as a magnetic head or a pick-up head in a magnetic recording/playback device such as a VTR or a video playback device such as a video disk to which the time axis correction device based on the embodiment shown in FIG. 1 is applied. It consists of a tracking control system for correctly reproducing signals by controlling the relative phase with a recording medium such as a magnetic tape or disk, and conventionally known systems are used.

By inputting the reference vertical synchronization signal VS from the terminal 100 to this servo control device,
The input video signal from the terminal 10 is servo-controlled so as to be phase-synchronized with this reference vertical synchronization signal.
More specifically, servo control is performed so that the phase of the reference vertical synchronization signal is delayed in time with respect to the phase of the vertical synchronization signal of the input video signal.

This servo control controls the write operation to the memory 2 so that it precedes the read operation. Therefore, all of the video information written to the memory 2 is read correctly without any loss on a stable time axis with no fluctuations, and the blanking and synchronization information deleted when writing to the memory 2 is read by the synchronization insertion circuit 800. is supplemented by a reference synchronization signal CS with the same stable time axis as the reading. Therefore, from the terminal 20, a stable video signal from which time axis fluctuations of the input video signal have been removed is correctly restored and output.

In addition, as mentioned above, since the write clock frequency (f _W ) and the read clock frequency (f _R ) are controlled by PLL so that they are the same, only the time axis fluctuations of the input video signal are removed, and the write and read clock frequencies (f R ) are controlled to be the same. When reading, the time axis is not compressed or expanded, causing graphical distortion. Furthermore, since the write clock is generated in instantaneous synchronization with the synchronization information of the input video signal, even if a sudden time axis change such as skew occurs, the write clock generation circuit 400 will not be disturbed by it. Therefore, it is possible to stably obtain a write clock that accurately follows any time axis fluctuation.

In the above embodiments, the conventional horizontal synchronization signal for each horizontal scan and the vertical synchronization signal for each vertical scan are used as video signal synchronization information, but the present invention is not limited to this. isn't it. For example, when assigning one horizontal synchronization information to multiple (for example, two) horizontal scans, as has been proposed in some cases for high-definition video signals, or when assigning luminance information and chromaticity information to one horizontal scan period. This method is also applicable when time-division multiplexing is performed by assigning one synchronization information to a single horizontal scanning period, or when multiple synchronization information (for example, synchronization information for luminance information and synchronization information for chromaticity information) is assigned to one horizontal scanning period. can.

Further, although the embodiment shown in FIG. 1 shows the case where the write clock f _W and the read clock f _R are set to have the same frequency, the present invention is not limited to this.

As an example, if the video signal input to the terminal 10 has a different time axis from that of a normal video signal,
For example, when a video signal that has been time-axis converted by m/n times the original video signal (time-axis compression when m>n, time-axis expansion when m<n) is input to the terminal 10, The frequency division ratio of the frequency circuit 414 is set to 1 (m
=n) and set the reference clock _f0 and the reading clock.
Either set f _R to the same frequency or do not use the frequency divider circuit 414 and the crystal oscillation circuit 41
If the reference clock f ₀ from 8 is directly supplied as the read clock f _R to the reference synchronization signal generation circuit 700, read address control circuit 600, and D/A conversion circuit 3, then f _R = (n /m)f _W , and therefore, in this case, the time axis of the input video signal is conversely transformed by m/n times (m>n
If m<n, the time axis is expanded, and if m<n, the signal is compressed on the time axis), and a signal having the same time axis as the original video signal can be obtained at the output terminal 20.

As described above, according to the present invention, in addition to the time axis correction function that removes the fluctuations in the time axis described above, the time axis conversion function that compresses or expands the time axis can be simultaneously realized without increasing the circuit scale. It is possible to obtain large economic effects.

Furthermore, not only negative polarity synchronization information as shown in FIGS. 4 and 5, but also positive polarity synchronization information, and instead of the conventional synchronization signal, for example, a separate part of horizontal blanking may be added. It can also be applied to cases where synchronization information such as multiplexed burst signals is used, and in any of these cases, the gist of the present invention is true and the effects obtained are the same.

In addition, in the embodiment of FIG. 1, the reference clock (f ₀ )
are individually generated by the crystal oscillation circuit 408, and the reference synchronization signal (CS) is generated by the reference synchronization signal generation circuit 700.
The figure shows a case in which the reference clock is formed inside the device, but in order to synchronously combine this reference synchronization signal with the reference synchronization signal from the outside, the APC circuit shown in Fig. 6 is used to obtain the same reference clock as above. However, this is the gist of the present invention.

That is, in FIG. 6, 700 is the same reference synchronization signal generation circuit as in FIG. 1, and is indicated by the same reference numeral.
VS, generates read start pulse HS. An output clock from a voltage controlled oscillation circuit 950 is supplied to the input of this reference synchronization signal generation circuit 700. An external reference synchronization signal is input to the input terminal 910, and a vertical synchronization signal is separated and outputted by the vertical synchronization separation circuit 920. The external reference vertical synchronization signal from the vertical synchronization separation circuit 920 and the internal reference vertical synchronization signal from the reference synchronization signal generation circuit 700
The phase of VS is compared in the phase comparison circuit 930, and the error voltage according to the phase difference between the two is outputted to the phase comparison circuit 930.
The voltage is output from the oscillation circuit 950 and supplied as a control voltage to the oscillation circuit 950 via the phase compensation circuit 940.

The above circuit constitutes an APC (or AFC) circuit, and the internal reference vertical synchronization signal VS from the reference synchronization signal generation circuit 700 is phase-synchronized with the external reference vertical synchronization signal. An output of the same frequency (f ₀ ) as the reference clock from the crystal oscillation circuit 408 in FIG.
60.

As described above, the oscillation circuit 950 based on the embodiment of FIG.
If used in place of the crystal oscillation circuit 408 of FIG. 1, the above-described time base correction device can be operated in external synchronization.

(Effects of the Invention) As described above, according to the present invention, it is possible to stably obtain a sampling clock that accurately follows any time axis fluctuations in the video signal without any frequency deviation. At the same time, it is possible to obtain effects such as being able to reliably remove the time-axis fluctuation without distortion of the figure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a conventional block diagram of a time axis correction device, FIG. 3 is a conventional block diagram of a write clock generation circuit, and FIGS. 4 and 5 are waveform diagrams of various parts of FIG. 1.
FIG. 6 is a block diagram showing another embodiment in which the time base correction device of the present invention is operated in external synchronization. 1...A/D conversion circuit, 2...memory, 3...
D/A conversion circuit, 300...Synchronization separation circuit, 40
0...Write clock generation circuit, 500...Write address control circuit, 600...Read address control circuit, 700...Reference synchronization signal generation circuit, 8
00...Synchronization insertion circuit.

Claims (1)

[Scope of Claims] 1. Synchronization information separation means for separating synchronization information included in an input video signal, and detecting at least a part of a redundant blanking period that does not have video information included in the video signal. an oscillation circuit whose start of oscillation is controlled in response to the output from the separation means; a voltage control means which voltage-controls the oscillation frequency of the oscillation circuit; and a reference which generates a reference signal of a predetermined frequency. A signal generation circuit compares the phases of the output from the reference signal generation circuit or the output obtained by dividing the output with the output from the oscillation circuit or the output obtained by dividing the output, and the phase error signal is detected by the detection. means for gating the output from the means for a predetermined period and feeding it back to the voltage control means; converting means for sampling the video signal and converting it into a sample value signal based on the output from the oscillation circuit; and the converting means writing means for sequentially writing output signals from the oscillator into a memory having a predetermined storage capacity using a write clock based on the output from the oscillation circuit; A time axis correction device for a video signal, comprising: reading means for sequentially reading signals; and output means for outputting the signals read from the memory. 2. The output means comprises: synchronization signal generation means for generating a reference synchronization signal based on the output of the reference signal generation circuit; and means for inserting the synchronization signal into the signal read from the memory. The video signal time axis correction device according to item 1. 3. The time axis correction device for a video signal according to claim 1, wherein the synchronization signal separation means is configured to separate a horizontal synchronization signal of the video signal. 4. The video signal time axis correction device according to claim 1, wherein the detection means is configured to output a pulse corresponding to a part of the period of vertical blanking of the video signal. 5. The frequency of the write clock based on the output from the oscillator circuit is chosen to be different from the frequency of the read clock based on the output from the reference signal generation circuit, and the output means is configured to 2. The video signal time axis correction device according to claim 1, wherein the video signal time axis correction device is configured to output a signal in which the time axis of the input video signal is compressed or expanded according to a ratio of clock frequencies. 6. The writing means includes a counting means for counting the number of output pulses from the oscillation circuit, and writes video information excluding at least a horizontal blanking period of the video signal into the memory according to the output of the counting means. A time axis correction device for a video signal according to claim 1. 7. The video signal time axis correction device according to claim 1, wherein the reference signal generation circuit is configured to generate a signal synchronized with a reference signal supplied from the outside.