JPH0453067A - Time base correcting circuit - Google Patents

Abstract

PURPOSE:To reduce residual error and to improve ability for correcting velocity error by extending a time base by an auxiliary holding means and a write/read control means before writing a reproducing data. CONSTITUTION:Since the data of a regenerative signal to be outputted from an A/D converting means 2 is written in an auxiliary holding means 6 at reference timing by a write/read control means 8 and read out at timing dividing the frequency of the reference timing by a prescribed frequency dividing ratio, the time base is extended. On the other hand, this data of the regenerative signal is written in a holding means 7 at timing corrected based on phase error detected by a phase error detecting means 9 under the control of a write control means 11. Then, the data of the regenerative signal to be held is read out at the reference timing, which is decided according to the accuracy of reference synchronism and a reference clock, by a read control means 12 while compressing the time base, converted to be analog and outputted as the regenerative signal having no time base error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time axis correction circuit that is applied to a recording/reproducing device such as a video tape recorder and performs time axis correction by removing a time axis error of a reproduced signal. It is something.

[Conventional technology]

In recording/playback devices such as video tape recorders, playback signals (including time axis errors called jitter) due to fluctuations in the relative speed between the magnetic tape and the playback head, etc.
If the image is played back as is, sideways shaking, color shift, etc. will occur in the played image. For this reason, some conventional recording and reproducing apparatuses are equipped with a time axis correction circuit for removing time axis errors, for example as shown below, and are configured to obtain good reproduced images.

As shown in FIG. 3, the reproduced signal input to the time axis correction circuit is converted into digital data by an A/D converter (A/D in the figure) 31 using the reference clock as a sampling clock, and becomes discretized data. In addition, the synchronous separation circuit 32
The horizontal synchronization signal is separated by Phase error detection circuit 3
3, based on the discretized data and the horizontal synchronization signal, a difference of the reference clock equal to or less than the JJilI period and a phase error of one cycle or more are detected, and the former is input to the W and Zero correction circuit 34, and the latter is is input to the phase modulation circuit 35.

W, Zero correction circuit 34 specifies address 00 when writing discretized data to memory 37, which will be described later.
Zer o (WRITE ZEJ<O) is 1
The phase is corrected so that the phase error is less than one period. In addition, the phase modulation circuit 3
In step 5, the phase error L is corrected to a phase error based on one cycle, and the phase of the reference clock 11 is transformed by this phase error to become the write clock WCk. Further, in the write address generation circuit 3G, a write address is generated based on the W, Zero and write clock described above.

On the other hand, the discretized data outputted from the A/D converter 31 is delayed by the delay circuit 37 at the timing of 11 base points in order to compensate for the delay time of error detection in the phase error detection circuit 33. is input. Then,
In the memory 38, discretized data is written to the J1 write address for each horizontal device period (H) at the timing of the write clock Wck. Thereby, the discretized data is held in the memory 38 with time axis errors removed.

The read address generation circuit 39 generates a read address based on the reference synchronization and the reference clock, and the discretized data specified by the read address is sequentially read out from the memory 38 at the timing of the reference clock. Then, the read discretized data is converted into analog data using a reference clock by a D/A converter (D/A in the figure) 4O.

In this way, the time axis correction circuit writes the discretized data to the memory 38 using the write clock corrected for the phase error, and reads it using the reference clock, so that a reproduced signal with no time axis error can be obtained. It has become.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, due to a limit in the physical accuracy of the elements constituting the phase modulation circuit 35, the correction ability cannot follow extremely small phase fluctuations, resulting in residual errors. Additionally, the above conventional technology has the problem that as the relative speed between the recording medium and the reproducing head increases, a speed error occurs, and time axis correction for this error is not sufficiently performed. There is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and aims to reduce residual errors and further improve the ability to correct speed errors.

[Means to solve the problem]

The time axis correction circuit according to the present invention includes a phase error detection means for detecting a phase error based on a horizontal synchronization signal separated from a reproduction signal, an A/D conversion means for converting the reproduction signal into a digital signal, and an A/D conversion means for converting the reproduction signal into a digital signal. holding means for holding data of the reproduced signal digitized by the D-converting means; write control means for controlling writing of the data of the reproduced signal into the holding means at a timing corrected based on the phase error;
A timer comprising readout control means for controlling readout of reproduction signal data from the holding means at a reference timing, and D/A conversion means for converting into analog data the reproduction signal data read from the holding means. In the axis correction circuit,
In order to solve the above problems, the present invention is characterized by the following features.

That is, the time axis correction circuit according to claim 1 of the scope of the present invention is provided as an auxiliary holding means provided before the holding means and holding the data of the reproduced signal digitized by the A/D converting means. , -1 Write/read control means for controlling writing in the auxiliary holding means at the reference timing, and controlling reading from the auxiliary holding means at a timing obtained by dividing the reference timing by a predetermined frequency division ratio. It is equipped with

Further, the time axis correction circuit according to claim 2 of the present invention includes:
In addition to the time axis correction circuit according to claim 1, further comprising speed error detection means for detecting a speed error occurring in the relative speed between the recording medium and the reproducing head based on the horizontal synchronization signal, The control means is configured to control writing at a phase that corresponds to the speed error.

[For production]

”- In the time base correction circuit according to claim 1, the A/D
The data of the reproduced signal outputted from the conversion means is written to the auxiliary holding means at a reference timing by the write/read control means, and read out at a timing obtained by dividing the reference timing by a predetermined frequency division ratio C. The time axis is expanded.

Further, the data of this reproduced signal is written into the holding means under the control of the write control means at a timing corrected based on the phase error detected by the first stage of phase error detection. Then, the data of the reproduced signal held in the holding means is read out at the reference timing determined by the reference synchronization and the accuracy of the reference clock by the first stage of readout control, is time-axis compressed, and is compressed in the time axis.
The signal is converted into analog by the /A conversion means and output as a reproduced signal without time axis error.

As described above, according to the time axis correction circuit according to claim 1, the time axis is expanded by the auxiliary holding means and the write/read control means before the data of the reproduced signal is written into the holding means. , the time axis error is also expanded in the same way. Therefore, it is possible to correct the time axis within the limits of circuit accuracy even for extremely small phase fluctuations, and residual errors can be reduced.

Further, according to the time axis correction circuit according to the second aspect of the present invention, it is possible to reduce the residual error similarly to the time axis correction circuit according to the first aspect of the present invention, and the write control means can reduce the speed. Since the writing of data of the reproduced signal is controlled with a phase according to the speed error detected by the error means, the speed error is distributed, and the time axis of the speed error is expanded in the same way as the above-mentioned time axis error. , the ability to correct speed errors can be improved.

[Embodiment 1] An embodiment according to claim 1 of the present invention will be described below based on FIG. 1.

As shown in FIG. 1, the time base correction circuit according to the present embodiment includes a synchronous separation circuit 1, an A/D converter (A, /D in the figure) 2,
It is composed of a D/A converter (D/A in the figure) 3, a frequency divider 4, and processing circuits 5 compatible with two-channel recording. In addition, in the same figure, illustration of one of the processing circuits 5 and 5 is omitted for convenience.

The synchronization separation circuit 1 is a circuit that separates a horizontal synchronization signal from a reproduced signal (for example, a video signal). The A/D converter 2 as an A/D conversion means is a circuit that converts the -F reproduction signal into digital data and outputs it as reproduction signal data (hereinafter referred to as M defeat data in the description of the embodiment). . The D/A converter 3 as a D/A conversion means is a circuit that converts the discretized data output from the processing circuits 5 into analog and returns it to a reproduction signal. The frequency divider 4 is a circuit that divides a reference clock generated by crystal oscillation at a predetermined frequency division ratio.

The processing circuit 5 includes memories 6 and 7, a write/read control section 8, a phase error detection circuit 9, a delay circuit 1o, a write control section 11, and a read address generation circuit 12.

The memory 6 as an auxiliary holding means and the memory 7 as a holding means are storage circuits that write and read the discretized data output from the A/D converter 2 for each horizontal scanning period (H).

The write/read control unit 8 as a write/read control means includes a write address generation circuit 13, a frequency divider 14, and a read address generation circuit 15.

The write address generation circuit 13 is a circuit that generates an address when writing discretized data to the memory 6 based on the horizontal synchronization signal and the reference clock separated by the synchronization separation circuit 1. , is a circuit that divides the frequency of the horizontal synchronizing signal with the same frequency division ratio as the frequency divider 4. The read address generation circuit 15 receives a horizontal synchronization signal (hereinafter referred to as a divided synchronization signal) whose frequency is divided by the frequency divider 14 and a reference clock signal (hereinafter referred to as a divided clock) whose frequency is divided by the frequency divider 4. ) is a circuit that generates an address when reading discretized data from the memory 6.

The phase error detection circuit 9 as a phase error detection means is a circuit that detects a phase error of one cycle or less and a phase error of one cycle or more of a frequency-divided clock based on a frequency-divided synchronization signal and discretized data. The delay circuit 10 is a circuit that delays discretized data in accordance with the delay in the detection operation in the phase error detection circuit 9.

The write control unit 11 as a write control means is W.

It consists of a zero correction circuit 16, a phase modulation circuit 17, and a write address generation circuit 18. W.

The Zero correction circuit 16 specifies the zero address when writing the discretized data to the memory 7 based on the phase error of one period or less of the divided clock among the phase errors output from the phase error detection circuit 9. .

This circuit corrects the phase of Zevo from a phase error of one cycle or more to a phase error of one cycle or less. On the other hand, the phase modulation circuit 17 is a circuit that corrects a phase error of one cycle or more of the frequency-divided clock from the phase error detection circuit 9 to one cycle or less, modulates the frequency-divided clock with this phase error, and outputs it as a modulated clock. It is.

The write address generation circuit 18 has W, Zer.

This circuit generates an address for writing discretized data into the memory 7 based on W and Zero output from the correction circuit 16 and a modulation clock output from the phase modulation circuit 17.

The read address generation circuit 12 serving as read control means is a circuit that generates an address when reading discretized data from the memory 7 based on a reference clock and reference synchronization.

In the above configuration, the input reproduction signal is sampled by the A/D converter 2 using the reference clock and converted into discretized data, and the synchronization separation circuit 1 separates the horizontal synchronization signal. This horizontal synchronization signal is input to the write address generation circuit 13, and is also input to the frequency divider 14.
The frequency of the signal is divided by , and input to the read address generation circuit 15 .

Then, the discretized data is written into the memory 6 at the write address generated by the write address generation circuit 13 in units of IH at the timing of the reference clock.

Next, the discretized data written in the memory 6 is sequentially read out from the data specified by the read address generated by the read address generation circuit 15 at the timing of the divided clock supplied from the frequency divider 4. At this time, for example, if the frequency-divided clock and frequency-divided synchronization signal are frequency-divided at a frequency division ratio of 1/N, the discretized data read from the memory 6 will be time-axis expanded by N times. Become.

Further, the phase error detection circuit 9 detects a phase error of one period or less and a phase error of one period or more of the divided clock based on the frequency-divided synchronization signal and the discretized data from the A/D converter 2. . In the W, ZerO correction circuit 16, the phase of W, Zero is corrected based on the above phase error, and in the phase modulation circuit 17, the phase of the divided clock is modulated with the correction error corrected to one period or less of the divided clock, and the phase is modulated. Become. When W, Zero and the modulated clock obtained as described above are input to the write address generation circuit 18, a write address is generated from there.

On the other hand, the discretized data read from the memory 6 is delayed by a delay circuit 10 and synchronized with the write address, and the modulated clock is set as the write clock Wck to the write address of the memory 7. Each IH is written. Then, the discretized data in the memory 7 is sequentially read out at the timing of the reference clock from the data specified by the read address generated by the read address generation circuit 12, so that 1. /N, the signal is compressed on the time axis, returned to the original time axis, converted into an analog signal by the D/A converter 3, and outputted as a playback signal with a stable time axis.

In this way, in this embodiment, the time axis of the discretized data is expanded by writing the discretized data into the memory 6 using the reference clock and reading it using the divided clock, so the time axis error is also expanded in the time axis. Even a very small time axis error can be easily corrected.

[Embodiment 2] Next, an embodiment of the time axis correction circuit according to claim 2 of the present invention will be described below based on FIG. 2. Note that circuits having the same functions as those of the circuit of Example 1 will be denoted by the same reference numerals, and a description thereof will be omitted.

As shown in FIG. 2, the time base correction circuit according to this embodiment includes a synchronous separation circuit 1, an A/D converter 2, a D/A converter 3,
It is composed of a frequency divider 4 and processing circuits 5' and 5'. The processing circuit 5' includes a write/read control section 8, a phase error detection circuit 9, a delay circuit 10, and a write address generation section 11'.
, read address generation circuit 12 and speed error detection circuit 1
It has 9. In addition, in the figure, for convenience, the processing circuit 5
The illustration of one of ' and 5' is omitted.

The write address generation section 11' includes a multiphase clock generation circuit 20 and a selection control circuit 21 in addition to the configuration of the write address generation circuit 11 of the tenth embodiment shown in FIG. The multiphase clock generation circuit 20 includes a phase modulation circuit 17
This circuit generates a plurality of clocks whose phases are changed by 1/a times per line of the reproduced signal based on the modulated clock from the oscilloscope. The selection control circuit 21 includes the speed error detection circuit 1
This circuit selects and outputs the multiphase clock according to the speed error detected by 9.

The speed error detection circuit 19 is a circuit that detects a speed error, which is an error in the relative speed between a tape as a recording medium (not shown) and a playback head, from the frequency-divided synchronization signal from the frequency divider 14.

In the above configuration, the input reproduction signal is converted into discretized data by the A/D converter 2, and the horizontal synchronization signal is separated by the synchronization separation circuit 1. The discretized data is transmitted to the write/read control circuit 8 based on this horizontal synchronization signal.
The data is written into the memory 6 under the control of , and read out sequentially after writing.

Further, the phase error detection circuit 9 detects a phase error based on the discretized data from the A/D converter 2 and the frequency-divided synchronization signal from the frequency divider 14. Based on this phase error,
The W and Zero correction circuit 16 corrects the phase of W and Zero, and the phase modulation circuit 17 outputs a modulated clock obtained by phase modulating the reference clock. Multiphase clock generation circuit 2
0, clocks with different phases are generated by the modulated clock. From this clock, the selection control circuit 21 selects a write clock Wck corresponding to the speed error detected by the detection circuit 21 from the frequency-divided synchronization signal.
is output as

On the other hand, the discretized data that has been read out from the memory 6 and expanded on the time axis is delayed through the delay circuit 10, and then the write clock W is applied to the write address of the memory 7. Written by. The discretized data in the memory 7 is read out sequentially using the read address from the read address generation circuit 12 and the reference clock, thereby compressing the time axis.
The signal is converted into an analog signal by the /A converter 3 and output as a playback signal with a stable time axis.

As described above, according to this embodiment, by using the clock of the multiphase clock generation circuit 20 as the write clock Wck, speed errors are dispersed and correction is performed evenly over one line of discretized data. Become. In addition, at this time, by expanding the time axis of the discretized data, the physical accuracy of the elements constituting the multiphase clock generation circuit 20 hardly becomes a problem, and by compressing the time axis when reading the memory 7, the result is As a result, the correction accuracy is improved to the same degree as the above-mentioned time axis extension.

〔Effect of the invention〕

As described above, the time axis correction circuit according to claim 1 of the present invention is provided in the preceding stage of the above-mentioned holding means, and is an auxiliary holding circuit for holding the data of the reproduced signal digitized by the above-mentioned A/D conversion means. and write/read control means for controlling writing in the auxiliary holding means at the reference timing and controlling reading from the auxiliary holding means at a timing obtained by dividing the reference timing by a predetermined frequency division ratio. This configuration has the following features.

As a result, the time axis is extended by the auxiliary holding means and the write/read control means before the data of the reproduced signal is written into the holding means, so that even slight phase fluctuations can be maintained within the limits of circuit accuracy. It is possible to correct the time axis and reduce the residual error.Therefore, it is possible to reduce the residual error and improve the ability to correct the time axis.

In addition to the time axis correction circuit according to claim 2, the time axis correction circuit according to claim 2 further includes a speed that is generated in the relative velocity between the recording medium and the reproducing head based on the horizontal synchronization signal. A speed error detection means for detecting an error is provided, and the write control means is configured to control writing at a phase according to the speed error.

As a result, similar to the time axis correction circuit according to claim 1, it is possible to reduce the residual error, and also to disperse the speed error, and furthermore, the speed error can be reduced in the same way as the time axis error. Since it is expanded, it is possible to improve the ability to correct speed errors, and it is possible to perform time axis correction with higher accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a time axis correction circuit according to claim 1 of the present invention. FIG. 2 is a block diagram showing the configuration of a time axis correction circuit according to claim 2 of the present invention. FIG. 3 is a block diagram showing the configuration of a conventional time axis correction circuit. 1 is a synchronous separation circuit, 2 is an A/D converter (A/D conversion means), 3 is a D/A converter (D/A conversion means), 4 is a frequency divider, and 6 is a memory (auxiliary holding means). , 7 is a memory (holding means), 8 is a write/read control section (write/read control means), 9
is a phase error detection circuit (phase error detection means), 11.11
' is a write control section (write control means), 12 is a read address generation circuit (read control means), and 19 is a speed error detection circuit (
speed error detection means), 20 is a multiphase clock generation circuit, 2
1 is a selection control circuit.

Claims (1)

[Claims] 1. Phase error detection means for detecting a phase error based on a horizontal synchronization signal separated from a reproduced signal, A/D conversion means for converting the reproduced signal into a digital signal, and this A/D conversion. holding means for holding data of the reproduced signal digitized by the holding means; write control means for controlling writing of data of the reproduced signal into the holding means at a timing corrected based on the phase error; A time axis correction device comprising a readout control means for controlling readout of data of a reproduction signal from the means at a reference timing, and a D/A conversion means for converting data of the reproduction signal read from the holding means into analog. In the circuit, an auxiliary holding means is provided upstream of the holding means and holds the data of the reproduced signal digitized by the A/D conversion means; and write/read control means for controlling readout of the auxiliary holding means at a timing obtained by dividing the reference timing by a predetermined frequency division ratio. 2. Speed error detection means for detecting a speed error occurring in the relative speed between the recording medium and the reproducing head based on the horizontal synchronization signal, and the write control means performs writing at a phase corresponding to the speed error. The time axis correction circuit according to claim 1, wherein the time axis correction circuit is configured to perform control.