JPH0443717A - Frequency conversion circuit with phase locked loop - Google Patents

Abstract

PURPOSE:To minimize the phase deviation time of an output when a fault such as 1-bit missing takes place in an input signal by providing a 1st frequency divider circuit, a 2nd frequency divider circuit, an interruption detection section and a switching section on this frequency conversion circuit. CONSTITUTION:When the interruption of an input signal to a phase locked loop 250 is restored normally, the output of a 2nd frequency divider circuit 270 is fed to a 1st frequency divider circuit 260 via a switching section 280 to reset the 1st frequency divider circuit 260 and the input signal to the phase locked loop 250 is fed dispersedly to the 1st frequency divider circuit 260. The 1st frequency divider circuit 260 divides the frequency of the input signal to a prescribed frequency and gives its output to a 2nd frequency divider circuit 270 via the switching section 280 to reset the 2nd frequency divider circuit 270. Thus, even when a fault such as 1-bit missing takes place, the phase deviation time of the output is minimized.

Description

[Detailed Description of the Invention] [Summary] Regarding a frequency conversion circuit using a phase-locked loop, a phase-locked loop that minimizes the phase shift of the output when a failure such as one bit missing occurs in the input signal. The purpose is to provide a frequency conversion circuit using a phase-locked loop that matches the output phase to the phase of an input signal of a constant frequency and outputs a signal of a predetermined frequency, and a phase-locked loop that branches the input signal to the phase-locked loop. In addition, there is a first frequency divider circuit that divides the frequency to a constant frequency and outputs it, and resets by inputting the output of the first frequency divider circuit. In a frequency conversion circuit using a phase-locked loop having a second frequency dividing circuit that outputs a signal, when the input signal to the phase-locked loop is normal, the input signal is added to the phase-locked loop and the first frequency dividing circuit. , when the input signal is disconnected, the output of the first and second frequency dividing circuits is inputted, and the output of the first and second frequency dividing circuits is input, and the input signal is input to the phase-locked loop. During normal operation, the input from the first frequency divider circuit is added to the second frequency divider circuit, and when the input signal is interrupted, the input from the second frequency divider circuit is added to the second frequency divider circuit according to the output disconnection detection signal of the disconnection detection section. A switching section for resetting the second frequency dividing circuit is provided, and when the interruption of the input signal is restored normally, the first frequency dividing circuit is reset by the output of the switching section, and the first frequency dividing circuit is reset. The configuration is such that the output is applied to the second frequency dividing circuit via the switching section and the second frequency dividing circuit is reset.

[Industrial application field]

The present invention relates to an improvement in a frequency conversion circuit using a phase-locked loop (hereinafter referred to as PLL).

At this time, when a failure occurs in the input signal such as one bit/node dropout, a PL that keeps the output phase shift to a minimum time is used.
There is a demand for a frequency conversion circuit using L.

[Prior Art] FIG. 3 is a block diagram showing the configuration of an example subscriber system.

FIG. 4 is a block diagram showing the configuration of a conventional frequency conversion circuit.

FIG. 3 shows an example of the configuration of a subscriber system. In the figure, signals from telephones 1-1 to 1-n are transmitted via a switch 2 in a telephone office A to a multiplexer (hereinafter referred to as MUX) 3. to multiplex signal data of multiple channels.
In this case, the clock from upper station B is transferred to the MUX of telephone station A.
Based on this clock, the clock supply circuit 4 generates clocks of various frequencies, and supplies them to the MUX 3 and the exchange 2 to multiplex the signal data.

In addition, as a means of supplementing when the output of the clock supply circuit 4 is insufficient, a frequency conversion circuit 5 described herein is provided.
The output of is used.

FIG. 4 shows an example of the frequency conversion circuit, in which a clock having a frequency of, for example, 8 KHz is input from the clock supply circuit 4 to the PLL 6 in the frequency conversion circuit 5. The PLL 6 applies the 8 KHz input clock to one input terminal of a phase comparator (hereinafter referred to as PC) 9.

The other input terminal of PC9 is connected to a voltage controlled oscillator (hereinafter ■
For example, the frequency of the output of 11 (referred to as CO) is 8 MHz.
A signal whose frequency is divided to 1/1000 (its frequency is 8 KHz) is inputted via the frequency dividing circuit 12.

Then, on the PC9, compare the phases of the two and find the difference.
A voltage proportional to the difference is output to a low pass filter (hereinafter referred to as LPF) 10. The LPFIO passes only the DC component of the input voltage and outputs it to the above-mentioned VCOII. V
The COII changes the output frequency from 8 MHz according to the above-mentioned input DC voltage component and outputs it.

In this way, a signal having a frequency of, for example, 8 MHz, whose phase is matched to the phase of the input signal to the PLL 6, is output. The output of the PLL 6 is converted into a clock pulse via a slice amplifier (not shown), and is output to a subsequent circuit (not shown), as well as to a frequency divider circuit 8 consisting of, for example, a counter. For example, the frequencies 64 KHz, 8 KHz and 0.4 KHz are determined by the frequency divider circuit 8, respectively.
The frequency of the clock is divided into clocks (1), (2), and (3) and output to a subsequent circuit (not shown).

In this case, the input signal to the PLL 6 (H2 at frequency 8) is branched and inputted to the frequency divider circuit 7 consisting of a counter, for example, and the frequency is divided to a frequency of 0.4 KHz, and the output is sent to the frequency divider port 'll18. It was output as a reset signal. This resets the frequency dividing circuit 8, which divides the frequency of the input signal from the PLL 6 and outputs the frequency.

[Problem to be solved by the invention]

However, in the above circuit configuration, when a failure occurs in the input clock of the active system (N) to the PLL 6, such as one pin loss, the input clock is switched to the input clock of the backup system (E) (not shown). Failures such as one bit missing may occur in the signal. In this case, the output signal of PLL6 itself is free-running, so no abnormality will occur, but the output reset signal of low frequency output signals such as ■, ■, and ■ created by dividing the output signal of PLL6 will be abnormal. There was a problem that there was a large phase shift.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a frequency conversion circuit using a phase-locked loop that minimizes the phase shift of the output when a failure such as one bit loss occurs in the input signal.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, there is a phase-locked loop 250 that matches the output phase to the phase of an input signal of a constant frequency and outputs a signal of a predetermined frequency, and a phase-locked loop 250 that outputs a signal of a predetermined frequency. The first frequency dividing circuit 260 divides and outputs the frequency, and the output of the first frequency dividing circuit 260 is input and reset, and the output of the phase locked loop 250 is branched and added to generate a signal of a predetermined frequency. In a frequency conversion circuit using a phase-locked loop having a second frequency dividing circuit 270 that outputs, when the input signal to the phase-locked loop 250 is normal, 220 transmits the input signal to the phase-locked loop 250 and the first frequency dividing circuit. In addition to 260, when the input signal is interrupted, it is a disconnection detection section that detects the disconnection of the input signal and outputs a disconnection detection signal to the switching section 280.

Moreover, 280- is the first and second frequency dividing circuit 260.270
When the input signal to the phase-locked loop 250 is normal, the input from the first frequency dividing circuit 260 is input, and when the input signal is interrupted, the input from the second frequency dividing circuit 260 is input by the interruption detection signal of the output of the interruption detection section 220. This is a switching unit that adds the input from the frequency dividing circuit 270 to the second frequency dividing circuit 270 and resets the second frequency dividing circuit 270.

The disconnection detection section 220 and the switching section 280 are newly provided.

Then, when the disconnection of the input signal is restored to normal, the switching unit 280
The first frequency dividing circuit 260 is reset by the output of
The configuration is such that the output of the first frequency dividing circuit 260 is applied to the second frequency dividing circuit 270 via the switching section 280, and the second frequency dividing circuit 270 is reset.

[For production]

In FIG. 1, when the input signal to the phase-locked loop 250 is normal, the output of the first frequency dividing circuit 260 is
In addition to the second frequency divider circuit 270, the second frequency divider circuit 270 is reset via 0. And phase locked loop 2
50 is branched and added to the second frequency dividing circuit 270,
The second frequency dividing circuit 270 divides the frequency into a signal of a predetermined frequency and outputs the signal.

Further, when the input signal to the phase-locked loop 250 is interrupted, the output of the second frequency dividing circuit 270 is switched to the second frequency dividing circuit 2 via the switching section 280 based on the disconnection detection signal of the output of the disconnection detecting section 220.
In addition to 70, the second frequency dividing circuit 270 is reset.
Then, the output of the phase-locked loop 250 is branched and added to the second frequency divider circuit 270, and the second frequency divider circuit 270 divides the frequency into a signal of a predetermined frequency and outputs the signal.

When the disconnection of the input signal to the phase-locked loop 250 is restored normally, the output of the second frequency divider circuit 270 is transferred to the switching unit 2.
After resetting the first frequency dividing circuit 260 in addition to the first frequency dividing circuit 260 via 80, the first frequency dividing circuit 260
The input signal to the phase-locked loop 250 is branched and added to the phase-locked loop 250. The first frequency divider circuit 260 divides the frequency of the input signal into a constant frequency, and then applies the output to the second frequency divider circuit 270 via the switching unit 280, and resets the second frequency divider circuit 270. .

As a result, when a failure such as one bit is lost in the input signal, it is possible to keep the phase shift of the output to a minimum amount of time.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a frequency conversion circuit according to an embodiment of the present invention.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, for example, a bipolar/unipolar conversion circuit (not shown) converts a decoded bipolar input signal having a frequency of 64 KHz to a decoded bipolar input signal having frequencies of 64 KHz and 8K.
Converts to a Hz unipolar signal clock. These outputs are then input to disconnection detection units 21 and 22 in the frequency conversion circuit, respectively, to detect when an abnormality such as a one-bit drop in the input clock occurs. The disconnection detection section 21
When disconnection is not detected in PLL 23.
4 and 25.

In the PLL23, the frequency matched to the phase of the input clock is, for example, 1.544 Ml (the clock of the z signal,
The PLL 24 outputs a clock signal having a frequency of, for example, 6.312 MHz to a subsequent circuit (not shown). Further, the PLL 25 outputs a clock signal having a frequency of, for example, 8.192 MHz that matches the phase of the input clock to a subsequent circuit (not shown) and also outputs it to the frequency dividing circuit 27.

The frequency dividing circuit 27 divides the input clock to 64KH, for example.
z, 8 KHz and 0.4 KHz clocks ■, ■ and ■. In this case, the output of the disconnection detection section 22 is input to the frequency dividing circuit 26, which divides the frequency into a clock having a frequency of, for example, 0.4 KHz, and sends the output as a rese/node signal via the switching section 28 as described above. In addition to the frequency dividing circuit 27, the frequency dividing circuit 27 performs frequency division as described above in accordance with the phase of the input signal.

For example, suppose that a failure (disconnection) such as a loss of one focus occurs in an input port with a frequency of 64 KHz. (At this time, the manual input/output with a frequency of 8 kHz is also disconnected at the same time.) Then, the disconnection detection section 21 detects this by inputting the output of the PLL 25 (frequency is 8.192 MHz). Further, the disconnection detection section 22 also detects this by inputting the clock having a frequency of 64 KHz output from the frequency dividing circuit 27.

The disconnection detection signals of the outputs of the disconnection detection units 21 and 22 are output to the switching unit 28, and the switching unit 28 switches from the normal side a to the abnormal side, so that the frequency of the output of the frequency dividing circuit 27 is Q,
A 4 KHz clock is applied to the switching unit 28 as an auxiliary reset signal. In the switching section 28, the above-mentioned frequency dividing circuit 2
Adding the auxiliary reset signal of the output of 7 to the frequency dividing circuit 27,
The frequency dividing circuit 27 is reset.

Then, the disconnection detection unit 21.22 continues to operate the disconnection detection unit 21.22 until the disconnection of the input clock returns to normal (for example, a timer (not shown) provided in the disconnection detection unit 21.22 uses a clock with a frequency of 0.4 KHz for about 2 clocks). 22 supplies a disconnection detection signal to the switching unit 28 . After the abnormality recovery, the disconnection detection sections 21 and 22 stop outputting the disconnection detection signal, and at the same time, the switching section 28 differentiates the auxiliary reset signal output from the frequency divider circuit 27 by a differentiating circuit (not shown), and converts the differential signal into is added to the frequency divider circuit 26 on the input side, and the frequency divider circuit 26 is reset in accordance with the phase of the output of the frequency divider circuit 27. Then, the switching section 28
Switch the input from the abnormal side to the normal side a.

As a result, when a failure occurs in the input clock, such as a one-bit loss, the PLL absorbs the abnormality in the case of a one-bit or two-bit failure and continues to output a stable PLL output signal. has almost no effect. on the other hand,
The frequency divider circuit on the input side is affected by an abnormality in the input clock, but after the abnormality is recovered, the output reset signal (generated by the frequency divider circuit on the input side) can be restored using the auxiliary reset signal.

As a result, the output phase shift can be kept to a minimum time.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to suppress the phase shift of the output for a minimum period of time when a failure such as one bit missing occurs in the input signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a block diagram showing the configuration of a frequency conversion circuit according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of an example subscriber system. FIG. 1 is a block diagram showing the configuration of a conventional frequency conversion circuit. In the figure, 220 indicates a disconnection detection section, and 280 indicates a switching section. I32,<;

Claims (1)

[Claims] A phase-locked loop (250) that matches the phase of an input signal with a constant frequency and outputs a signal of a predetermined frequency, and a phase-locked loop (250) that branches the input signal to the phase-locked loop (250). In addition, a first frequency divider circuit (
260), and a second frequency dividing circuit (260) that inputs and resets the output of the first frequency divider circuit (260), branches and adds the output of the phase-locked loop (250), and outputs a signal of a predetermined frequency.
In a frequency conversion circuit using a phase-locked loop having a frequency dividing circuit (270), when the input signal to the phase-locked loop (250) is normal, the input signal is transmitted to the phase-locked loop (250) and the first In addition to the frequency dividing circuit (260), when the input signal is disconnected, a disconnection detection section (220) that detects disconnection of the input signal and outputs a disconnection detection signal to the switching section (280); When the input signal to the phase-locked loop (250) is normal, the input from the first frequency divider circuit (260) is input, and the input signal from the first frequency divider circuit (260) is input. At the time of disconnection, the second
a switching unit (280) that adds the input from the frequency dividing circuit (270) to the second frequency dividing circuit 270 and resets the second frequency dividing circuit (270), When the disconnection is restored normally, the switching unit (280)
The first frequency divider circuit (260) is reset by the output of the first frequency divider circuit (260), and the output of the first frequency divider circuit (260) is switched to the switching unit (
A frequency conversion circuit using a phase locked loop, characterized in that the second frequency dividing circuit (270) is reset in addition to the second frequency dividing circuit (270) via the second frequency dividing circuit (280).