JP2009212659A - Phase difference correction circuit and phase difference correction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accuracy for phase synchronization of reference clock between a working system and a standby system. <P>SOLUTION: A reference clock supply system is configured by a redundant structure of a clock supply circuit for the working system and a clock supply circuit for the standby system. The working system supplies a first reference clock, while the standby system supplies a second reference clock phase-synchronized to the first reference clock. The phase difference correction circuit includes a phase difference measurement portion. The phase difference measurement portion measures a phase difference between the first and the second reference clocks on a side which receives the first and the second reference clocks from the reference clock supply system, and feeds back information on the phase difference to the reference clock supply system. The phase difference correction circuit makes correction to phase synchronization operation for the first and the second reference clocks by the reference clock supply system, according to phase difference information. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a phase difference correction circuit, and more particularly, to a reference clock supply system that has a clock synchronization control unit that is formed with a redundant configuration of an active system and a standby system and that synchronizes the phase of the reference clock of the standby system with the reference clock of the active system. The present invention relates to a phase difference correction circuit and a phase difference correction method.

  In the reference clock supply system, which is formed by a redundant configuration of the active system and the standby system, and can continue to supply the reference clock to the outside without interruption by switching to the standby system even if a failure occurs in the active system, A standby system that performs phase synchronization of a reference clock is known.

  For example, in Patent Document 1, a phase difference between a clock generated by an active (active) crystal oscillator and a clock generated by a standby (standby) crystal oscillator is detected, and a network synchronous clock is detected. There has been proposed a clock supply device that corrects a phase difference with respect to a standby clock using the detected phase difference after switching and before switching operation. According to this clock supply device, it is possible to prevent a glitch from occurring in the clock supplied from the host device of the telecommunications carrier to the base station device.

  Patent Document 2 compares the phases of output clocks from the first and second phase-locked loop circuits with a phase comparator, digitally converts the result with an analog / digital converter, and is obtained by digital conversion. Based on the information, a clock generation circuit has been proposed that controls the filter coefficient of the digital filter in the second phase-locked loop circuit so that the phase difference of each input to the selection unit becomes zero. According to this clock generation circuit, it is said that the phase variation of the output clock can be suppressed when switching between the active and standby reference clocks.

  FIG. 8 is a configuration example of the reference clock supply system related to the above.

  The reference clock supply system 10 shown in the figure is formed by a redundant configuration of a clock supply circuit 100 on the active system side and a clock supply circuit 110 on the standby system side, and is a receiving system that is an external system from each of the clock supply circuits 100 and 110. 120 is supplied with the first and second reference clocks 1a and 1b.

  As shown in the figure, the clock supply circuit 100 on the active side includes a clock synchronization control unit 101, a VCXO (Voltage Controlled Xtal Oscillator) 102, a system control unit 103, and buffers 104, 105, and 106. Have. Similarly, the standby-side clock supply circuit 110 also includes a clock synchronization control unit 111, a VCXO 112, a system control unit 113, and buffers 114, 115, and 116. The reception system 120 includes a clock reception unit 121, a selector 122, and buffers 224 and 225.

  In the figure, 1a, 1a1, 1a2 are first reference clocks generated and output on the active system side, and 1b, 1b1, 1b2 are second reference clocks generated and output on the standby system side. Show. Further, 1c is a reference clock use permission signal supplied from the active system control unit 103 to the selector 122, and 1c1 is a reference clock use permission signal supplied from the standby system control unit 113 to the selector 122. Each is shown. Further, 1d indicates a use reference clock switching signal supplied from the selector 122 to the clock receiving unit 121.

  The standby-side clock supply circuit 110 causes the standby-system second reference clock 1b to be phase-synchronized with the active-system first reference clock 1a by the clock synchronization control unit 111, the VCXO 112, and the system control unit 113. Operate. In other words, the clock synchronization control unit 111 distributes and inputs the second reference clock 1b1 from the VCXO 112, while receiving the first reference clock 1a2 from the active VCXO 102 via the buffers 105 and 115, both The control voltage of the VCXO 112 is adjusted so that the phases of the reference clocks 1b1 and 1a2 are synchronized.

In the above configuration, during normal operation, the receiving system 120 uses the active first reference clock 1a via the clock receiving unit 121. When a problem occurs in the active system in this state, the system control unit 103 on the active system switches the reference clock use permission signal 1c output to the selector 122 from ON to OFF. The selector 122 recognizes the switching of the reference clock use permission signal 1c and switches the used reference clock switching signal 1d output to the clock receiving unit 121 from the active system reference clock selection state to the standby system reference clock selection state. As a result, the clock receiving unit 121 recognizes the switching of the used reference clock switching signal 1d, and changes the used reference clock of the receiving system 120 from the working first reference clock 1a to the standby second reference clock 1b. Switch.
JP 2002-141893 A JP 2003-05742 A

  However, in the clock supply device of Patent Document 1 and the clock generation circuit of Patent Document 2 described above, the standby reference clock is operated so as to be phase-synchronized with the active reference clock. In the clock receiving unit on the receiving system side which is the supplied external system, a phase difference is generated between both reference clocks.

  That is, as shown in FIG. 8 described above, the second reference clocks 1a2 and 1b1 used for phase synchronization on the standby side and the first reference clock 1a used by the clock reception unit 121 on the reception system 120 side. 1b, a phase error occurs by passing through the buffers 104 and 105 on the active system side, the buffers 114 and 115 on the standby system side, and the buffers 124 and 125 on the reception system 120 side. Accordingly, in the clock receiver 121 on the reception system 120 side, a phase difference is generated between the first reference clock 1a for the active system and the second reference clock 1b for the standby system, and the reference clock 1a for the active system and the standby system is used. There is a problem that the accuracy of the phase synchronization of 1b is lowered.

  An object of the present invention is to solve the above-described problems, and to provide a phase difference correction circuit and a phase difference correction method capable of improving the accuracy of phase synchronization between the reference clocks of the active system and the standby system.

  In order to achieve the above object, a phase difference correction circuit according to the present invention is formed with a redundant configuration of an active system and a standby system, supplies a first reference clock from the active system, and supplies the first reference clock from the standby system. A phase difference correction circuit of a reference clock supply system that supplies a second reference clock that is phase-synchronized with one reference clock, on the side that receives the first and second reference clocks from the reference clock supply system A phase difference measuring unit configured to measure a phase difference between the first and second reference clocks and to ford-back the phase difference information to the reference clock supply system, and according to the phase difference information, the reference clock The phase synchronization operation of the first and second reference clocks by the supply system is corrected.

  The phase difference measurement unit may be disposed in an external system that is communicably connected to the reference clock supply system.

  The reference clock supply system includes a first voltage controlled oscillator that oscillates the first reference clock according to an input control voltage, and a second voltage that oscillates the second reference clock according to the input control voltage. Two voltage controlled oscillators, and a clock synchronization control unit that controls a control voltage of the second voltage controlled oscillator so as to synchronize the phase of the second reference clock with the first reference clock. The phase synchronization operation by the clock synchronization control unit may be corrected according to the phase difference information.

  The clock synchronization control unit detects a phase difference between a first reference clock oscillated by the first voltage controlled oscillator and a second reference clock oscillated by the second voltage controlled oscillator. And a control voltage of the second voltage controlled oscillator so as to synchronize the phase of the second reference clock with the first reference clock according to the phase difference detected by the phase difference detection circuit and the phase difference detection circuit. You may have the phase-synchronization means to control.

  The reference clock supply system may further include means for controlling a control voltage of the first voltage controlled oscillator so as to synchronize the phase of the first reference clock with a reference clock supplied from the outside.

  The phase difference measurement unit may be disposed in each of a plurality of external systems that are communicably connected to the reference clock supply system.

  The phase difference correction method according to the present invention is formed with a redundant configuration of an active system and a standby system, and supplies a first reference clock from the active system and is phase-synchronized from the standby system to the first reference clock. A phase difference correction method for a reference clock supply system for supplying a second reference clock, wherein the first and second reference clocks are received on the side receiving the first and second reference clocks from the reference clock supply system. The phase difference between the reference clocks is measured, the phase difference information is ford-backed to the reference clock supply system, and the phases of the first and second reference clocks by the reference clock supply system according to the phase difference information It is characterized by correcting the synchronous operation.

  According to the present invention, the reference clock phase difference between the active system and the standby system of the reference clock supply system is monitored from the outside, and the phase synchronization operation of the reference clocks of the active system and the standby system is performed according to the phase difference. By applying the correction, it is possible to improve the accuracy of phase synchronization between the reference clocks of the active system and the standby system.

  Next, the best mode for carrying out the phase difference correction circuit and the phase difference correction method according to the present invention will be described in detail with reference to the drawings. In addition, about the component similar to FIG. 8 mentioned above, the same code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  FIG. 1 shows an overall configuration of a phase difference correction circuit of a reference clock supply system according to an embodiment of the present invention.

  The reference clock supply system 10 shown in FIG. 1 is formed with a redundant configuration of a clock supply circuit 100 on the active system side and a clock supply circuit 110 on the standby system side. A second reference clock 1b phase-synchronized with the first reference clock 1a is supplied from the system side clock supply circuit 110. The reference clock supply system 10 is connected to a receiving system 120, which is an external system thereof, so that communication is possible, and the first and second reference clocks 1a and 1b are individually supplied.

  In this configuration, the phase difference correction circuit according to the present embodiment monitors the phase difference between the first and second reference clocks 1a and 1b between the clock supply circuits 100 and 110 of both systems on the reception system 120 side. The result is fed back to the standby-side clock supply circuit 110 to correct the internal clock synchronization control unit 111. By doing so, the accuracy of phase synchronization of the first and second reference clocks 1a and 1b of the active system and the standby system is improved.

  As shown in FIG. 1, the working clock supply circuit 100 includes a clock synchronization control unit 101, a VCXO (first voltage controlled oscillator) 102, a system control unit 103, and buffers 104, 105, and 106. Yes. The standby-side clock supply circuit 110 also includes a clock synchronization control unit 111, a VCXO (second voltage controlled oscillator) 112, a system control unit 113, and buffers 114, 115, and 116. The reception system 120 includes a clock reception unit 121, a selector 122, and buffers 224 and 225.

  In the figure, reference numerals 1a, 1a1, and 1a2 denote active first reference clocks, and 1b, 1b1, and 1b2 denote standby second reference clocks, respectively. 1c is a reference clock use permission signal supplied from the active system control unit 103 to the selector 122, and 1c1 is a reference clock use permission signal supplied from the standby system control unit 113 to the selector 122. . Further, 1d indicates a use reference clock switching signal supplied from the selector 122 to the clock receiving unit 121.

  In addition to the above configuration, the phase difference correction circuit according to the present embodiment includes a phase difference detection unit 123 on the reception system 120 side. The phase difference detection unit 123 includes a use reference clock switching signal 1 d from the selector 122, an active first reference clock 1 a from the buffer 124, and a standby second reference clock 1 b from the buffer 125. Entered. The phase difference detection unit 123 detects the phase difference between the first reference clock 1a for the active system and the second reference clock 1b for the standby system distributed from both buffers 124 and 125, and the detection result is used as the phase difference. Information 1e1 is fed back to the standby clock supply circuit 110.

  Next, the operation of this embodiment will be described.

  First, the first and second reference clocks 1 a and 1 b are supplied to the reception system 120 in a redundant configuration including the active-system side clock supply circuit 100 and the standby-system side clock supply circuit 110. During normal operation, the clock receiver 121 uses the first reference clock 1a for the active system. Consider a case where a malfunction occurs in the active system during this normal operation. In this case, it is necessary to switch the reference clock to be used from the first reference clock 1a for the active system to the second reference clock 1b for the standby system. Therefore, the active system control unit 103 switches the reference clock use permission signal 1c from ON to OFF.

  Then, the selector 122 of the receiving system 120 recognizes the switching of the reference clock use permission signal 1c, and switches the use reference clock switching signal 1d from the active system reference clock selection state to the standby system reference clock selection state. As a result, the clock reception unit 121 and the phase difference detection unit 123 recognize the switching of the used reference clock switching signal 1d from the selector 122, and use the used reference clock used by the receiving system 120 as the second reference clock of the standby system. Switch to 1b.

  Here, as described above, the standby reference clock 1 b is phase-synchronized with the first reference clock 1 a of the active system 100. This phase synchronization control is performed by the clock synchronization control unit 111 of the standby system 110, the system control unit 113, and the phase difference detection unit 123 of the reception system 120.

  That is, the standby-side clock synchronization control unit 111 inputs the clocks 1a2 and 1b1 distributed from the active-system side VCXO 102 and the standby-system side 112, and uses the standby-system second reference clock 1b as the active-system second reference clock 1b. It operates so as to be phase-synchronized with the first reference clock 1a. That is, the standby side clock synchronization control unit 111 distributes and inputs the second reference clock 1b1 from the VCXO 112, and also passes the first reference clock 1a2 from the active side VCXO 102 via the buffers 105 and 115. The control voltage of the VCXO 112 on the standby system side is adjusted so that the phases of the input reference clocks 1b1, 1a2 of both systems are synchronized.

  In addition to the above operation, in the present embodiment, in the phase difference detection unit 123 on the reception system 120 side and the system control unit 113 on the standby system side, the phase difference detection unit 123 on the reception system 120 side is input to the clock reception unit 121. By monitoring the phase difference between the first reference clock 1a for the active system and the second reference clock 1b for the standby system and supplying the phase difference information 1e1 to the system control unit 113 on the standby system side, The standby clock synchronization control unit 111 is operated so as to improve the phase synchronization accuracy of the reference clocks 1a and 1b, and the control voltage of the VCXO 112 is adjusted.

  That is, based on the phase difference information 1e1 supplied from the phase difference detection unit 123 on the reception system 120 side, the standby clock synchronization control unit 111 controls the clock reception unit 121 under the control of the system control unit 113. When there is a phase difference between the input reference clocks 1a and 1b, the adjusted control voltage of the VCXO 112 is corrected so that the phase difference is zero. Thereby, the reference clocks 1a and 1b of both systems input to the clock receiving unit 121 are adjusted from the asynchronous state shown in FIG. 2A to the synchronous state shown in FIG.

  According to this, by performing phase synchronization control by the clock synchronization control unit 111, the system control unit 113, and the phase difference detection unit 123, the clock reception unit 121 determines the reference clock to be used as the first reference clock 1a of the working system. When switching from the second reference clock 1b to the standby system, the reference clock can be received without any problem without causing an error due to the phase difference between the two reference clocks 1a and 1b.

  Since this system has a redundant configuration, it is possible to invert the clock supply circuit 110 employed as the standby system to the active system and the clock supply circuit 100 employed as the active system to the standby system. In this case, contrary to the above, the reference clock 1a of the standby clock supply circuit 100 operates in phase with the reference clock 1b of the active clock supply circuit 110.

  As described above, in this embodiment, the phase difference detection unit 123 is provided on the reception system 120 side which is an external system to which the first and second reference clocks 1a and 1b are supplied from the reference clock supply system 10. . The phase difference detector 123 measures the phase difference between the first and second reference clocks 1a and 1b input to the clock receiver 121, and feeds back the measured difference information to the standby clock supply circuit 110. Accordingly, the standby clock supply circuit 110 sets the phase difference between the first and second reference clocks 1a and 1b to 0 based on the difference information measured by the phase difference detection unit 123 on the reception system 120 side. Can be corrected.

  Therefore, according to this embodiment, the active clock is used between the reference clocks 1a2 and 1b1 of both systems used for the phase synchronization on the standby system side and the reference clocks 1a and 1b of both systems used by the reception system 120. The phase error caused by passing through the system side buffers 104 and 105, the standby system buffers 114 and 115, and the reception system 120 side buffers 124 and 125 is greatly reduced. The accuracy of phase synchronization of the system reference clocks 1a and 1b can be improved.

  Next, embodiments of the present invention will be described with reference to FIGS. In addition, about the component similar to FIG. 1 mentioned above, the same code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  The reference clock supply system 10a shown in FIG. 3 is formed with a redundant configuration of a clock supply circuit 100a on the active system side and a clock supply circuit 110a on the standby system side. The reference clocks 1a and 1b are supplied.

  The clock supply circuit 100a on the active system side includes a phase difference detection circuit 131, a CPU (processor) 132, a digital / analog converter (hereinafter referred to as “D”) as a configuration corresponding to the clock synchronization control unit 101, the VCXO 102, and the system control unit 103 described above. / A converter ”) 133, VCXO 134, and two frequency dividers 135 and 136. In addition, as described above, buffers 104, 105, and 106 are provided. The standby-side clock supply circuit 110a has the same configuration as the active-system-side clock supply circuit 100, and includes a phase difference detection circuit 141, a CPU 142, a D / A converter 143, a VCXO 144, two frequency dividers 145, 146 and buffers 114, 115, and 116.

  The active side CPU 132 outputs a reference value VD1 of the control voltage input (hereinafter referred to as “VC (voltage control)”) of the VCXO 134 to the D / A converter 133. Similarly, the standby side CPU 142 also outputs the reference value VD2 of the control voltage input (hereinafter referred to as “VC (voltage control)”) of the VCXO 144 to the D / A converter 143.

  The D / A converter 133 on the active side outputs a frequency adjustment voltage V1 corresponding to the VC reference value VD1 of the VCXO 134. Similarly, the D / A converter 143 on the standby side outputs a frequency adjustment voltage V2 corresponding to the VC reference value VD2 of the VCXO 144.

  The VCXO 134 on the active side outputs a clock corresponding to the frequency adjustment voltage V1, and is supplied to the receiving system 120, the distributor 135 on the active side, and the distributor 146 on the standby side as reference clocks 1a, 1a1, and 1a2, respectively. Distribute. Similarly, the standby-side VCXO 144 outputs a clock corresponding to the frequency adjustment voltage V1, and serves as the reference clocks 1b, 1b1, and 1b2 to the receiving system 120, the standby distributor 145, and the active distributor 136, respectively. Distribute each.

  The two frequency dividers 135 and 136 on the active system side divide the inputted first and second reference clocks 1a1 and 1b2 by a frequency of 1 / N, and output them to the phase difference detection circuit 131. Similarly, the two frequency dividers 145 and 146 on the standby side divide the inputted first and second reference clocks 1b1 and 1a2 to a frequency of 1 / N, and output them to the phase difference detection circuit 141. .

  The phase difference detection circuit 131 on the active side measures the phase difference between the input first and second reference clocks 1a1 and 1b2, and notifies the CPU 132 of the phase difference. Similarly, the standby-system phase difference detection circuit 141 measures the phase difference between the input first and second reference clocks 1a1 and 1b2, and notifies the CPU 142 of the phase difference.

  The reception system 120a includes a clock reception circuit 121a, a selector circuit 122a, and a phase difference detection circuit 123a.

  The selector circuit 122a recognizes the use permission signals 1c and 1c1 from the CPUs 132 and 142, and outputs a clock switching signal 1d.

  The phase difference detection circuit 123a measures the phase difference between the active and standby reference clocks 1a and 1b, and outputs the phase difference information 1e and 1e1 to the CPUs 132 and 142.

  Next, the operation of this embodiment will be described.

  Here, with reference to an operation flowchart shown in FIG. 4, the flow until the phase synchronization of the first reference clock 1a for the active system and the second reference clock 1b for the standby system will be described.

  First, after the entire reference clock supply system 10 is activated, the active system is determined. Since the reference clock supply system 10 is formed in a redundant configuration, both of the two clock supply circuits 100 and 110 in FIG. 3 can be used as the active system. Here, it is assumed that one of the clock supply circuits 100a, whose start-up is completed early, is used as the active system and the other clock supply circuit 110a is used as the standby system (step S11).

  The clock supply circuit 100a on the active system side performs the following operation. The reference clock use permission signal 1c is sent from the active CPU 132 to the selector circuit 122a of the receiving system 120a. Thus, the selector circuit 122a recognizes that the clock supply circuit 100 is the active system, and uses the reference clock switching signal 1d so that the clock reception circuit 121a uses the first reference clock 1a from the clock supply circuit 100. Send. Here, the CPU 132 internally sets the VC reference value VD1 of the VCXO 134 as an initial value, and instructs the D / A converter 133 to use the reference value VD1. The D / A converter 133 converts the reference value VD1 that is a digital value into an analog value, and outputs the analog value to the VCXO 134 as the frequency adjustment voltage V1. As a result, the VCXO 134 generates a clock at a frequency corresponding to the frequency adjustment voltage V1 and supplies the first reference clocks 1a, 1a1, and 1a2 to the receiving system 120a, the active distributor 135, and the standby distributor 146, respectively. Output.

  Similarly, in the clock supply circuit 110a on the standby side, the CPU 142 has the VC reference value VD2 of the VCXO 144 inside, and the D / A converter 143 converts the reference value VD2 that is a digital value into an analog frequency adjustment voltage. Then, the VCXO 144 generates a clock at a frequency corresponding to the frequency adjustment voltage V2, and the second reference clocks 1b, 1b1, and 1b2 are received by the reception system 120a, the standby distributor 145, and the active distributor 136. Start output for each.

  As described above, the clock supply circuit 100a operating in the active system continues to output the first reference clock 1a having a constant frequency with reference to the reference value VD1 of the VC of the CPU 132.

  On the other hand, the clock supply circuit 110a operated in the standby system starts the phase synchronization work for the active system (step S12).

  That is, when the VCXO 134 and 144 start oscillating and the first and second reference clocks 1a2 and 1b1 for phase synchronization start to be supplied to the standby system, both reference clocks 1a2 and 1b1 are divided by the frequency dividers 145 and 146, respectively. The clocks α and β are supplied to the phase difference detection circuit 141 on the standby side. The phase difference detection circuit 141 measures the phase difference between the clocks α and β.

  Here, as shown in FIG. 5A, the standby-side phase difference detection circuit 141 counts the phase difference between the clocks α and β with the sampling clock M, and sets the phase difference count to γ as the CPU 142. Notice. Then, the CPU 142 sets the reference value VD2 of VC so that γ = 0, and instructs the D / A converter 143 to set the reference value VD2. Thereby, the D / A converter 143 converts the analog value to the frequency adjustment voltage V2 corresponding to the digital value VD2, and the VCXO 144 generates and outputs a clock corresponding to the frequency adjustment voltage V2.

  Next, after a lapse of a certain time (step S13), the standby-side phase difference detection circuit 141 measures the phase difference between the clocks α and β, and whether the phase difference count number γ is 0 clock (γ = 0). Confirm whether or not (step S14). As a result, if γ = 0 is not satisfied (NO), the process returns to step S13 and the same processing is performed. On the other hand, if it is confirmed that γ = 0 (YES), the phase difference detection circuit 123a on the reception system 120 side detects the phase difference between the first reference clock 1a for the active system and the second reference clock 1b for the standby system. (Step S15), and the result is reported to the standby CPU 142 as phase difference detection information 1e1.

  Here, as shown in FIG. 5B, if the phase difference between the first and second reference clocks 1a and 1b is Δ, the CPU 142 calculates the correction clock number X for Δ to be zero. The control method of the reference value VD2 of the CPU 142 is changed so that the phase difference count γ between the clocks α and β is always X (step S16).

  After a predetermined time has elapsed (step S17), the phase difference between the clocks α and β is measured, and it is confirmed whether or not the phase difference count number γ is equal to X clocks (γ = 0) (step S18). As a result, if γ = 0 is not satisfied (NO), the process returns to step S17 and the same processing is performed. On the other hand, if it is confirmed that γ = X (YES), the phase difference detection circuit 123a on the reception system 120 side again detects the phase difference between the first and second reference clocks 1a and 1b of both systems ( Step S19).

  Next, it is confirmed whether or not the phase difference between the first and second reference clocks 1a and 1b is 0 (step S20). As a result, if the phase difference between the first and second reference clocks 1a and 1b is not 0 (NO), the process returns to step S16 and the same processing is repeated. On the other hand, if the phase difference between the reference clocks 1a and 1b is 0 (YES), after a predetermined time has elapsed (step S21), the process returns to step S19 to detect the phases of the first and second reference clocks 1a and 1b. Do. As a result, when the phase difference between the first and second reference clocks 1a and 1b is Δ1, the phase difference information 1e1 is fed back to the CPU 142, and the CPU 142 adjusts the value of the correction clock number X to Δ1 so that Δ1 is 0. Is updated to X1, and the same control as described above is repeated.

  Therefore, according to this embodiment, the reference clock phase difference between the active system and the standby system is monitored from the external system to the reference clock supply system formed by the redundant configuration of the active system and the standby system. Then, by correcting the standby clock synchronization control unit, it is possible to improve the accuracy of phase synchronization between the reference clocks of the active system and the standby system.

(Modification)
As a modification of the embodiment shown in FIG. 1, a reference clock 1c is externally supplied to the active and standby clock synchronization control units 101 and 111 as shown in FIG. The present invention can also be applied to a configuration in which the working first reference clock 1a is phase-synchronized with the externally supplied reference clock 1c. Further, as shown in FIG. 7, the present invention can also be applied to a configuration in which a plurality of reception systems 120 exist and the phase difference detection unit 123 is individually arranged in each reception system 120.

  As mentioned above, although the Example of this invention was described in detail, this invention is not limited to the above-mentioned Example illustrated typically, and those skilled in the art will be based on description content of a claim. The present invention can be modified and changed into various modes without departing from the gist of the present invention. These modified examples and modified examples also belong to the scope of the right of the present invention.

  The present invention is formed by a redundant configuration of an active system and a standby system, and even if a malfunction occurs in the active system, it is possible to continue supplying the reference clock to the external system without interruption by switching to the standby system. The present invention can be applied to a phase difference correction circuit (including units, parts, devices, etc.) and a phase difference correction method of a reference clock supply system that performs phase synchronization of the reference clock in the system and the standby system.

It is a block diagram which shows the whole structure of the phase difference correction circuit of the reference clock supply system which concerns on embodiment of this invention. (A) And (b) is a timing chart explaining operation | movement of the phase difference correction circuit shown in FIG. It is a block diagram which shows the whole structure of the phase difference correction circuit which concerns on the Example of this invention. 4 is a flowchart for explaining the operation of the phase difference correction circuit shown in FIG. 3. (A) And (b) is a timing chart explaining operation | movement of the phase difference correction circuit shown in FIG. It is a block diagram which shows the structure in the case of making the phase difference correction circuit of the reference clock supply system which concerns on the modification of this invention phase-synchronize the reference clock of an active system with an external supply reference clock. It is a block diagram which shows a structure in case the phase difference correction circuit of the reference clock supply system which concerns on the modification of this invention has multiple receiving systems. It is a block diagram which shows the structure of the reference clock supply system of related technology.

Explanation of symbols

10, 10a Reference clock supply system 100, 100a Clock supply circuit (current system)
101 Clock synchronization controller (current system)
102, 112 VCXO (current system)
103, 113 System control unit (current system)
104, 105, 106 Buffer 110, 110a Clock supply circuit (standby system)
111 Clock synchronization controller (standby system)
112 VCXO (standby system)
113 System control unit (standby system)
114, 115, 116 Buffer (standby system)
120, 120a Reception system 121 Selector 121a Selector circuit 122 Clock receiver 122a Clock receiver circuit 123 Phase difference detector 123a Phase difference detector 124, 125 Buffer 131 Phase difference detector (active system)
132, 142 CPU (current system)
133, 143 Digital / analog converter (current system)
134, 144 VCXO (current system)
135, 136 Distributor (current system)
141 Phase difference detection circuit (preliminary system)
142 CPU (spare system)
143 Digital / analog converter (standby system)
144 VCXO (spare system)
145, 146 Distributor (standby system)

Claims (7)

A first reference clock is formed from a redundant configuration of the active system and the standby system, and a first reference clock is supplied from the active system and phase-synchronized with the first reference clock from the standby system. A phase difference correction circuit for a reference clock supply system,
The phase difference between the first and second reference clocks is measured on the side receiving the first and second reference clocks from the reference clock supply system, and the phase difference information is returned to the reference clock supply system. A phase difference measurement unit
According to the phase difference information, a phase difference correction circuit corrects the phase synchronization operation of the first and second reference clocks by the reference clock supply system.   The phase difference correction circuit according to claim 1, wherein the phase difference measurement unit is arranged in an external system that is communicably connected to the reference clock supply system. The reference clock supply system includes:
A first voltage controlled oscillator that oscillates the first reference clock according to an input control voltage;
A second voltage controlled oscillator that oscillates the second reference clock according to the input control voltage;
A clock synchronization control unit for controlling a control voltage of the second voltage controlled oscillator so as to synchronize the phase of the second reference clock with the first reference clock;
The phase difference correction circuit according to claim 1, wherein the phase synchronization operation by the clock synchronization control unit is corrected according to the phase difference information. The clock synchronization control unit
A phase difference detection circuit for detecting a phase difference between a first reference clock oscillated by the first voltage controlled oscillator and a second reference clock oscillated by the second voltage controlled oscillator;
Phase synchronization means for controlling a control voltage of the second voltage controlled oscillator so as to synchronize the phase of the second reference clock with the first reference clock according to the phase difference detected by the phase difference detection circuit. The phase difference correction circuit according to claim 3, further comprising:   The reference clock supply system further includes means for controlling a control voltage of the first voltage-controlled oscillator so as to synchronize the phase of the first reference clock with a reference clock supplied from outside. Item 5. The phase difference correction circuit according to Item 3 or 4.   6. The phase difference correction circuit according to claim 1, wherein the phase difference measurement unit is disposed in each of a plurality of external systems communicably connected to the reference clock supply system. . A first reference clock is formed from a redundant configuration of the active system and the standby system, and a first reference clock is supplied from the active system and phase-synchronized with the first reference clock from the standby system. A phase difference correction method for a reference clock supply system,
The phase difference between the first and second reference clocks is measured on the side receiving the first and second reference clocks from the reference clock supply system, and the phase difference information is returned to the reference clock supply system. Let
According to the phase difference information, a phase difference correction method for correcting the phase synchronization operation of the first and second reference clocks by the reference clock supply system.

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