JP2009284196A - Oscillation circuit, electronic device provided with oscillation circuit and control method of oscillation circuit - Google Patents

Oscillation circuit, electronic device provided with oscillation circuit and control method of oscillation circuit Download PDF

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JP2009284196A
JP2009284196A JP2008133948A JP2008133948A JP2009284196A JP 2009284196 A JP2009284196 A JP 2009284196A JP 2008133948 A JP2008133948 A JP 2008133948A JP 2008133948 A JP2008133948 A JP 2008133948A JP 2009284196 A JP2009284196 A JP 2009284196A
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phase difference
phase
oscillation circuit
signal
frequency
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Toshiichi Uchiyama
敏一 内山
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by turning phase synchronization between high precision oscillators to an intermittent operation. <P>SOLUTION: The oscillation circuit 1 includes: the high precision oscillator 100 of high frequency accuracy for outputting the reference signals Fref of a frequency to be a reference; a voltage controlled oscillator 110 for controlling the frequency of output signals Fout by a control voltage Vc; a phase comparison part 120 for detecting a phase difference between the phase of the reference signals Fref and the phase of the output signals Fout and outputting phase difference signals Po; a control voltage generation part 130 for generating the control voltage Vc on the basis of the phase difference signals Po; a switch circuit 140 for switching the connection of a power source VDD to the phase comparison part 120 to a connection state or a non-connection state; and a timer circuit 150 for outputting control signals Sw for turning the switch circuit 140 to the connection state in a period until prescribed time elapses from the point of time at which there is no more phase difference on the basis of the phase difference signals Po and turning the switch circuit 140 to the non-connection state at the time other than the period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、高精度な信号を出力する発振回路、発振回路を備えた電子機器及び発振回路の制御方法に関する。   The present invention relates to an oscillation circuit that outputs a highly accurate signal, an electronic device including the oscillation circuit, and a method for controlling the oscillation circuit.

一般に位相同期制御は、高精度の基準発振器とその精度に依存させようとする比較的安定度の悪い発振器を位相同期させることにより、任意の周波数で用意した後者の発振器の出力を高精度の基準発振器並みの安定度で得るための技術である。前者には原子発振器や恒温槽入り発振器(OCXO:Oven Controlled Xtal Oscillator)或いは有線、無線により供給される基準信号を用い、後者には電圧制御方式の水晶発振器(VCXO:Voltage Controlled Xtal Oscillator)やLC発振器などが用いられている。   In general, phase-locked control is performed by phase-locking a highly accurate reference oscillator and a relatively unstable oscillator that is dependent on the accuracy, so that the output of the latter oscillator prepared at an arbitrary frequency is a highly accurate reference. This is a technique for obtaining the same level of stability as an oscillator. The former uses an atomic oscillator, an oven controlled oscillator (OCXO) or a reference signal supplied by wire or wireless, and the latter uses a voltage controlled crystal oscillator (VCXO) or LC. An oscillator or the like is used.

一方、通信網などの広域インフラや放送システムなどで原子発振器同士を位相同期制御する場合があるが、位相同期制御は原子発振器同士の出力信号の位相差がずれていくのを検出して補正制御する方式であるため、両者の安定度が極めて高い場合、検出可能な位相差が生じるのに一定の時間経過が必要になる。   On the other hand, phase synchronization control of atomic oscillators is sometimes performed in wide-area infrastructure such as communication networks and broadcasting systems, but phase synchronization control detects and corrects the phase difference between the output signals of atomic oscillators. Therefore, when the stability of both is extremely high, a certain time elapses to generate a detectable phase difference.

この問題を解決するために、例えば特許文献1には、無線の間欠受信に対応した同期制御を行なうことにより、非動作時の周波数精度を確保する方法が記載されている。   In order to solve this problem, for example, Patent Document 1 describes a method of ensuring frequency accuracy during non-operation by performing synchronization control corresponding to wireless intermittent reception.

特表2007−528642号公報Special table 2007-528642 gazette

しかしながら、従来の方法では、高速デジタル通信などにおいて機器間の信号同期を常に一定に確保するために有用であるが、基準発振器の周波数精度を一定に保ったり、高精度時計として月単位、年単位で一定の周波数精度を保つためには過剰な制御となり、低消費電力化が必要な小型機器には適さないという課題がある。つまり、従来の方法を用いれば瞬時の周波数や位相精度が維持でき、その延長として長期的にも変化の少ない周波数信号が得られるものの、例えば1年後の周波数に対しては、周波数ゆらぎに代表される短期的な変動があったとしてもプラス側のゆらぎとマイナス側のゆらぎは相殺されてしまうので、長期的に考えた場合には過剰制御と言える。   However, the conventional method is useful for ensuring constant signal synchronization between devices in high-speed digital communications, etc., but the frequency accuracy of the reference oscillator can be kept constant, or a high-accuracy clock can be used on a monthly or yearly basis. However, in order to maintain a certain frequency accuracy, excessive control is required, and there is a problem that it is not suitable for small devices that require low power consumption. In other words, if the conventional method is used, the instantaneous frequency and phase accuracy can be maintained, and a frequency signal with little change in the long term can be obtained as an extension, but for the frequency after one year, for example, it is represented by frequency fluctuation. Even if there is a short-term fluctuation, the fluctuation on the positive side and the fluctuation on the negative side are offset, so it can be said that it is over-controlled when considered in the long term.

本発明は、上述の課題の少なくとも一部を解決するためになされたものであり、以下の形態または適用例として実現することが可能である。   SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[適用例1]
基準となる周波数の基準信号を出力する周波数確度が高い高精度発振器と、出力信号の周波数を制御電圧で制御する電圧制御発振器と、前記基準信号の位相と前記出力信号の位相との位相差を検出し位相差信号を出力する位相比較部と、前記位相差信号に基づき前記制御電圧を生成する制御電圧生成部と、前記位相比較部への電源の接続を接続状態または非接続状態に切り替えるスイッチ回路と、前記位相差信号に基づき前記位相差が無くなった時点から所定の時間が経過するまでの期間は前記スイッチ回路を前記接続状態にし、前記期間以外は前記スイッチ回路を前記非接続状態にする制御信号を出力するタイマ回路と、を含む、ことを特徴とする発振回路。
[Application Example 1]
A high-precision oscillator that outputs a reference signal of a reference frequency with high frequency accuracy, a voltage-controlled oscillator that controls the frequency of the output signal with a control voltage, and a phase difference between the phase of the reference signal and the phase of the output signal A phase comparison unit that detects and outputs a phase difference signal; a control voltage generation unit that generates the control voltage based on the phase difference signal; and a switch that switches connection of a power source to the phase comparison unit between a connected state and a disconnected state The switch circuit is set in the connected state during a period until a predetermined time elapses after the phase difference disappears based on the circuit and the phase difference signal, and the switch circuit is set in the non-connected state during other periods. An oscillation circuit comprising: a timer circuit that outputs a control signal;

この構成によれば、基準信号の位相と出力信号の位相とが同期した時点から所定の時間が経過するまでの期間は位相比較部への電源供給を非接続状態にすることができるので、低消費電力化を図ることができる。   According to this configuration, since the phase of the reference signal and the phase of the output signal are synchronized until the predetermined time elapses, the power supply to the phase comparison unit can be disconnected. Power consumption can be reduced.

[適用例2]
上記に記載の発振回路において、前記所定の時間は、前記電圧制御発振器の半周期を前記電圧制御発振器の1周期毎に発生する位相差で割って得られる時間以下に設定されることを特徴とする発振回路。
[Application Example 2]
In the oscillation circuit described above, the predetermined time is set to be equal to or less than a time obtained by dividing a half cycle of the voltage controlled oscillator by a phase difference generated every cycle of the voltage controlled oscillator. Oscillator circuit to perform.

この構成によれば、位相比較部への電源供給を非接続状態にする所定の時間の間に電圧制御発振器に起こり得る位相差を半周期以内に設定することにより基準信号に対して出力信号が遅れていると判断することができるので、電圧制御発振器の制御を確実に行うことができる。   According to this configuration, the output signal is output with respect to the reference signal by setting the phase difference that can occur in the voltage controlled oscillator within a predetermined period during the predetermined time when the power supply to the phase comparison unit is disconnected. Since it can be determined that there is a delay, the voltage controlled oscillator can be reliably controlled.

[適用例3]
上記に記載の発振回路において、前記タイマ回路は、前記位相差信号に基づき前記位相差が無くなった時点から次に前記位相差が検出される時点までの経過時間を計測し、前記経過時間に基づき前記所定の時間を設定することを特徴とする発振回路。
[Application Example 3]
In the oscillation circuit described above, the timer circuit measures an elapsed time from the time when the phase difference disappears to the next time when the phase difference is detected based on the phase difference signal, and based on the elapsed time. An oscillation circuit characterized in that the predetermined time is set.

この構成によれば、位相差が無くなってから再び位相差が検出されるまでの経過時間を計測し所定の時間を決められるので、製造ばらつきや経年劣化などを吸収し、高精度な発振回路を実現できる。   According to this configuration, it is possible to determine the predetermined time by measuring the elapsed time from when the phase difference disappears until the phase difference is detected again. realizable.

[適用例4]
上記に記載の発振回路において、前記発振回路は、高精度で動作させる場合は前記所定の時間を短く設定し、低精度で動作させる場合は前記所定の時間を長く設定することを特徴とする発振回路。
[Application Example 4]
In the oscillation circuit described above, the oscillation circuit sets the predetermined time short when operating with high accuracy, and sets the predetermined time long when operating with low accuracy. circuit.

この構成によれば、高精度で動作させる場合は所定の時間を短く設定することにより位相差の検出能力を高めることができ、低精度で動作させる場合は所定の時間を長く設定することにより低消費電力化を図ることができる。   According to this configuration, the phase difference detection capability can be enhanced by setting the predetermined time short when operating with high accuracy, and the time can be reduced by setting the predetermined time long when operating with low accuracy. Power consumption can be reduced.

[適用例5]
上記に記載の発振回路を備えたことを特徴とする電子機器。
[Application Example 5]
An electronic device comprising the oscillation circuit described above.

この構成によれば、基準信号の位相と出力信号の位相とが同期した時点から所定の時間が経過するまでの期間は位相比較部への電源供給を非接続状態にすることができるので、低消費電力化を図ることができる電子機器を提供できる。   According to this configuration, since the phase of the reference signal and the phase of the output signal are synchronized until the predetermined time elapses, the power supply to the phase comparison unit can be disconnected. An electronic device capable of reducing power consumption can be provided.

[適用例6]
基準となる周波数の基準信号を出力する周波数確度が高い高精度発振器と、出力信号の周波数を制御電圧で制御する電圧制御発振器と、前記基準信号の位相と前記出力信号の位相との位相差を検出し位相差信号を出力する位相比較部と、前記位相差信号に基づき前記制御電圧を生成する制御電圧生成部と、を含む発振回路の制御方法であって、前記位相差信号に基づき前記位相差が無くなった時点から所定の時間が経過するまでの期間は前記位相比較部への電源の接続を接続状態にし、前記期間以外は前記位相比較部への電源の接続を非接続状態にするスイッチ工程を含む、ことを特徴とする発振回路の制御方法。
[Application Example 6]
A high-precision oscillator that outputs a reference signal of a reference frequency with high frequency accuracy, a voltage-controlled oscillator that controls the frequency of the output signal with a control voltage, and a phase difference between the phase of the reference signal and the phase of the output signal A method for controlling an oscillation circuit, comprising: a phase comparison unit that detects and outputs a phase difference signal; and a control voltage generation unit that generates the control voltage based on the phase difference signal. Switch for connecting the power supply to the phase comparison unit during the period from when the phase difference disappears until a predetermined time elapses, and for disconnecting the power supply connection to the phase comparison unit during the period other than the period A method of controlling an oscillation circuit, comprising a step.

この構成によれば、基準信号の位相と出力信号の位相とが同期した時点から所定の時間が経過するまでの期間は位相比較部への電源供給を非接続状態にすることができるので、低消費電力化を図ることができる。   According to this configuration, since the phase of the reference signal and the phase of the output signal are synchronized until the predetermined time elapses, the power supply to the phase comparison unit can be disconnected. Power consumption can be reduced.

以下、発振回路の実施形態について図面に従って説明する。   Hereinafter, embodiments of the oscillation circuit will be described with reference to the drawings.

(第1実施形態)
<発振回路の構成>
先ず、第1実施形態に係る発振回路の構成について、図1を参照して説明する。図1は、第1実施形態に係る発振回路の構成を示す回路図である。
(First embodiment)
<Configuration of oscillation circuit>
First, the configuration of the oscillation circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit according to the first embodiment.

図1に示すように、発振回路1は、高精度発振器である原子発振器100と、電圧制御発振器(VCO:Voltage Controlled Oscillator)110と、位相比較部120と、制御電圧生成部130と、スイッチ回路140と、タイマ回路150と、から構成されている。なお、VCO110は、高精度かつ電圧制御可能な原子発振器や水晶発振器(VCXO:Voltage Controlled Xtal Oscillator)などを含む。   As shown in FIG. 1, an oscillation circuit 1 includes an atomic oscillator 100 that is a high-precision oscillator, a voltage controlled oscillator (VCO) 110, a phase comparison unit 120, a control voltage generation unit 130, and a switch circuit. 140 and a timer circuit 150. Note that the VCO 110 includes a highly accurate and voltage-controllable atomic oscillator, a crystal oscillator (VCXO), and the like.

位相比較部120は、原子発振器100が出力する基準信号Frefの周波数を1/R(Rは任意の整数)分周した分周信号Frを出力する1/R分周器121と、VCO110が出力する出力信号Foutの周波数を1/N(Nは任意の整数)分周した分周信号Fnを出力する1/N分周器122と、分周信号Frと分周信号Fnとの位相差を比較し位相差信号Poを出力する位相比較器123と、から構成されている。例えば、基準信号Frefの周波数が10MHz、出力信号Foutの周波数が500MHzだとすると、1/N分周器122の分周をN=50に設定すれば、1/R分周器121は必要なくなる。   The phase comparison unit 120 outputs a frequency division signal Fr obtained by dividing the frequency of the reference signal Fref output from the atomic oscillator 100 by 1 / R (R is an arbitrary integer), and the VCO 110 outputs The 1 / N frequency divider 122 that outputs a frequency-divided signal Fn obtained by dividing the frequency of the output signal Fout to be 1 / N (N is an arbitrary integer), and the phase difference between the frequency-divided signal Fr and the frequency-divided signal Fn. And a phase comparator 123 that compares and outputs a phase difference signal Po. For example, if the frequency of the reference signal Fref is 10 MHz and the frequency of the output signal Fout is 500 MHz, the 1 / R divider 121 is not necessary if the frequency division of the 1 / N divider 122 is set to N = 50.

制御電圧生成部130は、位相比較器123の出力する位相差信号Poがデジタルデータの場合にアナログデータPaに変換するためのデジタル−アナログ変換器(DAC:Digital Analog Converter)131と、アナログデータPaから低域周波数のみを通過させた制御電圧Vcを出力するローパスフィルタ(LPF:Low Pass Filter)132と、から構成されている。   The control voltage generator 130 includes a digital-analog converter (DAC) 131 for converting to analog data Pa when the phase difference signal Po output from the phase comparator 123 is digital data, and analog data Pa. And a low pass filter (LPF) 132 that outputs a control voltage Vc through which only a low frequency is passed.

スイッチ回路140は、位相比較部120への電源VDDの接続を接続状態または非接続状態に切り替える。   The switch circuit 140 switches the connection of the power supply VDD to the phase comparison unit 120 between a connected state and a disconnected state.

タイマ回路150は、位相差信号Poに基づき位相差が無くなった時点から所定の時間が経過するまでの期間はスイッチ回路140を接続状態にする制御信号Sw=Hレベルを出力し、それ以外の期間はスイッチ回路140を非接続状態にする制御信号Sw=Lレベルを出力する。所定の時間は、出力信号Foutの立ち上がりの回数をカウントし、立ち上がりの回数がn回(nは任意の整数)になるまでの時間で設定することができる。nの値は、タイマ回路150の図示しないレジスタに外部から書き換え可能で予め設定しておくことができる。例えば、出力信号Foutの立ち上がりから次の立ち上がりまでの周期をCkとすると、所定の時間はCk×nとなる。なお、nの値は、VCO110の半周期をVCO110の1周期毎に発生する位相差で割って得られる値以下に設定する。例えば、VCO110の半周期を0.05秒、VCO110の1周期毎に発生する位相差を1×10-6秒とすれば、n=0.05÷1×10-6=5000となる。 The timer circuit 150 outputs a control signal Sw = H level that keeps the switch circuit 140 connected during a period from when the phase difference disappears based on the phase difference signal Po until a predetermined time elapses, and other periods. Outputs a control signal Sw = L level that switches the switch circuit 140 to a disconnected state. The predetermined time can be set as a time until the number of rising times of the output signal Fout is counted and the number of rising times becomes n (n is an arbitrary integer). The value of n can be rewritten from the outside in a register (not shown) of the timer circuit 150 and can be set in advance. For example, if the period from the rising edge of the output signal Fout to the next rising edge is Ck, the predetermined time is Ck × n. Note that the value of n is set to a value obtained by dividing the half cycle of the VCO 110 by the phase difference generated for each cycle of the VCO 110. For example, if the half cycle of the VCO 110 is 0.05 seconds and the phase difference generated every cycle of the VCO 110 is 1 × 10 −6 seconds, then n = 0.05 ÷ 1 × 10 −6 = 5000.

<発振回路の動作>
次に、発振回路の動作について図2及び図3を参照して説明する。図2は、発振回路の動作を示すフローチャートである。図3は、発振回路の動作を示すタイミング図である。なお、図3のタイミング図は、説明を簡略化するために極端に分周信号Fnが変化する場合を例示しており、実際のVCO110では分周信号Fnが緩やかに単調に変化する。
<Operation of oscillation circuit>
Next, the operation of the oscillation circuit will be described with reference to FIGS. FIG. 2 is a flowchart showing the operation of the oscillation circuit. FIG. 3 is a timing chart showing the operation of the oscillation circuit. Note that the timing diagram of FIG. 3 exemplifies a case where the frequency-divided signal Fn changes extremely to simplify the description. In the actual VCO 110, the frequency-divided signal Fn changes gently and monotonously.

先ず、図2のステップS100では、タイマ回路150は、制御信号SwをHレベルに設定する。例えば、図3の時点t1で制御信号SwがHレベルに設定されたのでスイッチ回路140は接続状態となり、位相比較部120へ電源VDDが供給され、位相比較部120がON状態となる。位相比較部120がON状態となったので、位相比較器123により分周信号Frと分周信号Fnとの位相差を比較した位相差信号Poがタイマ回路150に出力される。   First, in step S100 of FIG. 2, the timer circuit 150 sets the control signal Sw to the H level. For example, since the control signal Sw is set to the H level at the time t1 in FIG. 3, the switch circuit 140 is connected, the power supply VDD is supplied to the phase comparison unit 120, and the phase comparison unit 120 is turned on. Since the phase comparator 120 is turned on, the phase comparator 123 outputs a phase difference signal Po obtained by comparing the phase difference between the frequency-divided signal Fr and the frequency-divided signal Fn to the timer circuit 150.

次に、ステップS102では、次の時点の位相差信号Poを読み込み、ステップS104に移行する。   Next, in step S102, the phase difference signal Po at the next time point is read, and the process proceeds to step S104.

次に、ステップS104では、読み込んだ位相差信号PoがHレベルであるか否かを判定し、Hレベルである場合はステップS106に移行し、Hレベルでない場合はステップS102に移行する。例えば、図3において、時点t2で読み込んだ位相差信号PoはLレベルなのでステップS102に移行し、時点t3で読み込んだ位相差信号PoはHレベルなのでステップS106に移行する。   Next, in step S104, it is determined whether or not the read phase difference signal Po is at H level. If it is at H level, the process proceeds to step S106, and if not, the process proceeds to step S102. For example, in FIG. 3, since the phase difference signal Po read at time t2 is L level, the process proceeds to step S102, and since the phase difference signal Po read at time t3 is H level, the process proceeds to step S106.

次に、ステップS106では、次の時点の位相差信号Poを読み込み、ステップS108に移行する。   Next, in step S106, the phase difference signal Po at the next time point is read, and the process proceeds to step S108.

次に、ステップS108では、読み込んだ位相差信号PoがLレベルであるか否かを判定し、Lレベルである場合はステップS110に移行し、Lレベルでない場合はステップS106に移行する。例えば、図3において、時点t4で読み込んだ位相差信号PoはHレベルなのでステップS106に移行し、時点t5で読み込んだ位相差信号PoはLレベルなのでステップS110に移行する。   Next, in step S108, it is determined whether or not the read phase difference signal Po is at the L level. If it is at the L level, the process proceeds to step S110, and if not, the process proceeds to step S106. For example, in FIG. 3, since the phase difference signal Po read at time t4 is at the H level, the process proceeds to step S106, and since the phase difference signal Po read at time t5 is at the L level, the process proceeds to step S110.

次に、ステップS110では、タイマ回路150は、制御信号SwをLレベルに設定する。例えば、図3の時点t5で制御信号SwがLレベルに設定されたのでスイッチ回路140は非接続状態となり、位相比較部120への電源VDDの供給が遮断され、位相比較部120がOFF状態となる。位相比較部120がOFF状態となったので、位相差信号PoはLレベルを維持する。   Next, in step S110, the timer circuit 150 sets the control signal Sw to the L level. For example, since the control signal Sw is set to the L level at time t5 in FIG. 3, the switch circuit 140 is disconnected, the supply of the power supply VDD to the phase comparison unit 120 is cut off, and the phase comparison unit 120 is turned off. Become. Since the phase comparison unit 120 is in the OFF state, the phase difference signal Po maintains the L level.

次に、ステップS112では、タイマ回路150は、内部カウンタの値Countを0に設定し、ステップS114に移行する。   Next, in step S112, the timer circuit 150 sets the value Count of the internal counter to 0, and proceeds to step S114.

次に、ステップS114では、タイマ回路150は、次の時点で内部カウンタの値Countに1を加算し、ステップS116に移行する。   Next, in step S114, the timer circuit 150 adds 1 to the value Count of the internal counter at the next time point, and proceeds to step S116.

次に、ステップS116では、タイマ回路150は、内部カウンタの値Countがn回以上か否かを判定し、n回以上の場合はステップS100に移行し、n回未満の場合はステップS114に移行する。例えば、図3において、時点t6では内部カウンタの値Count=1なのでステップS114に移行し、時点t7において内部カウンタの値Count=nとなったのでステップS100に移行する。   Next, in step S116, the timer circuit 150 determines whether the value Count of the internal counter is n times or more. If it is n times or more, the process proceeds to step S100. If it is less than n times, the process proceeds to step S114. To do. For example, in FIG. 3, since the internal counter value Count = 1 at time t6, the process proceeds to step S114. At time t7, the internal counter value Count = n is reached, so the process proceeds to step S100.

以上に述べた本実施形態によれば、以下の効果が得られる。   According to the present embodiment described above, the following effects can be obtained.

本実施形態では、基準信号の位相と出力信号の位相とが同期した時点から所定の時間が経過するまでの期間は位相比較部への電源供給を非接続状態にすることができるので、低消費電力化を図ることができる。   In this embodiment, the power supply to the phase comparison unit can be disconnected during a period from when the phase of the reference signal and the phase of the output signal are synchronized until a predetermined time elapses. Electricity can be achieved.

以上、発振回路の実施形態を説明したが、こうした実施の形態に何ら限定されるものではなく、趣旨を逸脱しない範囲内において様々な形態で実施し得ることができる。以下、変形例を挙げて説明する。   Although the embodiments of the oscillation circuit have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the scope of the invention. Hereinafter, a modification will be described.

(変形例1)発振回路の変形例1について説明する。前記第1実施形態では、nの値をタイマ回路150のレジスタに外部から予め設定しておくように説明したが、製造プロセスのばらつきなどにより一律に決められない場合がある。そこで、実際に発振回路1毎に位相差信号Poの位相差が無くなった時点から次に位相差が検出される時点までの経過時間を計測することにより、nの値をレジスタに書き込むようにしてもよい。   (Modification 1) Modification 1 of the oscillation circuit will be described. In the first embodiment, it has been described that the value of n is set in advance in the register of the timer circuit 150 from the outside. However, the value may not be determined uniformly due to variations in the manufacturing process. Therefore, by measuring the elapsed time from when the phase difference of the phase difference signal Po actually disappears for each oscillation circuit 1 to when the phase difference is detected next, the value of n is written to the register. Also good.

(変形例2)発振回路の変形例2について説明する。前記第1実施形態では、nの値を一種類に決めるように説明したが、例えば、発振回路1を高精度で動作させるモードと、低精度で動作させるモードとを切り替えて動作可能なように、それぞれのnの値を設定してもよい。   (Modification 2) Modification 2 of the oscillation circuit will be described. In the first embodiment, it has been described that the value of n is determined as one type. For example, the mode can be switched between a mode in which the oscillation circuit 1 is operated with high accuracy and a mode in which the oscillation circuit 1 is operated with low accuracy. The value of each n may be set.

(変形例3)発振回路の変形例3について説明する。前記第1実施形態では、図2に示すようにステップS108で位相差信号PoがHレベルからLレベルに変化した時点で判定するように説明したが、Lレベルに変化した時点の次の時点でHレベルに戻ることも想定し、ステップS108からステップS110に移行する前に、さらにステップS106とステップS108を挿入してもよい。このように構成すれば、同期判定精度を向上させることができる。   (Modification 3) Modification 3 of the oscillation circuit will be described. In the first embodiment, as illustrated in FIG. 2, the determination is made when the phase difference signal Po changes from the H level to the L level in step S108. However, at the next time after the change to the L level. Assuming that the level returns to the H level, step S106 and step S108 may be further inserted before shifting from step S108 to step S110. If comprised in this way, a synchronous determination precision can be improved.

(変形例4)発振回路の変形例4について説明する。発振回路1は、電子機器として腕時計、携帯電話、ノート型パーソナルコンピュータなどの基準時刻を発振するために搭載し、利用可能である。   (Modification 4) Modification 4 of the oscillation circuit will be described. The oscillation circuit 1 can be mounted and used to oscillate a reference time of a wristwatch, a mobile phone, a notebook personal computer, or the like as an electronic device.

第1実施形態に係る発振回路の構成を示す回路図。1 is a circuit diagram showing a configuration of an oscillation circuit according to a first embodiment. 発振回路の動作を示すフローチャート。The flowchart which shows operation | movement of an oscillation circuit. 発振回路の動作を示すタイミング図。FIG. 5 is a timing chart showing the operation of the oscillation circuit.

符号の説明Explanation of symbols

1…発振回路、100…原子発振器、110…VCO、120…位相比較部、121…1/R分周器、122…1/N分周器、123…位相比較器、130…制御電圧生成部、131…DAC、132…LPF、140…スイッチ回路、150…タイマ回路。   DESCRIPTION OF SYMBOLS 1 ... Oscillator circuit, 100 ... Atomic oscillator, 110 ... VCO, 120 ... Phase comparison part, 121 ... 1 / R frequency divider, 122 ... 1 / N frequency divider, 123 ... Phase comparator, 130 ... Control voltage generation part 131 ... DAC, 132 ... LPF, 140 ... switch circuit, 150 ... timer circuit.

Claims (6)

基準となる周波数の基準信号を出力する周波数確度が高い高精度発振器と、
出力信号の周波数を制御電圧で制御する電圧制御発振器と、
前記基準信号の位相と前記出力信号の位相との位相差を検出し位相差信号を出力する位相比較部と、
前記位相差信号に基づき前記制御電圧を生成する制御電圧生成部と、
前記位相比較部への電源の接続を接続状態または非接続状態に切り替えるスイッチ回路と、
前記位相差信号に基づき前記位相差が無くなった時点から所定の時間が経過するまでの期間は前記スイッチ回路を前記接続状態にし、前記期間以外は前記スイッチ回路を前記非接続状態にする制御信号を出力するタイマ回路と、
を含む、
ことを特徴とする発振回路。
A high-precision oscillator with high frequency accuracy that outputs a reference signal of a reference frequency,
A voltage controlled oscillator that controls the frequency of the output signal with a control voltage; and
A phase comparator that detects a phase difference between the phase of the reference signal and the phase of the output signal and outputs a phase difference signal;
A control voltage generator for generating the control voltage based on the phase difference signal;
A switch circuit that switches the connection of the power source to the phase comparison unit to a connected state or a disconnected state;
Based on the phase difference signal, a control signal for setting the switch circuit in the connected state for a period from when the phase difference disappears until a predetermined time elapses, and for setting the switch circuit in the non-connected state for other periods. An output timer circuit;
including,
An oscillation circuit characterized by that.
請求項1に記載の発振回路において、前記所定の時間は、前記電圧制御発振器の半周期を前記電圧制御発振器の1周期毎に発生する位相差で割って得られる時間以下に設定されることを特徴とする発振回路。   2. The oscillation circuit according to claim 1, wherein the predetermined time is set to be equal to or less than a time obtained by dividing a half cycle of the voltage controlled oscillator by a phase difference generated for each cycle of the voltage controlled oscillator. Features an oscillation circuit. 請求項1に記載の発振回路において、前記タイマ回路は、前記位相差信号に基づき前記位相差が無くなった時点から次に前記位相差が検出される時点までの経過時間を計測し、前記経過時間に基づき前記所定の時間を設定することを特徴とする発振回路。   2. The oscillation circuit according to claim 1, wherein the timer circuit measures an elapsed time from the time when the phase difference disappears to the next time when the phase difference is detected based on the phase difference signal, and the elapsed time. An oscillation circuit characterized in that the predetermined time is set based on 請求項1に記載の発振回路において、前記発振回路は、高精度で動作させる場合は前記所定の時間を短く設定し、低精度で動作させる場合は前記所定の時間を長く設定することを特徴とする発振回路。   2. The oscillation circuit according to claim 1, wherein the oscillation circuit sets the predetermined time short when operating with high accuracy, and sets the predetermined time long when operating with low accuracy. Oscillator circuit to perform. 請求項1から4のいずれか一項に記載の発振回路を備えたことを特徴とする電子機器。   An electronic apparatus comprising the oscillation circuit according to claim 1. 基準となる周波数の基準信号を出力する周波数確度が高い高精度発振器と、
出力信号の周波数を制御電圧で制御する電圧制御発振器と、
前記基準信号の位相と前記出力信号の位相との位相差を検出し位相差信号を出力する位相比較部と、
前記位相差信号に基づき前記制御電圧を生成する制御電圧生成部と、
を含む発振回路の制御方法であって、
前記位相差信号に基づき前記位相差が無くなった時点から所定の時間が経過するまでの期間は前記位相比較部への電源の接続を接続状態にし、前記期間以外は前記位相比較部への電源の接続を非接続状態にするスイッチ工程を含む、
ことを特徴とする発振回路の制御方法。
A high-precision oscillator with high frequency accuracy that outputs a reference signal of a reference frequency,
A voltage controlled oscillator that controls the frequency of the output signal with a control voltage; and
A phase comparator that detects a phase difference between the phase of the reference signal and the phase of the output signal and outputs a phase difference signal;
A control voltage generator for generating the control voltage based on the phase difference signal;
An oscillation circuit control method including:
Based on the phase difference signal, the power supply to the phase comparison unit is in a connected state during a period from when the phase difference disappears until a predetermined time elapses. Including a switch step of bringing the connection into a disconnected state,
And a method for controlling the oscillation circuit.
JP2008133948A 2008-05-22 2008-05-22 Oscillation circuit, electronic device provided with oscillation circuit and control method of oscillation circuit Withdrawn JP2009284196A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016225779A (en) * 2015-05-29 2016-12-28 セイコーエプソン株式会社 Reference signal generating device, electronic equipment, mobile body, data communication device, and digital terrestrial communication network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016225779A (en) * 2015-05-29 2016-12-28 セイコーエプソン株式会社 Reference signal generating device, electronic equipment, mobile body, data communication device, and digital terrestrial communication network

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