JP2004179719A - Phase locked loop apparatus and phase locked loop method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL apparatus for maintaining a phase lock state so as to prevent an output frequency from being fluctuated even when a reference signal for phase comparison is momentarily interrupted. <P>SOLUTION: The PLL apparatus for controlling a control object signal is provided with: a reference signal input section 13 for receiving the reference signal 6, allowing a delay circuit 7 to generate a delayed reference signal 12 resulting from delaying the reference signal 6 by a prescribed time, and allowing an OR circuit 8 to generate an OR between the reference signal 6 and the delayed reference signal 12 as an adjusted reference signal 14; a phase comparator 1 for comparing the adjusted reference signal 14 with the control object signal to detect a phase difference between them; a charge pump 2 for receiving the phase difference and supplying a current to a loop filter 3 according to the received phase difference; the loop filter 3 for storing the supplied current and converting the stored current into a voltage; a VCO 4 for generating a signal with a frequency based on the voltage; and a frequency divider 5 for receiving the signal generated by the VCO 4 and frequency-dividing the signal to be supplied to the phase comparator 1 as the control object signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a phase locked loop device (phase locked loop) and a method in a wireless communication device.
[0002]
[Prior art]
FIG. 6 is a diagram showing a conventional circuit configuration. In the figure, 1 is a phase comparator for performing a phase comparison, and 2 is controlled by a phase difference signal whose phase is compared by the phase comparator 1. The charge pump 3 is a loop filter that accumulates the current from the charge pump 2 and converts it into a voltage. 4 is a VCO (Voltage Controlled Oscillator) that generates the frequency of an output signal in accordance with the voltage of the loop filter. A divider 6 for dividing the signal from the VCO 4 is a reference signal for performing a phase comparison.
[0003]
Next, the operation will be described.
The reference signal 6 for phase comparison and the comparison signal from the frequency divider 5 are input to the phase comparator 1, and the phases are compared by the phase comparator 1. The phase comparator 1 detects a phase difference, controls the charge pump 3 based on the phase difference signal, and generates a sink / source current as a charge pump output. The sink / source current from the charge pump 3 is supplied to the loop filter 4 and converted into a control voltage of the VCO 5. The oscillation frequency of the VCO 5 is controlled by the control voltage from the loop filter 4, and finally, the phase comparator 1 performs closed loop control so that the phase difference becomes zero, and obtains a signal of a desired constant frequency. Can be.
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 06-061850 [Patent Document 2]
JP 2001-274682 A
[Problems to be solved by the invention]
In the conventional PLL circuit, when the reference signal is interrupted, phase comparison cannot be performed. That is, the phase difference signal advances and the phase difference increases, and the frequency of the output signal from the VCO 5 fluctuates to a lower frequency according to the time constant of the PLL circuit. In a wireless communication, in particular, a PLL circuit for determining a radio frequency of a mobile communication device has a small time constant of the PLL in order to shorten a channel switching time, and a change in the radio frequency due to the interruption of the reference signal is large. The reference signal for the phase comparison is supplied by a reference signal oscillator unit in the device, and the reference signal oscillator unit has a redundant configuration, so that even if one reference signal oscillator unit fails, the operation of the device is maintained. It is configured to be able to continue without stopping (provided with a plurality of reference signal oscillator units). However, there is a problem in that a momentary interruption occurs when the reference signal oscillator unit is switched to the other when the reference signal oscillator unit fails, thereby causing a change in radio frequency.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to obtain a PLL device and a PLL method in which a frequency (in particular, a radio frequency) does not fluctuate due to a momentary interruption of a reference signal.
[0007]
[Means for Solving the Problems]
A phase-locked loop device (PLL device) according to the present invention is a PLL device that controls a control target signal.
A reference signal input unit that receives a reference signal, generates a delay reference signal obtained by delaying the reference signal by a predetermined time, and generates a logical sum of the reference signal and the delay reference signal as an adjustment reference signal;
A phase comparison unit that receives the adjustment reference signal and the control target signal generated by the reference signal input unit, compares the adjustment reference signal with the control target signal, and detects a phase difference,
A charge pump that inputs the phase difference detected by the phase comparison unit and supplies electricity according to the input phase difference,
A loop filter that accumulates electricity supplied from the charge pump and converts the accumulated electricity into a voltage;
A voltage-controlled oscillator that receives the voltage converted by the loop filter and generates a signal having a frequency based on the input voltage;
A frequency divider for inputting a signal generated by the voltage controlled oscillator and dividing the input signal as the control target signal to the phase comparator.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
In FIG. 1, reference numeral 1 denotes a phase comparator for performing a phase comparison, 2 denotes a charge pump controlled by a phase difference signal compared in phase by the phase comparator 1, and 3 denotes a current from the charge pump 2. A loop filter that accumulates (electricity) and converts it into a voltage, 4 is a VCO (Voltage Controlled Oscillator) that generates the frequency of an output signal according to the voltage of the loop filter, and 5 is a signal that separates the signal from the VCO 4 A frequency divider that circulates, 6 is a reference signal (reference frequency) for performing a phase comparison, 7 is a delay circuit for delaying the reference signal 6, and 8 is a delay reference signal 12 output from the delay circuit 7 and a reference. An OR circuit that outputs an OR with the signal 6.
[0009]
Next, the operation will be described.
The reference signal 6 for the phase comparison is supplied to the OR circuit 8 without passing through the delay circuit 7 for delaying the time when the phase comparison signal is momentarily interrupted and the delay circuit 7. The delay circuit 7 delays a predetermined time (a predetermined clock) and outputs a delayed reference signal 12 having the same phase as that of the reference signal 6. The delay reference signal 12 and the reference signal 6 are input to the OR circuit 8, and an OR signal of these signals is output. When the reference signal 6 is input without an instantaneous interruption, the output signal from the OR circuit 8 becomes the same signal as the reference signal 6, and phase synchronization is performed based on the reference signal 6. On the other hand, when the reference signal 6 is stopped due to an instantaneous interruption, the reference signal 6 supplied to the OR circuit 8 disappears, but the signal delayed by a predetermined time by the delay circuit 7 has the same phase as that of the reference signal 6 originally supplied. To the OR circuit 8. Thus, the output of the OR circuit 8 continues to supply the reference signal 6 for phase comparison to the phase comparator 1 even when the reference signal 6 is momentarily interrupted.
[0010]
FIG. 2 is a diagram showing a relationship among the reference signal 6, the delay reference signal 12, and the adjustment reference signal 14.
The reference signal 6 indicates a case where three clocks are interrupted.
The delay reference signal 12 is a signal output from the delay circuit 7, and FIG. 2 shows a case where the delay circuit 7 outputs a signal obtained by delaying the reference signal 6 by 5 clocks. Accordingly, the delay reference signal 12 output from the delay circuit 7 appears with the instantaneous interruption timing delayed by five clocks.
FIG. 2 shows a case where the predetermined delay time is set to 5 clocks. The delay time is a time (clock) for delaying the reference signal 6 in the delay circuit 7. The delay time is a predetermined time (the number of clocks), and an arbitrary number of clocks can be set.
The adjustment reference signal 14 is a signal output from the OR circuit 8 and input to the phase comparator 1.
[0011]
As shown in FIG. 2, the OR circuit 8 outputs the logical sum of the reference signal 6 and a delayed reference signal 12 obtained by delaying the reference signal 6 by 5 clocks as an adjustment reference signal 14. Therefore, when an instantaneous interruption within the set predetermined time (five clocks in FIG. 2) occurs in the reference signal 6, a change in phase due to the instantaneous interruption can be canceled.
[0012]
As described above, in this embodiment, in the PLL device that controls the control target signal (the signal output from the frequency divider 5 in FIG. 1), the reference signal 6 is input, and the reference signal 6 is supplied for a predetermined time. A reference signal input unit 13 for generating a delayed reference signal 12 and generating a logical sum of the reference signal 6 and the delay reference signal 12 as an adjustment reference signal 14; and an adjustment generated by the reference signal input unit 13. A phase comparison unit (a phase comparator 1 is an example) that receives the reference signal 14 and the control target signal and compares the adjustment reference signal 14 with the control target signal to detect a phase difference; Inputs a detected phase difference, supplies a charge (current) in accordance with the input phase difference, and stores a charge supplied from the charge pump 2 and converts the stored electricity into a voltage. filter And a voltage controlled oscillator (VCO 4 is an example) that receives the voltage converted by the loop filter 3 and generates a signal having a frequency based on the input voltage, and a signal generated by the voltage controlled oscillator. The PLL device including the frequency divider 5 for dividing the input signal as the control target signal to the phase comparison unit has been described.
[0013]
Further, the reference signal input section 13 includes a delay section (a delay circuit 7 is an example) for generating a delay reference signal obtained by delaying the reference signal 6 by a predetermined time, and a delay section generated by the reference signal 6 and the delay section. An example in which a reference signal 12 is input and a logical sum unit (an OR circuit 8 is an example) that outputs a signal of a logical sum of the reference signal 6 and the delay reference signal 12 as the adjustment reference signal 14 will be described. did.
In FIG. 1, each component is shown using a circuit, but the present invention is not limited to this. For example, the delay circuit 7 is an example of a delay unit, and the OR circuit 8 is an example of a logic unit. Therefore, it may be realized by software or the like.
[0014]
As described above, the PLL device according to the present embodiment generates the adjustment reference signal 14 in the reference signal input unit 13 having the delay unit and the logic unit, so that the predetermined time set in the delay unit (in the example of FIG. (Five clocks), it is possible to suppress the fluctuation of the frequency due to the occurrence of the instantaneous interruption. Therefore, even when an instantaneous interruption occurs, the phase synchronization state can be continued.
[0015]
In addition, even while the reference signal is momentarily interrupted, the phase synchronization circuit can maintain the phase synchronization, and can stably maintain the frequency of the output signal.
[0016]
As described above, in the present embodiment, the phase comparator 1 that performs the phase comparison, the VCO 4 that performs the frequency control by the voltage, the charge pump that supplies the current according to the result of the phase comparison, and the current from the charge pump A loop filter (Loop Filter) 3 for accumulating and supplying a control voltage to the VCO, a frequency divider 5 for dividing the output signal of the VCO 4 for phase comparison, a reference signal for phase comparison, and the phase comparator A description has been given of a PLL circuit for a wireless communication device (an example of a PLL device), which is provided with a delay circuit 7 for delaying a reference signal in one reference signal input unit 13.
[0017]
Embodiment 2 FIG.
Although the delay circuit 7 is provided in the first embodiment of the present invention, the phase synchronization detection circuit 9 and the charge pump current limit control circuit 10 are connected to each other when an instantaneous interruption for the delay time of the delay circuit 7 or longer occurs. By providing such a structure, it is possible to reduce the occurrence of loss of phase synchronization and frequency shift. FIG. 3 shows the configuration.
[0018]
Next, the operation will be described.
From the phase difference generated by the phase comparison in the phase comparator 1, the phase synchronization state is detected by the phase synchronization detection circuit 9. In response to the phase synchronization state signal output from the phase synchronization detection circuit 9, the charge pump current limit control circuit 10 controls the sink / source current of the charge pump 2 to decrease in the phase synchronization state, and the non-phase synchronization state. In, the sink / source current of the charge pump 2 is controlled to be maximum. As a result, even if the reference signal is cut off in the phase-locked state, the sink / source current of the charge pump 2 is limited to a minimum, so that the current supplied to the loop filter 3 is minimized, and the voltage for controlling the VCO 4 is reduced. The change is minimized, and the fluctuation of the output frequency is reduced.
[0019]
FIG. 4 is a diagram showing a relationship among the reference signal 6, the delay reference signal 12, and the adjustment reference signal 14. Except for the number of clocks at which an instantaneous interruption has occurred, description of the same parts as in FIG. 2 will be omitted.
The reference signal 6 indicates a case in which 9 clocks are interrupted. This point is different from the example of FIG.
FIG. 4 also shows a case where the delay time is set to 5 clocks.
In FIG. 4, the number of clocks of 9 clocks in which the instantaneous interruption has occurred and continued exceeds the number of clocks of the delay time of 5 clocks. Therefore, as shown in FIG. 4, the adjustment reference signal 14 is in a state where the input signal is disconnected (disconnected state).
[0020]
In a state where the input signal is turned off, the phase synchronization detecting circuit 9 detects that the input signal is out of phase, and the charge pump current limit control circuit 10 sets the sink / source current of the charge pump 2 to the maximum. Will be controlled so that By maximizing the sink / source current, the variation in output frequency is reduced.
[0021]
As described above, in this embodiment, in addition to the configuration of the first embodiment, the PLL device receives the phase difference compared by the phase comparator 1, detects the synchronization state based on the phase difference, and A phase synchronization detection unit (an example of a phase synchronization detection circuit 9) that outputs a phase synchronization state signal indicating whether the state is a state or not, and the phase synchronization state signal input from the phase synchronization detection unit, It has been described that a charge pump control unit (the charge pump current limit control circuit 10 is an example) that controls supply of electricity (current) supplied by the charge pump 2 based on a signal is provided. In addition, although the two additional configurations described above are described using circuits in FIG. 3, they are not limited thereto, and may be realized by software or the like.
[0022]
By adding the above configuration, even when the state where the reference signal is interrupted (cut off) exceeds a predetermined delay time, it is possible to reduce the fluctuation of the frequency.
Further, during the phase synchronization, the sink / source current of the charge pump 2 is reduced, so that an instantaneous interruption exceeding the phase synchronization holding time (predetermined delay time) by the delay unit (delay circuit 2) occurs. Can minimize the loss of phase synchronization.
[0023]
As described above, in this embodiment, in addition to the first embodiment, the phase synchronization detection circuit 9 and the charge control for controlling the supply current of the charge pump in the phase synchronization state in accordance with the signal from the phase synchronization detection circuit 9 are performed. The PLL circuit for a wireless communication device having the pump current limit control circuit 10 has been described.
[0024]
Embodiment 3 FIG.
In the second embodiment of the present invention, the charge pump current limiting control circuit 10 for controlling the sink / source current of the charge pump 2 is provided. The same object can be achieved by providing a phase difference limiting circuit 11 that limits the phase difference signal from a phase difference of 0 to a maximum phase difference in a stepwise manner. FIG. 5 shows the configuration.
[0025]
Next, the operation will be described.
Based on the phase synchronization state signal detected by the phase synchronization detection circuit 9, in the phase difference limiting circuit 11, even if the phase difference signal from the phase comparator 1 changes from a state without a phase difference to a maximum phase difference, By controlling the phase difference to be changed stepwise without maximizing the phase difference, the output current of the charge pump is controlled, the current supplied to the loop filter 3 is minimized, and the change in the voltage controlling the VCO 4 is minimized. And the fluctuation of the output frequency is reduced.
[0026]
Also in this embodiment, as shown in FIG. 4, when the duration of the instantaneous interruption exceeds a predetermined delay time, the fluctuation of the frequency can be reduced.
In the PLL circuit according to this embodiment, when the adjustment reference signal 14 is disconnected as shown in FIG. 4, the phase difference limiting circuit 11 controls the phase difference so as to change the phase difference stepwise.
[0027]
FIG. 5 shows, as an example, a configuration in which a phase synchronization detecting circuit 9 and a phase difference limiting circuit 11 are added to the configuration of the PLL circuit of the first embodiment. However, a configuration in which the phase difference limiting circuit 11 is added to the PLL circuit shown in FIG. 3 is also possible.
[0028]
As described above, in this embodiment, the phase synchronization detection unit (the phase synchronization detection circuit 9 is an example), the phase difference output from the phase comparator 1, and the phase synchronization state signal output from the phase synchronization detection unit And a phase difference control unit (phase difference limiting circuit) that controls the phase difference to change stepwise based on the phase synchronization state signal, and outputs the controlled phase difference to the charge pump 2. 11 is an example). The phase difference limiting circuit 11 is an example, and is not limited to a circuit.
[0029]
As described above, by changing the phase difference stepwise by the phase difference control unit, the sink / source current of the charge pump 2 can be reduced during the phase synchronization. Thus, when an instantaneous interruption that exceeds the phase synchronization holding time (predetermined delay time) by the delay unit (delay circuit 2) occurs, it is possible to minimize the loss of phase synchronization.
[0030]
As described above, in this embodiment, in addition to the first embodiment, a phase synchronization detecting circuit 9 and a phase difference limiting circuit for controlling the phase difference signal from the phase comparator 1 in accordance with the signal from the phase synchronization detecting circuit 9 The PLL circuit for a wireless communication apparatus, which has 11, and controls the phase difference stepwise in response to a phase synchronization state, that is, a phase difference signal changing from a phase difference 0 to a maximum phase difference, has been described.
[0031]
Embodiment 4 FIG.
The configurations of the PLL circuits (PLL devices) shown in FIGS. 1, 3, and 5 shown in the first to third embodiments are merely examples.
For example, in FIG. 1, the phase difference control unit 15 shows, as an example, a configuration including components of a portion surrounded by a dotted line, a charge pump 2, a loop filter 3, a VCO 4, and a frequency divider 5. However, the phase difference control unit 15 is a specific component as long as it has a function of inputting the phase difference detected by the phase comparison unit (for example, the phase comparator 1) and controlling the phase difference. Is not limited to the example shown in FIG. The same applies to the phase difference control unit 15 in FIGS.
[0032]
In addition, in FIGS. 2 and 4, the reference signal and the like are described using digital signals, but the present invention is not necessarily limited to digital signals. It is also possible to apply to analog signals.
[0033]
Embodiment 5 FIG.
In the above embodiment, the description has been made using the device as the PLL circuit. However, the phase locked loop method using the PLL device is also characterized in that the adjustment reference signal is used. In the phase locked loop method, a reference signal is input, and a logical sum of the input reference signal and a delay reference signal generated based on the reference signal is compared with a control target signal to be controlled as an adjustment reference signal.
[0034]
As a specific example, the phase locked loop method is performed by the following procedure.
(1) A reference signal is input, and a reference signal delayed from the reference signal by a predetermined time is generated (a reference signal generation step).
(2) An OR of the reference signal and the generated delay reference signal is generated as an adjustment reference signal (adjustment reference signal generation step).
(3) A phase difference is detected by comparing the generated adjustment reference signal with the control target signal (phase difference detecting step).
(4) Control so as to suppress the detected phase difference (phase difference control step).
[0035]
【The invention's effect】
According to the present invention, by using the signal of the logical sum of the reference signal and the reference signal obtained by delaying the reference signal by the predetermined time, the phase synchronization state is maintained even when the instantaneous interruption of the reference signal occurs. It becomes possible. Therefore, the frequency of the output signal can be maintained in a stable state. In particular, in a PLL device of a wireless communication device having a small time constant, the influence of an instantaneous interruption can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a PLL circuit for a wireless communication device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a relationship among a reference signal 6, a delay reference signal 12, and an adjustment reference signal 14.
FIG. 3 is a configuration diagram of a PLL circuit for a wireless communication device according to a second embodiment of the present invention.
FIG. 4 is a diagram showing a relationship among a reference signal 6, a delay reference signal 12, and an adjustment reference signal 14.
FIG. 5 is a configuration diagram of a PLL circuit for a wireless communication device according to a third embodiment of the present invention.
FIG. 6 is a configuration diagram of a conventional PLL circuit for a wireless communication device.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 phase comparator, 2 charge pump, 3 loop filter, 4 VCO, 5 divider, 6 reference signal, 7 delay circuit, 8 OR circuit, 9 phase synchronization detection circuit, 10 charge pump current limit control circuit, 11 phase difference Limiting circuit, 12 delay reference signal, 13 reference signal input section, 14 adjustment reference signal, 15 phase difference control section.

Claims (6)

In a phase locked loop device for controlling a control target signal,
A reference signal input unit that receives a reference signal, generates a delay reference signal obtained by delaying the reference signal by a predetermined time, and generates a logical sum of the reference signal and the delay reference signal as an adjustment reference signal;
A phase comparison unit that receives the adjustment reference signal and the control target signal generated by the reference signal input unit, compares the adjustment reference signal with the control target signal, and detects a phase difference,
A charge pump that inputs the phase difference detected by the phase comparison unit and supplies electricity according to the input phase difference,
A loop filter that accumulates electricity supplied from the charge pump and converts the accumulated electricity into a voltage;
A voltage-controlled oscillator that receives the voltage converted by the loop filter and generates a signal having a frequency based on the input voltage;
A frequency divider that receives a signal generated by the voltage-controlled oscillator and divides the input signal as the control target signal to the phase comparator. "PLL") device. The reference signal input section is
A delay unit that generates a delay reference signal obtained by delaying the reference signal by a predetermined time;
An input unit that inputs the reference signal and the delay reference signal generated by the delay unit, and an OR unit that outputs a signal of the OR of the reference signal and the delay reference signal as the adjustment reference signal. The PLL device according to claim 1, wherein The PLL device further includes:
A phase synchronization detection unit that receives the phase difference compared by the phase comparison unit, detects a synchronization state based on the phase difference, and outputs a phase synchronization state signal indicating whether or not the synchronization state is established;
2. A charge pump control unit that receives the phase synchronization state signal from the phase synchronization detection unit and controls supply of electricity supplied by a charge pump based on the phase synchronization state signal. Or the PLL device according to 2. The PLL device further includes:
A phase synchronization detection unit that receives the phase difference compared by the phase comparison unit, detects a synchronization state based on the phase difference, and outputs a phase synchronization state signal indicating whether or not the synchronization state is established;
The phase difference output by the phase comparison unit and the phase synchronization state signal output by the phase synchronization detection unit are input, and the phase difference is controlled to change stepwise based on the phase synchronization state signal. 3. The PLL device according to claim 1, further comprising: a phase difference control unit that outputs a controlled phase difference to the charge pump. In a phase locked loop device (hereinafter, referred to as a “PLL device”) that controls a control target signal,
A reference signal input unit that receives a reference signal, generates a delay reference signal obtained by delaying the reference signal by a predetermined time, and generates a logical sum of the reference signal and the delay reference signal as an adjustment reference signal;
A phase comparison unit that receives the adjustment reference signal and the control target signal, and compares the adjustment reference signal and the control target signal to detect a phase difference;
A phase control unit for receiving the phase difference detected by the phase comparison unit and controlling the phase difference. In a phase locked loop method for controlling a control target signal,
Input the above reference signal,
Generating a delay reference signal obtained by delaying the reference signal for a predetermined time;
The reference signal, the OR of the generated delay reference signal is generated as an adjustment reference signal,
The generated adjustment reference signal is compared with the control target signal to detect a phase difference,
A phase-locked loop method comprising controlling to suppress the detected phase difference.

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