JP3370258B2 - Clock supply device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply device used in a slave synchronization system for communication, and more particularly to a clock supply device for performing frequency monitoring and control for improving clock quality of a communication network. It is a thing.

In a current communication system that multiplexes and demultiplexes in order to efficiently transmit a digitized signal, the operation of each node and each device in the network is taken into consideration in consideration of the load on the device, the economical efficiency, and the like. The clocks must match. This method is called network synchronization. In Japan, the "dependent synchronization method" is used as a means to achieve network synchronization. This is a method in which each node in the network has a hierarchical relationship, and the lower node extracts the clock from the synchronization signal received from the upper node and generates the clock of its own node from this. By this method, all the devices in the node are synchronized with the clock generated by the standard clock generator installed in the node located at the top of the network.

Details of the slave synchronization scheme are shown in FIGS. 1a and 1b. FIG. 1a represents an image of clock distribution between nodes. In FIG. 1a, 11 is a standard clock generator, 12 is a clock supply device, 13 is a master node, 14 is a sub-master node, 15 is a sub-master node, 16 is a slave node, and a solid arrow is an N-system clock path and transmission by it. The flow of signals to be performed, and the dotted line arrow is the flow of signals to be transmitted by the E system clock path.

In the clock network of the subordinate synchronization system, the respective nodes are associated with each other in the vertical direction, the highest node thereof is called a master node, its lower nodes are called sub-master nodes, and the lower nodes are called slave nodes. There are two standard clock generators 11, one is installed in the master node 13, and all signals of the clock network are synchronized with this standard clock generator 11. Another standard clock generator
11 is installed in the secondary master node 14 and the master node 13
It is used when an abnormality occurs in the standard clock generator 11 installed in. Therefore, in a normal state, the sub master node 14 receives a clock from the master node 13 and actually functions as a sub master node.

The standard clock generated by the standard clock generator 11 installed in the master node 13 is supplied to the clock supply device 12 in the master node 13. The clock supply device 12 reproduces a clock synchronized with the standard clock from the standard clock generator 11 and distributes it to the synchronizing device (transmission device, exchange, etc.) in the node (see FIG. 1b). Each synchronization device in the node transmits a signal synchronized with the clock received from the clock supply device 12 to another node. The nodes below the sub-master node extract the clock from the transmission path from the upper node and reproduce the clock of the own node. The principle is shown in FIG. 1b.

FIG. 1b shows one of the slave nodes 16.
From the signal received from the upper node 15 through the transmission line 17,
The transmission device 18 extracts the timing signal and sends it to the clock supply device 12. The clock supply device 12 reproduces the clock synchronized with this timing signal and distributes it to the synchronization devices (transmission device 18, exchange 19, etc.) in the node. Each synchronization device in the node transmits a signal synchronized with the clock received from the clock supply device 12 to another node.

A transmission path from an upper node from which a node below the sub master node extracts a timing signal is called a clock path. In Japan, in order to ensure high reliability, the clock path is usually provided with two systems, a working N system and a standby E system. This redundant configuration will be described in detail below.

FIG. 2 shows details of the conventional clock supply device 12. Reference numeral 21 is a clock receiving circuit, 22 is a clock selection switching circuit, 23 is a network synchronous oscillator, 24 is a frequency conversion circuit, and 25 is a clock distribution circuit. N is an N system input signal and a signal synchronized with the signal, and E is an E system input signal and a signal synchronized with the signal. The clock supply device of FIG. 2 employs a redundant configuration including N system and E system.

In the redundant configuration of the clock supply device, this N
There is a 0/1 redundant configuration in addition to the / E redundant configuration. The comparison is as follows. -N / E redundant configuration: When operating normally, N system (active) operates and N
Switch to the E system (spare) when the system is abnormal. When the N system returns to normal, it switches back to the N system. 0/1 redundant configuration: It is assumed that there are two equivalent circuits, 0 and 1, to which a subsequent circuit is connected. If an abnormality occurs in the circuit 0 while the circuit in the subsequent stage receives the timing signal from the circuit 0, the information is transmitted to the circuit in the subsequent stage, and based on this, the circuit in the subsequent stage switches the input from the circuit 0 to the circuit 1. After that, even if the circuit 0 is restored, the input of the subsequent circuit is not switched.

In the clock supply device 12 of FIG. 2, the clock receiving circuit 21 has an N / E redundant configuration, and has a 0/1 redundant configuration in the subsequent stage. Clock receiver circuit
21 receives the timing signal extracted from the clock path, converts it to an 8K TTL signal, and sends it to the clock selection switching circuit 22. The clock receiving circuit 21 issues an alarm when it detects an input disconnection or an output disconnection. The clock selection switching circuit 22 which receives the inputs from the clock receiving circuits 21 of both the N system and the E system selects the input according to the alarm occurrence status in the clock receiving circuit 21. When no alarm is generated in both systems, the input from the N system clock receiving circuit 21 is selected and transmitted to the network synchronous oscillator 23. When an alarm is generated in the N-system clock receiving circuit 21, the input from the E-system clock receiving circuit 21 is selected and transmitted to the network synchronous oscillator 23. After the alarm is recovered, the clock selection switching circuit 22 makes an input by pressing a switchback button (not shown) on the clock supply device 12 or by the clock supply device 12 receiving a switchback request signal transmitted from the outside. Switch back from E system to N system. The clock selection switching circuit 22 has a 0/1 redundancy configuration, and when the output disconnection of the clock selection switching circuit 22 is detected, the frequency conversion circuit 24 in the subsequent stage switches the input.

The network synchronous oscillator 23 is a clock selection switching circuit.
A clock is generated based on the signal from 22 and transmitted to the frequency conversion circuits 24 of both systems. The network synchronous oscillator 23 has a 0/1 redundant configuration and issues an alarm in the following situations.・ When the phase comparison result is abnormal (when the result that the network synchronous oscillator 23 cannot follow) is detected ・ When the control data is abnormal (when the result that the network synchronous oscillator 23 cannot follow is detected) When the CPU and the memory in the network synchronization oscillator 23 are abnormal (when the result that the network synchronization oscillator 23 cannot follow) is detected, when the output interruption of the network synchronization oscillator 23 is detected.

The frequency conversion circuit 24, which has received the inputs from both the 0-system and 1-system network-synchronized oscillators 23, selects either one in accordance with the alarm generation status in the clock selection switching circuit 22 and the network-synchronized oscillator 23. , The selected signal is converted into a target frequency and transmitted to the clock distribution circuits 25 of both systems. The switching operation in the frequency conversion circuit 24 in this case is shown in FIG. In the figure, a circle indicates a normal case, and a cross indicates a failure case, and the selection up to that point is switched based on the occurrence of the failure. Frequency conversion circuit 24
Has a 0/1 redundant configuration and issues an alarm when the frequency conversion circuit 24 detects an output interruption. Frequency conversion circuit for both systems
The clock distribution circuit 25 receiving the input from 24 selects either one in accordance with the alarm generation status of the frequency conversion circuit 24, branches the signal, and distributes the clock to the in-node devices.

FIG. 4 shows details of the network synchronous oscillator 23 shown in FIG. 31 is a phase comparison unit, 32 is an analog / digital converter (A / D converter), 33 is a central processing unit (CPU), 34
Is a digitally controlled oscillator unit, and 35 is a frequency divider. The phase comparison unit 31 compares the phase of the signal from the clock selection switching circuit 22 of FIG. 2 with the output signal of the frequency divider 35. The result of this comparison (analog value) is converted into phase data (digital value) by the A / D converter 32. CPU33 is A / D converter 32
The phase data from is processed and processed, and transmitted as control data to the digitally controlled oscillator unit 34. The digitally controlled oscillator unit 34 controls and outputs the frequency according to the control data from the CPU 33.

The output of the digital control oscillator unit 34 is branched into the following three. A signal that is frequency-divided by the frequency divider 35 and transmitted to the frequency conversion circuit 24; a signal that is transmitted to the A / D converter 32 as a counting clock used for A / D conversion; A signal that is converted to the same frequency as the signal from the clock selection switching circuit 22 in and is compared in phase with the signal from the clock selection switching circuit 22 in the phase comparison unit 31.

The clock supply device 12 issues an alarm in the following cases.・ When the clock is disconnected. This clock interruption is detected by the clock receiving circuit 21, the clock selection switching circuit 22, the network synchronous oscillator 23, the frequency conversion circuit 24, and the clock distribution circuit 25.・ When the network synchronous oscillator becomes unable to follow. This is detected by the network synchronization oscillator 23. When the clock supply device 12 detects an abnormality, it determines that the respective parts of the corresponding device are out of order. Therefore, there are the following two problems when the device is normal.

The first problem is that the frequency accuracy is deteriorated, but when a clock that can be followed by the network synchronous oscillator 23 is input, the clock supply device 12 does not notice the frequency deterioration,
That is, the clock that follows the input is distributed to the lower node as it is. This will be described in detail with reference to FIG. FIG. 5 is a diagram showing the same clock supply device 12 as in FIG. The dotted arrow in the figure represents a signal in which the frequency accuracy of the clock has deteriorated to such an extent that it affects communication but is synchronized with it, although it is within the range in which the network synchronous oscillator 23 can follow,
Hereinafter referred to as signal K. A solid arrow represents a signal with normal frequency accuracy and a signal synchronized with it, which will be hereinafter referred to as a signal L.

As shown in the figure, the signal K is input to the N system and E
A case where the signal L is input to the system will be described. In this case, since no signal disconnection is observed in the clock receiving circuit 21, an alarm indicating abnormality is not issued and the received signal is transmitted to the clock selection switching circuit 22. Since no signal interruption is observed even in the clock selection switching circuit 22, an alarm indicating an abnormality is not issued,
The signal K from the N-system clock receiving circuit 21 is selected and transmitted to the network synchronous oscillator 23. The network synchronous oscillator 23 transmits the signal K to the frequency conversion circuit 24 without generating an alarm indicating an abnormality because no signal disconnection is observed and the signal K can be followed. Since no signal disconnection is observed in the frequency conversion circuit 24, no alarm indicating an abnormality is generated, and since the signal K is input from the network synchronous oscillators 23 of both systems to the frequency conversion circuit 24, the frequency conversion circuit 24 will eventually Even if the input of is selected, the signal K is transmitted to the clock distribution circuit 25. Since no signal interruption is observed in the clock distribution circuit 25 as well, an alarm indicating an abnormality is not generated, and since the signal K is similarly input from both systems, the signal K is transmitted to the in-node device and the lower node.

In such a case, an abnormality occurs in communication between the device in the node synchronized with the signal K and the device of another node synchronized with the signal L. In this case, the conventional clock supply device
In the case of 12, the alarm indicating the abnormality is not generated at all even though the signal K is input. Therefore, it is difficult to find that the cause of the communication abnormality is due to the signal K, and the clock supply device 12 continues to transmit the signal K for a long time, which adversely affects the communication for a long time and a wide range. Will be given.

The second problem is that, when a clock that the network-synchronous oscillator 23 cannot follow is input, the clock supply device 12 judges that the network-synchronous oscillator 23 of both systems has a failure, and the frequency conversion circuit 24 in the subsequent stage It means that the degraded clock is distributed to the lower nodes to fix the input. This will be described in detail with reference to FIG. FIG. 6 is a diagram showing the same clock supply device 12 as in FIG. The dotted arrow in the figure indicates the network synchronous oscillator 23.
Represents a signal in which the frequency accuracy of the clock is deteriorated to the extent that cannot be followed and a signal in synchronization with the signal, and is hereinafter referred to as signal S. The dotted arrow represents the output signal when the network-synchronous oscillator 23 strays with respect to the signal S and the signal synchronized therewith, and is hereinafter referred to as the signal P. A solid arrow represents a signal with normal frequency accuracy and a signal synchronized therewith, and is a signal L.

As shown in the figure, the signal S is input to the N system and E
A case where the signal L is input to the system will be described. In this case, since no signal disconnection is observed in the clock receiving circuit 21, an alarm indicating abnormality is not issued and the received signal is transmitted to the clock selection switching circuit 22. Since no signal interruption is observed even in the clock selection switching circuit 22, an alarm indicating an abnormality is not issued,
The signal S from the N-system clock receiving circuit 21 is selected and transmitted to the network synchronous oscillator 23. At this time, since the network synchronous oscillator 23 cannot follow the signal S, an alarm indicating an abnormality is generated, and the signal P is transmitted from the network synchronous oscillator 23 of both systems to the frequency conversion circuit 24 of both systems. At this time, the frequency conversion circuit 24 fixes the input according to the information that the alarm has been generated by the network synchronous oscillator 23.
Therefore, the frequency conversion circuit 24 is a clock distribution circuit 25 for both systems.
To the signal P. In the clock distribution circuit 25, since the signal P is input from both systems, the signal P is transmitted to the in-node device and the lower node regardless of which signal is selected.

In such a case, an abnormality occurs in communication between the device in the node synchronized with the signal P and the device of another node synchronized with the signal L. In this case, the conventional clock supply device
In the case of 12, an alarm indicating an abnormality is generated in the network synchronous oscillator 23, and even if the frequency conversion circuit 24 in the subsequent stage has a function of switching the input, the output of the clock supply device 12 is not improved and the signal P remains output. is there. Further, the abnormality in the network synchronization oscillator 23 is judged to be the failure of the network synchronization oscillator 23, and the discovery that the cause of the communication abnormality is due to the signal S and the signal P is delayed, which adversely affects the communication over a long period and a wide range. Will be given.

[0022]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to promptly find a clock which is deteriorated from a set clock quality without changing the circuit design of each part of the existing apparatus and to always provide a stable clock. An object of the present invention is to provide a clock supply device capable of supplying a lower node.

[0023]

In order to achieve the above object, a clock supply device of the present invention has a clock receiving circuit for receiving a plurality of clock signals, and a clock selection for selecting a clock to be followed among the received clocks. Switching circuit,
A network synchronous oscillator that digitally generates a clock that is synchronized with a selected clock, a frequency conversion circuit that converts the generated clock to a target frequency, a clock distribution circuit that distributes the converted clock in a desired number, and preset Equipped with an anomaly detection circuit that detects anomalies related to the specified items, and a circuit that makes the network-synchronous oscillator self-run when the clock signal is not received, and the frequency accuracy of the clock is lower than the preset value. When the clock is received, the clock receiver is changed, and when it is judged that the quality of all the receivers is abnormal, the input is cut off and the network-synchronized oscillator is self-running.

In the present invention as described above, the frequency control data of the network synchronous oscillator is periodically collected as data,
It is desirable that the average value of the collected data is calculated, the average value is compared with the individual collected data, and the comparison result is integrated over time. Furthermore, set a threshold for judging the normality and abnormality of the comparison result of individual collected data and average value, if the comparison result is above the threshold value, alarm is issued, and further, individual collected data and average value Set the threshold for judging the normality and abnormality of the time integrated value of the comparison result with
If the time integration value of the comparison result is equal to or greater than the threshold value, it is desirable to issue an alarm and change the clock to be followed. Furthermore, for all received clocks, if the time integration value of the comparison result of the collected data and the average value exceeds the threshold value, the input to the clock supply device is shut off and the reference value before shutting off (average of the collected data It is desirable that the value) be used as control data for the network synchronous oscillator and the network synchronous oscillator be self-propelled.

According to the clock supply device of the present invention as described above, two kinds of thresholds are set and the fluctuation of the control data of the network synchronous oscillator is monitored to detect an abnormality which cannot be found by the conventional device. be able to. When the variation of control data exceeds the threshold 1, an alarm is issued.
It can be found that a signal of abnormal quality may be input to the clock supply device for each control data collection cycle. Therefore, it is possible to detect the danger before the clock supply device actually follows the abnormal input. By detecting an alarm when the time integrated value of the amount of change in control data exceeds a threshold value 2, it is possible to detect a deterioration in clock quality without determining an instantaneous change in control data due to noise etc. as abnormal. You can

When an abnormal quality signal is input to the N-system clock receiving circuit, the input is switched to the E-system clock receiving circuit by the clock selection switching circuit, but the abnormal quality signal is input to both system clock receiving circuits. Then, the clock supply device stops following these abnormal inputs, and the clock supply device can run by itself. When the input is cut off and the clock supply device is self-propelled, the clock supply device can output with the same accuracy as in the case of following the normal input.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a clock supply device of the present invention will be described in detail with reference to the drawings. FIG. 7 is a block diagram of the clock supply device of the present invention. In the figure, 61 is a clock receiving circuit, 62 is a clock selection switching circuit, 63 is a network synchronous oscillator, 64 is a frequency conversion circuit, 65 is a clock distribution circuit,
66 is a controller, 67 is control data, 68 is a control signal, 69
Is an alarm. Here, the clock receiving circuit 61 has an N / E redundant configuration, and the subsequent stage has a 0/1 redundant configuration. FIG. 8 is a diagram showing the details of the configuration of the network synchronous oscillator 63. In the figure, 70 is an input from the clock selection switching circuit 62, 71 is a phase comparison unit, 72 is an A / D conversion unit, and 73 is C.
PU, 74 is a D / A converter, 75 is a digitally controlled oscillator,
76 and 77 are frequency dividers, and 78 is an output to the frequency conversion circuit 64.

The controller 66 is provided with an abnormality detection circuit for detecting an abnormality relating to a preset item, and a circuit for causing the network synchronous oscillator to self-run when the clock signal is not received.

The abnormality detection circuit of the controller 66 includes means for setting a period for collecting data, means for collecting data, means for setting the number of samples for calculating an average value of the collected data, and means for averaging the collected data. , Means for comparing average value with individual collected data, means for setting integration interval for time integration of comparison result, means for time integration of comparison result, normal comparison result of individual collection data and average value For setting thresholds for determining the abnormalities and abnormalities, means for issuing an alarm if the comparison result is greater than or equal to the threshold, normality and abnormality of the time integrated value of the comparison result of individual collected data and the average value. Means for setting a threshold value for determining whether the time integration value of the comparison result is greater than or equal to the threshold value, and an alarm is issued if the time integration value of the comparison result is greater than or equal to the threshold value. Comprising means for changing the to clock.

The circuit for free-running the network-synchronized oscillator of the controller 66 inputs to the clock supply device when the time integrated value of the comparison result of the collected data and the average value exceeds the threshold value for all the reception clocks. With means to shut off
When the input of the receiving circuit is cut off, the reference value (the average value of the collected data) before the cutoff is used as the control data of the network synchronous oscillator, and the network synchronous oscillator is made to run by itself.

Since the threshold 1 and the threshold 2 can be arbitrarily set, the international recommendation "ITU-T" is used here.
Set various parameters as follows so as to satisfy "G828, G824".・ Control data collection cycle: 100 seconds ・ Number of samples for calculating the average value of control data: 100 ・ Integration interval for calculating the time-integral value of the variation of control data: 5 × 10 ⁶ seconds ( 50,000 samples), Threshold 1: Graph 2 in FIGS. 9, 11, 13, and 15 Threshold 2: Graph 5 in FIGS. 10 and 14 and Graph 7 in FIGS.

[Embodiment 1] In the first embodiment, the N-system clock receiving circuit 61 has a frequency deviation Δf (Δf / Δf / Δf / Δf / Δf / Δf / Δf / Δf / Δf / Δf / Δf) with respect to the frequency f ₀ of the input clock (hereinafter referred to as the signal A) in a normal state.
This is a case where an abnormal clock (hereinafter referred to as signal B) with f ₀ = 5 × 10 ⁻⁹ ) is input, and the operation principle in that case will be described. Since the frequency deviation of Δf / f ₀ = 5 × 10 ^-9 is within the range in which the clock supply device can follow, the conventional clock supply device does not give an alarm to the signal B. Time t =
When the signal B is input to 0 to the N-system clock receiving circuit 61,
The control data (value converted into frequency deviation) changes with time as shown in graph 1 of FIG. 9, and the time integration value of the variation amount of the control data (difference from the average value of the control data) is plotted with time. It changes like the graph 4 of 10. The control data exceeds the threshold 1 (graph 2 in FIG. 9) at time t =
Although it is 53 seconds, since the control data collection period is 100 seconds, at time t = 100 seconds, the means for issuing an alarm of the controller 66 detects that the variation amount of the control data exceeds the threshold value 1, The alarm "CAUTION" is generated. When the threshold value 1 is exceeded, the input of the clock supply device is not switched.
This is because the control value may temporarily change due to the influence of noise or the like.

Therefore, the controller 66 continues to generate "CAUTION" until the time t = 2300 seconds when the time integral value of the fluctuation amount of the control data exceeds the threshold value 2 (graph 5 in FIG. 10). By continuously generating “CAUTION”, the maintenance person of the clock supply device can detect that the clock supply device may be input with abnormal quality. At time t = 2300 seconds, if the time integration value of the fluctuation amount of the control data exceeds the threshold value 2, the controller
The means for issuing the alarm of 66 determines that the fluctuation of the control data is not due to the influence of noise or the like but due to the signal B, and issues the alarm "EMERGENCY". At the same time, the means for changing the clock of the controller 66 sends a control signal to the clock selection switching circuit 62 and switches the input to the clock selection switching circuit 62 from the N system clock receiving circuit 61 to the E system clock receiving circuit 61. By this operation, the clock supply device follows the input of the E-system clock receiving circuit 61 which is a normal signal, so that the control data changes as shown in graph 3 of FIG. 9 after t = 2300 seconds, and the fluctuation amount of the control data is changed. The time integration value changes as shown by the graph 6 in FIG. Therefore, by the operation of the controller 66, the output quality of the clock supply device maintains high accuracy in conformity with the international standard, in contrast to the case of the conventional device (graph 1 in FIG. 9, graph 4 in FIG. 10).

Next, the case where the signal B is input to both the N-system and E-system clock receiving circuits 61 will be described. The means for changing the clock of the controller 66 sends a control signal to the clock selection switching circuit 62,
The operation until the input to 62 is switched from the N-system clock receiving circuit 61 to the E-system clock receiving circuit 61 is the same as described above. In this case, since the signal B is also input to the E-system clock receiving circuit 61, the control data collected 100 seconds after the switching continues to exceed the threshold 1, and the time integration value of the variation amount of the control data is Threshold 2 is still exceeded. Therefore, at t = 2300 seconds, the means for issuing the alarm of the controller 66 determines that the signal B is also input to the E-system clock receiving circuit 61, issues the alarm "EMERGENCY", and the means for changing the clock is the clock. A selection switching circuit control signal is transmitted, and control is performed so that the clock selection switching circuit 62 does not select an input from any of the N-system and E-system clock receiving circuits 61.
That is, the clock supply device is controlled so as to run by itself.

At the same time, the means for averaging the collected data of the controller 66 sends the average value of 50,000 control data including the control data collected last to the network synchronous oscillator 63,
The network synchronous oscillator 63 controls to generate a clock based on this value. At this time, the control data is t = 2300 seconds and thereafter.
1 changes as shown by the graph 3, and the time integration value of the variation amount of the control data changes as shown by the graph 6 in FIG. If the clock supply is self-propelled, the output frequency accuracy is 1.
It drifts at 93 × 10 ^-17 and gradually converges to the accuracy of 1 × 10 ^-9 of the network-synchronized oscillator 63 installed. Time t = 5.2 × 10 ⁷
After converging to the accuracy of the network synchronous oscillator 63 per second, the output is maintained at that accuracy. Therefore, the graph 3 of FIG. 11 and the graph 6 of FIG. 12 have different shapes from the graph 3 of FIG. 9 and the graph 6 of FIG. 10, respectively.

In the self-running function of the conventional clock supply device,
When the signal B is input to the clock receiving circuits 61 of both the N system and the E system, the control data is generated based on the signal B. Therefore, when the signal is allowed to run as it is, the clock supply device has the accuracy of the signal B. It will start self-propelled. Therefore, the control data generated based on the signal B is reset, and the network synchronous oscillator 63
It is best to self-propelled with the accuracy of. The time integration value of the variation amount of the control data at this time changes as shown by the graph 5 in FIG. Therefore, by the operation of the controller 66, the output quality of the clock supply device is maintained with higher accuracy than in the case of the conventional device (graph 1 in FIG. 11, graph 4 or 5 in FIG. 12).

[Embodiment 2] In the second embodiment, in the N-system clock receiving circuit 61, the frequency deviation Δf (Δf / f ₀ = 1.1) with respect to the frequency f ₀ of the input clock (signal A) in the normal state.
The case where an abnormal clock (hereinafter referred to as signal C) of × 10 ^-8 ) is input, and the operation principle in that case will be described.
Since the frequency deviation of Δf / f ₀ = 1.1 × 10 ⁻⁸ is in the range in which the clock supply device cannot follow, an alarm is generated in the network synchronous oscillator 63. At time t = 0, the signal C changes to the clock receiving circuit 61.
Control data changes as shown in graph 1 of FIG. The value of the control data exceeds the threshold value 1 at t = 23 seconds, but since the collection period of the controller 66 is 100 seconds, the means for issuing an alarm of the controller 66 at time t = 100 seconds is the variation amount of the control data. Is judged to have exceeded the threshold 1, and an alarm "CAUTION" is issued. At time t = 1200 seconds, the control data exceeds the range in which both the 0-system and 1-system network synchronous oscillators 63 can follow. At this time, the network synchronous oscillator 63 issues an alarm "FAIL" for both system 0 and system 1. Since the alarm is generated in the network-synchronous oscillators 63 of both systems, the frequency conversion circuit 64 in the subsequent stage fixes the input from the network-synchronous oscillator 63 as it is without switching.

At the same time, at time t = 1200 seconds, the time-integrated value of the fluctuation amount of the control data exceeds the threshold value 2. At this time, the means for issuing an alarm of the controller 66 determines that the variation of the control data is due to the signal C, and issues an alarm "EMERGENCY". At the same time, the means for changing the clock of the controller 66 transmits a control signal to the clock selection switching circuit 62 and switches the input to the clock selection switching circuit 62 from the N-system clock receiving circuit 61 to the E-system clock receiving circuit 61. By this operation, the clock supply device follows the input from the E-system clock receiving circuit 61, which is a normal signal, so the control data changes as shown in graph 3 of FIG. 13 after t = 1200 seconds.
The time integral value of the variation amount of the control data changes as shown by the graph 6 in FIG. Therefore, by the operation of the controller 66, the output quality of the clock supply device maintains high accuracy in conformity with the international standard, as opposed to the case of the conventional device (graph 1 in FIG. 13 and graph 4 in FIG. 14).

Next, both N-system and E-system clock receiving circuits
The case where the signal C is input to 61 will be described. The means for changing the clock of the controller 66 sends a control signal to the clock selection switching circuit 62, and the clock selection switching circuit 62
The operation until switching the input to the N-system clock receiving circuit 61 to the E-system clock receiving circuit 61 is the same as described above. In this case, since the signal C is also input to the E-system clock receiving circuit 61, the control data collected 100 seconds after the switching still exceeds the threshold value 1, and the time integration value of the variation amount of the control data is Threshold 2 is still exceeded. Therefore, t
= 1300 seconds, the controller 66 alarm generating means determines that the signal C is also input to the E system clock receiving circuit 61, generates the alarm "EMERGENCY", and the clock changing means is the means for changing the clock. A control signal is transmitted, and control is performed so that the clock selection switching circuit 62 does not select an input from any of the N-type and E-type clock receiving circuits 61. That is, the clock supply device is controlled so as to run by itself.

At the same time, the means for averaging the collected data of the controller 66 sends the average value of 50,000 control data including the control data collected last to the network synchronous oscillator 63,
The network synchronous oscillator 63 controls to generate a clock based on this value. At this time, the control data is after t = 1200 seconds.
5 changes as shown by the graph 3 and the time integration value of the variation amount of the control data changes as shown by the graph 6 in FIG. FIG.
Similarly to the graph 5 in FIG. 12, the graph 5 in FIG. 12 represents a curve in the case of free-running with the accuracy of the network synchronous oscillator 63 of the clock supply device. Therefore, by the operation of the controller 66, the output quality of the clock supply device maintains a higher accuracy than in the case of the conventional device (graph 1 in FIG. 15, graph 4 or 5 in FIG. 16).

[0041]

As described in detail above, according to the clock supply device of the present invention, it is possible to detect an abnormality in the input signal of a level that cannot be detected by the conventional clock supply device, and the input of the standby system is normal. In this case, by switching to this, the output quality of the clock supply device can be maintained with high accuracy, and if there is an abnormality in both the active and standby systems, the input to the clock supply device is cut off and the clock supply with higher accuracy than before. By self-propelling the device, the output quality can be maintained with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a subordinate synchronization method.

FIG. 2 is a block diagram of a conventional clock supply device.

FIG. 3 is a diagram showing a switching operation in a frequency conversion circuit.

FIG. 4 is a block diagram of a network synchronous oscillator.

FIG. 5 is a diagram showing an operation in the case where a clock, which is within a range in which the network-synchronous oscillator can follow, but whose frequency accuracy of the clock has deteriorated to the extent of affecting communication is input to the clock supply device.

FIG. 6 is a diagram showing an operation when a clock that the network synchronous oscillator cannot follow is input to the clock supply device.

FIG. 7 is a block diagram of a clock supply device of the present invention.

FIG. 8 is a block diagram showing a configuration of a network synchronous oscillator of the present invention.

FIG. 9 is a diagram showing a change with time of a control data value when an abnormal signal is input to the N system.

FIG. 10 shows a case where an abnormal signal is input to the N system,
It is a figure which shows the change with time of the time integration value of the fluctuation amount of control data.

FIG. 11 is a diagram showing changes in control data values with time when an abnormal signal is input to the N system and the E system.

FIG. 12 is a diagram showing a change with time of an integrated value of a variation amount of control data when an abnormal signal is input to the N system and the E system.

FIG. 13 is a diagram showing a change with time of a control data value when an altitude abnormality signal is input to the N system.

FIG. 14 is a diagram showing a change with time of a time integral value of a variation amount of control data when an altitude abnormality signal is input to the N system.

FIG. 15 is a diagram showing changes in control data values with time when an abnormal altitude signal is input to the N system and the E system.

FIG. 16 is a diagram showing a change with time of a time integral value of a variation amount of control data when an abnormal altitude signal is input to the N system and the E system.

[Explanation of symbols]

11 Standard clock generator 12 Clock supply device 13 Master node 14 Secondary Masternode 15 Submaster node 16 slave nodes 17 Transmission line 18 Transmission device 19 exchanges 21 Clock receiving circuit 22 Clock selection switching circuit 23 Network synchronous oscillator 24 Frequency conversion circuit 25 clock distribution circuit 61 Clock receiving circuit 62 Clock selection switching circuit 63 Network synchronous oscillator 64 frequency conversion circuit 65 clock distribution circuit 66 controller 67 Control data 68 Control signal 69 alarm 70 Input from the clock selection switching circuit 71 Phase comparator 72 A / D converter 73 CPU 74 D / A converter 75 Digitally controlled oscillator 76, 77 divider 78 Output to frequency conversion circuit

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-9-181757 (JP, A) JP-A-7-336785 (JP, A) JP-A-5-316089 (JP, A) JP-A-60- 59415 (JP, A) JP-A-1-307397 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04Q 11/04 304 H04L 7/00

Claims (5)

(57) [Claims] 1. A clock receiving circuit for receiving a plurality of clock signals, a clock selection switching circuit for selecting a clock to be followed among the received clocks, and a network synchronous oscillator for digitally generating a clock synchronized with the selected clock. , A frequency conversion circuit that converts the generated clock to a target frequency, a clock distribution circuit that distributes the converted clock in a desired number, an abnormality detection circuit that detects an abnormality related to a preset item, and a clock signal is received If a clock with abnormal quality whose clock frequency accuracy is lower than a preset value is received, the clock receiver is changed and all receivers are changed. If it judges that the quality is abnormal, it shuts off the input and configures the network synchronous oscillator to run by itself. A clock supply device characterized by the above. 2. The clock supply device according to claim 1, wherein the abnormality detection circuit sets a period for periodically collecting the frequency control data of the network synchronous oscillator as data, and the frequency control data of the network synchronous oscillator is set. Means to collect as data regularly, Means to set the number of samples for calculating the average value of the collected data, Means to average the collected data, Means to compare the average value with individual collected data, Time to compare results A clock supply device comprising: means for setting an integration interval for integration; and means for time-integrating a comparison result. 3. The clock supply device according to claim 1, wherein the abnormality detection circuit sets a threshold value for determining normality and abnormality of a comparison result of individual collected data and an average value. , A means for issuing an alarm if the comparison result is equal to or more than a threshold value, a means for setting a threshold value for judging the normality and abnormality of the time integrated value of the comparison result of individual collected data and the average value, If the time integration value is greater than or equal to the threshold value, means for issuing an alarm, and if the time integration value of the comparison result is greater than or equal to the threshold value,
A clock supply device comprising means for changing a clock to be followed by a clock selection switching circuit. 4. The clock supply device according to claim 1, 2 or 3, wherein the circuit for free-running the network-synchronous oscillator is the time of the comparison result of the collected data and the average value for all the reception clocks. A clock supply device comprising means for cutting off an input to the clock supply device when the integrated value exceeds a threshold value. 5. The clock supply device according to claim 1, 2, 3 or 4, wherein when the circuit for free-running the network synchronous oscillator cuts off the input of the receiving circuit, the reference value (collected data The clock supply device is characterized in that the network synchronization oscillator is configured to be self-propelled by using the average value) of the network synchronization oscillator as control data.