JP4187480B2 - Clock synchronous switching device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock synchronization switching device, and more particularly to a clock synchronization switching device and system provided at each node of a slave synchronization network that sequentially synchronizes with a clock of a master node.
[0002]
[Prior art]
FIG. 30 is a block diagram of a conventional clock synchronization switching device, showing a clock synchronization switching device provided at each node of a slave synchronization network that sequentially synchronizes with the clock of the master node. In the figure, 31 is a first transmission path clock priority information separating means for separating clock priority information received from the first transmission path, 32 is a first transmission path clock extracting means for extracting a clock from the first transmission path, 33 Is a second transmission path clock priority information separating means for separating clock priority information received from the second transmission path, 34 is a second transmission path clock extracting means for extracting a clock from the second transmission path, and 35 is an external clock input The external clock input monitoring means 36 for monitoring the clock, the clock priority setting means 36 for presetting the priority for the self node to become the master node as the clock priority, and the clock generating means 38 for generating the clock within the self node. .
[0003]
Further, reference numeral 37 denotes a clock priority setting value of the clock priority setting means 36, an external clock input monitoring signal from the external clock input monitoring means 35, and first and second transmission line clock priority information separating means 31, 32. The first and second received clock priority information are compared with each other to adjust the clock selection, 39 is the first and second transmission line clock extracting means 32 and 34 respectively extracted by the first and second transmission path clock extracting means 32 and 34. A clock switching unit 40 for selecting any one of the second transmission line clock, the external clock input, and the clock in the own node generated by the clock generation unit 38 based on the arbitration result of the arbitration unit 37; In-device clock generation means for generating an in-device clock from the clock selected by the clock switching means 39.
[0004]
Arbitration means 37 performs arbitration as follows. That is, if “clock priority setting value”> “first and second reception clock priorities”, the local node clock (or external clock if there is an external clock input), and “clock priority setting value” "<" First reception clock priority ">" second reception clock priority ", the first transmission path clock, and" clock priority setting value "<" first reception clock priority " <In the case of “second reception clock priority”, the second transmission path clock, and “clock priority setting value” <“first reception clock priority” = “second reception clock priority” In this case, selective arbitration is performed so that the first or second transmission path clock is used as the in-device clock source.
[0005]
Further, 41 is a clock priority information relay means, and the priority information relayed by the own node includes the clock priority setting value set by the clock priority setting means 36 and the first and second transmission path clock priorities. It is updated to the highest priority value of the first and second reception clock priority information separated by the information separation means 31 and 33, and the sequence number indicating the validity of the clock priority information (of the own node) Only when the clock priority setting value is the highest, the value is rewritten to that value, and when it is low, the clock priority information selected for reception / arbitration is relayed as it is for each system).
[0006]
Further, the clock priority relay means 41 is connected to the first and second transmission line clock priority information multiplexing means 42 and 43, and the first transmission line clock priority information multiplexing means 42 is connected to the first transmission line output. The clock priority information is multiplexed, and the second transmission path clock priority information multiplexing means 43 multiplexes the clock priority information on the second transmission path output. This multiplexing operation is performed based on the in-device clock from the in-device clock generation means 40.
[0007]
Conventionally, a plurality of communication nodes having such a clock synchronous switching device are connected in a linear or ring shape, and the node having the highest priority according to the clock priority assigned to each communication node is a master node, and the other nodes are slave nodes. And the master node sends a clock signal supplied from its own node or an external clock source (network synchronization device) to the transmission line, and each slave node is slave-synchronized with the clock extracted from the transmission line. Alternatively, clock synchronization with an external network is established, and then normal data transmission / reception is enabled at each communication node. In addition, network synchronization is always established by performing automatic switching of the master node and automatic switching of the subordinate system at the slave node even in the event of various failures such as external clock supply interruption, master node disconnection or transmission path interruption. ing.
[0008]
[Problems to be solved by the invention]
Conventionally, however, the external clock input is treated as the highest priority in all cases, and the priority order among a plurality of external inputs is also fixed in advance. It has not been possible to flexibly cope with the case where it is desired to increase the priority of the extracted clocks or to determine the priority among a plurality of external input clocks as desired.
[0009]
Also, since the hardware configuration of the external clock input / output unit is fixed, it can be flexibly applied to nodes that do not require external clock input / output and nodes that require more than the fixed number of routes. Could not respond.
[0010]
In addition, since switching control is conventionally performed using only clock priority information, for example, when transmission paths having the same clock priority information and different dependent stage number information are input, the number of dependent stages is large (deteriorated). ) There was an inconvenience that the clock path might be selected.
[0011]
Conventionally, a path with high clock priority information is preferentially selected, so when a failure / restoration of a transmission path occurs, switching / switching back of the clock path occurs and the network is often disturbed. Was the cause.
[0012]
In addition, when a transmission path failure is recovered, there are cases where it is desired to always select the optimum clock path even if disturbance due to switching back occurs, and there are cases where the number of disturbance occurrences is desired to be reduced as much as possible even though the clock path is not optimal. However, the conventional method cannot meet the latter requirement.
[0013]
Further, conventional clock dependent synchronization methods include a method using an external network synchronization device (DCS) having a highly accurate dependent oscillator and a method using a dependent oscillator (PLO) in its own node. By using a high-accuracy network synchronization device, it becomes possible to perform dependent synchronization beyond the limit of the number of dependent stages when using a dependent oscillator in its own node. However, since the conventional handling of the number of dependent stages is handled as the number of dependent stages uniformly without distinguishing these, effective (strict) management of the clock quality cannot be performed.
[0014]
In general, in the synchronous synchronization method of a linear clock path using a network synchronizer, even if the master node (upper clock path) is abnormal, disturbance occurs in the clock switching control after the next network synchronizer. It is desirable not to. However, in the past, all nodes other than the master node uniformly referenced and relayed the clock priority information of the master node, so when the master node transitioned, the clock path was selected at the node after the next network synchronization device Disturbance (switching / switching back) occurred. Hereinafter, it demonstrates concretely according to a figure.
[0015]
FIGS. 31 and 32 are diagrams (1) and (2) for explaining the clock switching operation of the linear type clock path using the conventional clock synchronous switching device, and FIG. 31 shows a normal state. The master node 1 is slave-synchronized with an external clock input with priority = 1 and outputs information with clock priority = 1 downstream and upstream. The next internal slave node 2 is slave-synchronized with the clock input of priority = 1 and relays information of priority = 1 downstream and upstream. Thereafter, proceeding in the same manner, the next-stage external subordinate node 10 using the external network synchronization device outputs a clock input (path sine wave) of priority = 1 to the external network synchronization device (DCS), In addition, subordinate synchronization is performed with the external clock input with priority = 2 generated by the network synchronizer, and the information with input priority = 1 is relayed to the downstream and upstream sides as it is. The internal slave node 11 at the next stage is slave-synchronized with the clock input with priority = 1 and relays information with priority = 1 downstream and upstream. Thereafter, the process proceeds in the same manner, and the external subordinate node 20 outputs the clock input (path sine wave) with the priority = 1 to the external network synchronization device, and the priority = 3 generated by the network synchronization device. While subordinately synchronizing with the external clock input, the information of the input priority = 1 is relayed downstream and upstream as it is.
[0016]
FIG. 32 shows a state at the time of abnormality in which the network synchronization device of the master node 1 has failed. In this example, the node 1 continues to become a master node depending on the built-in oscillator (PLO) due to the priority = 4 of the clock switching unit, and also outputs information on the clock priority = 4 to the downstream and upstream sides. In this case as well, since the node 1 is still the master node, each node is subordinately synchronized with the clock having the priority = 4 and the nodes having the priority = 4 after a sufficient time has passed. Information is relayed downstream and upstream. That is, the clock path selection route in each of the nodes 2, 10, 11, and 20 should remain facing the route (upstream) of the master node 1.
[0017]
However, since the linear clock path network has a physical spread, the network side still has the original information before the new priority = 4 information, which replaces the priority = 1 information, is propagated downstream. A phenomenon occurs in which information with a priority of 1 remains (propagated). For this reason, for example, when the internal subordinate node 11 temporarily picks up the information of the remaining priority = 1 from the downstream, switches the clock selection route to the downstream side, and then switches back to the upstream of the priority = 4. The so-called fluttering phenomenon occurs. The same applies to the other nodes 2, 10, and 20. Thus, conventionally, there has been a disadvantage that clock path selection disturbance occurs on the network side when the master node is switched.
[0018]
Further, in the external subordinate node 10 that uses an external network synchronization device, for example, after arbitrating the extraction clock from the transmission channel, the transmission channel extraction clock with a high priority is sent to the network synchronization device, and the network synchronization device The internal clock of the node 10 is generated from the clock that is synchronized and recovered in the previous step. However, since the selective arbitration of the internal clock has been a fixed selection of the external clock input in the past, the input from multiple network synchronous devices is selected and arbitrated. There was no degree of freedom when it came to doing.
[0019]
In addition, transmission / reception of priority information in the synchronous transmission using the conventional STM method can be performed at a constant cycle by using the overhead area of the transmission data. On the other hand, in the asynchronous transmission using the ATM method, priority transmission is possible. Since the frequency information is transmitted / received by the cell, it is impossible to transmit / receive the priority information at a constant cycle due to the influence of cell fluctuation or the like. For this reason, it is desired that proper clock path switching control can be performed even if there is fluctuation in transmission / reception of priority information.
[0020]
Further, in an asynchronous network such as ATM, if information related to clock switching control is transmitted at the same interval as that of a synchronous network such as STM, the bandwidth of the main signal data will be compressed, so improvement is desired.
[0021]
The present invention has been made in view of the above-described problems of the prior art. The object of the present invention is to provide a clock synchronization switching device capable of stably and reliably performing clock network synchronization control of various network configurations with a simple configuration and arbitration control, and To provide a system.
[0022]
[Means for Solving the Problems]
  According to the first aspect of the inventionThe clock synchronization switching device is a clock synchronization switching device provided in each node of the slave synchronization network that sequentially synchronizes with the clock of the master node, and the clock switching extracted by the interface unit that terminates each signal connection with the transmission line. Predetermined information related to controlAnd predetermined information related to clock switching control generated by an interface unit that terminates each signal connection with an external network synchronization deviceA clock switching control unit that performs clock path arbitration control based oneachThe type of informationWithout distinguishing between transmission path extraction clock and network synchronizer output clockBy unifying them, there is one that manages these mediations uniformly.
[0023]
  The present inventionTherefore, the clock switching control unit sets the type (content) of the predetermined information to be arbitrated to the same type such as “clock priority information”, “clock dependent stage number information”, “transmission path abnormality information”, etc. Regardless of the type of arbitration route, whether it is a transmission path extraction clock or a network synchronizer output clock, with a unified arbitration configuration, these are uniformly implemented by a simple, uniform arbitration logic. Mediation is possible. Therefore, various network configurations such as raising the priority of the transmission path extraction clock over the network synchronizer output clock, or receiving the input clocks from a plurality of network synchronizers and determining the priority among them as desired The clock path can be selected with a high degree of freedom.
[0024]
  In the second aspect of the present invention,The predetermined information includes clock priority information and clock dependent stage number information, and the clock switching control unit includes a first operation mode in which arbitration control is performed based only on the clock priority information, clock priority information, and clock dependent stage number information. And a second operation mode for performing arbitration control based on the above, and each operation mode can be switched manually or automatically.
[0025]
  The present inventionAccording to the above, even when a plurality of transmission lines having the same clock priority information and different clock dependent stage number information are input, an optimum clock path with a small number of clock dependent stages is selected by selecting the second operation mode. Can be selected.
  In the third aspect of the present invention, the clock switching control unit performs the second operation when clock priority information higher than the currently selected priority is input during switching control in the first operation mode. The mode is automatically switched to the mode, and after the new clock path is arbitrated in the second operation mode, the mode is automatically switched back to the first operation mode.
  In the fourth aspect of the present invention, the clock dependent stage number information includes network synchronization apparatus dependent stage number information indicating the number of stages dependent on an external network synchronization apparatus, and the clock switching control unit is configured to perform the same when the clock priority information is the same. Arbitration is selected preferentially with the smaller number of network synchronization device dependent stages.
  In the fifth aspect of the present invention, the clock dependent stage number information includes in-device dependent stage number information indicating the number of stages dependent on the clock source in the apparatus, and the clock switching control unit is The arbitration selection is preferentially performed for the one having less in-device dependent stage number information.
[0026]
  In the sixth aspect of the present invention,The clock switching control unit includes a network synchronization device output clock arbitration unit that performs arbitration selection of a clock source to be output to the network synchronization device based on each predetermined information related to the clock switching control extracted or generated by each interface unit. In-device clock arbitration means for selecting arbitration of the in-device clock source based on the predetermined information.
[0027]
  The present inventionTherefore, the arbitration of the clock source to be output to the network synchronization device and the arbitration of the clock source in the device are controlled separately, so that predetermined information (clock priority information, etc.) to be arbitrated is unified. However, flexible arbitration control of the clock path is possible. For example, after arbitration of the transmission path extraction clock by the network synchronizer output clock arbitration means (however, the input of the network synchronizer output clock is masked at this time), the highest priority transmission path extraction clock is set to one or more external It is possible to easily select one or more network synchronizer output clocks sent to the network synchronizer and synchronized and reproduced by the network synchronizer by the in-device clock arbitrating means. In addition, in the event of a failure in the selected transmission line extraction clock, the output of the network synchronizer output clock arbitration means is stopped, and the high-accuracy network synchronizer output clock that continues to run by itself is selected by the internal clock arbitration means. Is possible.
[0028]
  In the seventh aspect of the present invention,The clock switching control unit provides the first clock signal selected by the network synchronization device output clock arbitration means to the external network synchronization device, and the second clock signal synchronously reproduced by the network synchronization device. The arbitration selection is performed by the in-device clock arbitration means, and the clock priority information relayed and output by the own station is used as the clock priority information set in advance for the second clock signal.
[0029]
  The present inventionAccording to the above, each external subordinate node updates the clock priority information relayed and output by the own station in advance, and outputs it, for example, in the subordinate synchronization of the linear clock path using the network synchronization device. When an upper clock path is abnormal, it is possible to prevent disturbance from the network synchronization device next to the node where the abnormality has occurred.
  In the eighth aspect of the present invention, the clock accuracy information is associated with each clock source existing in the network, and the clock source selected by the network synchronizer output clock arbitration means belongs to the low accuracy class, so that the output of the clock is output. Means for preventing this are provided.
[0030]
  In the ninth aspect of the present invention,The input or output transmission path interface unit includes a predetermined information setting unit for clock switching control, and the setting is replaced with the predetermined information extracted from the input transmission path or the predetermined information mounted on the output transmission path. The setting information of the means can be inserted.
[0031]
  The present inventionAccording to the above, by inserting arbitrary setting information (clock priority information) of the setting means in place of predetermined information (for example, clock priority information) extracted from the input transmission path, from the upstream (higher network etc.) The provided clock priority information can be changed as desired, and therefore, the clock connection with the upstream (higher network etc.) and its priority management can be performed as desired on the downstream side. Alternatively, by providing arbitrary setting information (clock priority information) of the setting means in place of predetermined information (for example, clock priority information) mounted on the output transmission path, it is provided downstream (such as a lower network). The clock priority information can be changed as desired. Therefore, on the upstream side, the clock connection with the downstream (lower network etc.) and the priority information management can be performed as desired.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 is a block diagram of a clock synchronous switching device according to an embodiment. The device is connected to a plurality of input / output transmission lines and a plurality of interface (IF) units for terminating external clock input / output, The clock switching unit 28 that performs the arbitration switching control is provided.
[0033]
Paying attention to the input path of each IF section, 1 is a first transmission path clock priority information separating means for separating priority information from the first transmission path input, and 2 is for separating the dependent stage number information from the first transmission path input. First transmission line clock dependent stage number information separating means, 3 is a first transmission line abnormality detecting means for detecting an abnormal transmission line state from the first transmission line input, and 4 is a first extracting clock from the first transmission line input. Transmission path clock extracting means, which is not shown in the figure, is followed by an IF section that terminates the second and third transmission paths in the same manner, and 5 is an nth transmission that separates priority information from the nth transmission path input. Path clock priority information separating means, 6 is an nth transmission line clock dependent stage number information separating means for separating the dependent stage number information from the nth transmission line input, and 7 is an nth detecting line abnormality state from the nth transmission line input. Transmission line transmission line abnormality detection means, 8 is the first A first n line clock means for extracting a clock from the transmission line input. Further, 9 is an external clock input clock priority information setting means for setting external clock input priority information, 10 is an external clock input clock dependent stage number information setting means for setting external clock input dependent stage number information, and 11 is an external clock. External clock input abnormality detecting means 12 for detecting an input transmission line abnormal state, and 12 is an external clock input clock extracting means for extracting a clock from the external clock input.
[0034]
In this way, the signals extracted from each input IF unit are unified into clock priority information, clock dependent stage number information, transmission path abnormality information, and extracted clocks in all directions. It does not identify what kind of IF unit the input is from. In addition, it is possible to set the priority information and dependent stage number information of the external clock input, so that the priority of the transmission line input can be made higher than that of the external clock input, and a clock adapted to various network forms. The path can be constructed flexibly.
[0035]
In the clock switching unit 28, reference numeral 13 denotes clock priority information setting means for presetting the priority for the own node to become the master node as a clock priority, and reference numeral 14 denotes the dependent stage number information when the own node becomes the master node. Clock dependent stage number information setting means 15 for setting, clock generation means 15 for generating a clock within the own node.
[0036]
Further, reference numeral 16 denotes an in-device clock arbitration means for performing selective arbitration of the in-device clock. Each of the first to nth transmission lines and external clock input priority information, relay stage number information, transmission line abnormal state, and self The node priority information setting value and the relay stage number information setting value are compared to select and arbitrate the clock in the apparatus.
[0037]
FIG. 3 shows the arbitration logic of the internal clock. Note that the symbols “high”, “medium”, and “low” representing the priorities in the figure indicate that the clock priorities are relatively high, medium, and low, respectively. On the other hand, with regard to the relay stage number information, there are a method of incrementing by 1 (+1) every time a clock is relayed and a method of decrementing by (−1). In the former case, the smaller the relay stage number information, the higher the priority. In the latter case, the higher the relay stage number information, the higher the priority. For example, when paying attention to the row of item 5, when the clock priorities are equal, the first transmission path clock having a higher priority of the relay stage number information is selected, and when paying attention to the row of term 6, priority of the relay stage number information is selected. The nth transmission line clock having a high degree is selected.
[0038]
Returning to FIG. 2, reference numeral 17 denotes a network synchronizer output clock arbitration means for arbitrating an output clock to an external network synchronizer. Selection of the network synchronizer output clock is made based on the same input as that of the internal clock arbitration means 16. Mediate.
[0039]
FIG. 4 shows the arbitration logic of the network synchronizer output clock. For example, paying attention to each row of the term 4 / term 8, if the clock priority of the own node is high, or if the clock priority of each node is equal and the priority of the relay stage number information of the own node is high, The clock in the own node is output to the network synchronization device. However, in this case, the clock accuracy is deteriorated, so that the output clock to the network synchronization device is stopped.
[0040]
Returning to FIG. 2, reference numeral 19 denotes an apparatus for selecting any one of the first to nth transmission path clocks, the external clock input, and the own node clock based on the arbitration output of the apparatus clock arbitration means 16. An internal clock switching means, 21 is an internal clock generation means for generating an internal clock from the selected clock as a source, and 20 is a first to nth based on the arbitration output of the network synchronization apparatus output clock arbitration means 17. A network synchronizer output clock switching means for selecting one of the transmission path clock and the external clock input, and 22 is a network synchronizer output clock for generating a network synchronizer output clock from the selected clock as a source. It is a generation means. The network synchronization device output clock switching means 20 causes the clock accuracy to deteriorate by outputting the clock in the own node to the network synchronization device, so that the clock in the own node is not included in the options. Yes.
[0041]
Further, 18 is a clock information relay means for relaying the clock priority information and the clock relay stage number information. The clock priority information includes the clock priority setting value and the first to nth clock priority information. The clock relay stage number information is updated to the highest value, and when the clock priority setting value of the own node is the highest, the value becomes the master node, and when it is lower, the received clock relay stage number information is incremented by 1 (or Update to the decremented value and relay.
[0042]
The clock information relay means 18 is connected to first to n-th transmission line clock priority information multiplexing means 23 to 24 that multiplex priority information and relay stage number information to the first to n-th transmission line outputs, respectively. Each of the multiplexing units 23 to 24 performs the multiplexing operation based on the in-device clock, but receives the same clock priority information and clock relay stage number information separately from the clock information relay unit 18.
[0043]
As described above, the output of the clock switching unit 28 is unified to the relayed priority information and dependent stage number information in all the routes, but the use / unuse is determined according to the type of the external interface to be connected. That is, for example, when the external clock input / output interface is used, since the relayed priority information and relay stage number information are not used, no transfer is performed.
[0044]
Thus, according to the present embodiment, each IF unit with the above-mentioned interface can be expanded to physical restrictions such as the board size, and any connection form such as a transmission path extraction clock and an external clock input can be used. Mediation management can be performed uniformly. Furthermore, by setting the priority order as desired, it is possible to perform 0/1 type switching control and working / standby type switching control, and it is possible to construct clock paths according to various network configurations. .
[0045]
FIG. 5 is a state transition diagram of the arbitration operation according to the embodiment. “Dependent stage number information valid mode” in which arbitration is performed using the clock priority information and the dependent stage number information, and “Dependency” in which arbitration is performed only with the clock priority information. "Stage number information invalid mode" is provided, and by switching these manually / automatically, it is possible to select an optimal clock path according to the network configuration.
[0046]
In the figure, for example, the “dependent stage number information valid mode” is entered by resetting the apparatus or performing an operation (manual / remote operation) for setting dependent stage number information valid. In this mode, arbitration is performed between the priority information and the dependent stage number information, so that an optimal quality clock path is always selected. For example, when the priority information is the same and the dependent stage number information is different, the clock path is switched when an abnormality occurs in the selected route, but when the abnormality occurrence route is recovered, Since switching is performed in consideration of the stage number information, so-called active / spare type switching is performed.
[0047]
On the other hand, the operation of setting the dependent stage number information invalid setting causes the “dependent stage number information invalid mode”. In this mode, arbitration is basically performed without considering the number of dependent stages. However, when clock priority information (CPID) higher than the priority information currently selected is received, the number of dependent stages is automatically set. Transition to the “information valid mode” and perform arbitration including the dependent stage number information. Therefore, when switching occurs, an optimal clock path with a small number of dependent stages is selected from the same priority information. After the route is determined, the mode automatically returns to the “dependent stage number information invalid mode”. In this operation mode, when the priority information is the same and the dependent stage number information is different, switching occurs when an abnormality occurs in the selected route, but priority is given when the abnormality occurrence route is restored. Since the degree information is the same, the dependent stage number information is not taken into account (that is, the transition to the “dependent stage number information invalid mode” is not performed), so that a so-called 0/1 type switching without switching back occurs. In any of the above cases, when the dependent stage number information exceeds the specified value, the information from the route is treated as invalid information.
[0048]
Therefore, it is possible to flexibly cope with various switching modes required by the network configuration without changing hardware. Even in switching control using only priority information, when switching occurs, arbitration including the dependent stage number information is performed so that the optimum clock path at that time can be selected. Even when a failure occurs, the disturbance due to the dependent clock switching can be reduced.
[0049]
FIG. 6 is a diagram showing the format of the priority information and the dependent stage number information. In this embodiment, the dependent stage number information is considered in the clock switching control, and the dependent stage number information is converted into the network synchronization apparatus dependent stage number information and the device internal information. It is divided into two fields of dependent stage number information. Basically, the one with the smaller number of dependent stages of the network synchronization device is selected, and if the number of dependent stages of the network synchronous device is equal, the one with the smaller number of dependent stages in the device is preferentially selected. It is possible.
[0050]
In the operation for the dependent stage number information, the network synchronization apparatus connection node increments the network synchronization apparatus dependent stage number by 1 (or decrements) and resets (initializes) the in-apparatus dependent stage number for transmission. In addition, the dependent node in the apparatus increments only the number of dependent stages in the apparatus by 1 (or decrements), and relays and transmits the number of dependent stages in the network synchronization apparatus as they are. Hereinafter, it demonstrates concretely according to a figure.
[0051]
7 to 9 are diagrams (1) to (3) for explaining the operation of transmitting the number of dependent stages on the network, and FIG. 7 shows a case where the network is operating normally. In the figure, the nodes 2 to 4 are connected to the master node 1 in a ring shape. In this example, since there is no node dependent on the external clock other than the master node 1, the network synchronization device dependent stage number (RHOP) is constant, but the intra-device dependent stage number (SHOP) is −1 every time the node passes. (Decrement).
[0052]
The master node 1 is slave-synchronized with an external clock input (external CLKIF unit) having a priority (CPST = 1), and sends information of CPST = 1, RHOP = 1, and SHOP = 3 (−1) to each route. To do. Node 2 (same for node 4) is slave-synchronized with the clock of CPST = 1 from the master node 1 (corresponding to the external CLKIF unit), and information of CPST = 1, RHOP = 1, SHOP = 2 (−1) Are sent downstream and upstream. In this case, the clocks to be input to the node 3 are CPST = 1, RHOP = 1, and SHOP = 2 in any route. Basically, the first route is selected, and in the case of the second arrival, the route with the youngest interface is selected. In this example, the clock path from the node 2 is selected.
[0053]
FIG. 8 shows a case where the external clock of the master node 1 is cut off in the state of FIG. 7, and in this case, the node 2 that has set the priority CPST = 2 of the clock (SCK) in its own device is used instead. It is a master node. The master node 2 is slave-synchronized with the built-in OSC of its own node, and sends information of CPST = 2, RHOP = 1, and SHOP = 3 (−1) to each route. Node 3 (same for node 1) is slave-synchronized with the clock of CPST = 2 (corresponding to SCK2) from master node 2, and the information of CPST = 2, RHOP = 1, SHOP = 2 (−1) is downstream and Send upstream. Then, the node 4 in this example is subordinately synchronized with the CPST = 2 clock from the node 3 and sends information of CPST = 2, RHOP = 1, and SHOP = 1 (−1) to the downstream and upstream sides.
[0054]
FIG. 9 shows a case where the transmission path between the master node 1 and the slave node 2 is disconnected in the state of FIG. 7. In this case, the node 1 is still the master node, and the node 2 and the node 3 are subordinate. Route switching occurs. That is, the node 4 is originally subordinately synchronized with the CPST = 1 clock (corresponding to the external CLKIF unit) from the master node 1, and the information of CPST = 1, RHOP = 1, SHOP = 2 (−1) is downstream and upstream. To the side. On the other hand, the node 3 is synchronized (switched) in synchronization with the clock of CPST = 1 from the node 4 and sends information of CPST = 1, RHOP = 1, SHOP = 1 (−1) to the downstream and upstream sides. Then, the node 2 is synchronized (switched) in synchronization with the CPST = 1 clock from the node 3 and sends information of CPST = 1, RHOP = 1, and SHOP = 0 (−1) to the downstream and upstream sides.
[0055]
Therefore, the maximum number of dependent stages of the network synchronization device and the maximum number of dependent synchronization steps of the in-device dependent nodes can be respectively defined and monitored (managed) individually. This also eliminates the possibility of selecting an abnormal clock path that causes the clock path to become a loop when there is no master node, and avoids such a situation by monitoring such a path and switching the selection state. Is possible.
[0056]
FIGS. 10 and 11 are diagrams (1) and (2) for explaining the clock switching operation of the linear type clock path using the clock synchronous switching device according to the embodiment. (Stage number information) is always the priority information (and dependent stage number information) set in the external clock input / output unit that interfaces with the network synchronization device. This shows a case where no disturbance of clock switching is applied after the network synchronization device (external subordinate node). This will be specifically described below.
[0057]
FIG. 10 shows a normal state, and its basic operation may be the same as that described in FIG. 31, but in this embodiment, the clock priority information (and the external subordinate nodes 10 and 20) The method of relaying (dependent stage number information) is different. That is, the master node 1 in this example is subordinately synchronized with the external clock input with priority = 1 and outputs information with priority = 1 downstream and upstream. The subsequent internal subordinate node 2 is subordinately synchronized with the clock input of priority = 1 and relays information of priority = 1 downstream and upstream. In the same manner, the next external subordinate node 10 extracts the clock input (path sine wave) of priority = 1 and outputs it to the external network synchronization device (DCS), which is generated by the network synchronization device. The subordinate synchronization with the external clock input with priority = 2 is performed, and information with priority = 2 is newly output to the downstream and upstream sides. Such an operation can be realized by setting priority information (and dependent stage number information) transmitted by the clock information relay means 18. Further, the subsequent internal subordinate node 11 is subordinately synchronized with the clock input of priority = 2 and relays information of priority = 2 downstream and upstream. Thereafter, the process proceeds in the same manner, and the next external subordinate node 20 extracts the clock input (path sine wave) of priority = 2 and outputs it to the external network synchronization device, and the network synchronization device is generated. In addition to subordinate synchronization with the external clock input with priority = 3, here, information with priority = 3 is newly output downstream and upstream.
[0058]
FIG. 11 shows a state at the time when the network synchronization device of the master node 1 has failed. When the master node fails, information with priority = 1 from the higher-order clock path (and dependent stage number information) stops. In this example, the external subordinate node 10 becomes the master node instead, and the master node 10 subordinately synchronizes with the external clock input with the priority = 2 and continuously outputs the information with the priority = 2 downstream and upstream. To do. At this time, the master node 10 stops outputting the route sine wave with the priority = 1, which has been output to the network synchronization device so far, because the own node becomes the master. Further, the downstream internal subordinate node 11 originally subordinately synchronizes with the clock input of priority = 2, and relays information of priority = 2 to the downstream and upstream sides, so that arbitration switching of the clock path occurs. Absent. Thereafter, the process proceeds in the same manner, and the next external subordinate node 20 extracts the clock input (path sine wave) of the priority = 2 and outputs it to the external network synchronization device, and the network synchronization device is generated. The subordinate synchronization is performed with the external clock input with priority = 3, and the information with priority = 3 is output to the downstream and upstream sides. Therefore, arbitration switching of the clock path does not occur. Therefore, according to the present embodiment, the priority information (and the dependent stage number information) does not change downstream of the new master node 10, and thus the clock path switching disturbance that has occurred conventionally may occur. Absent.
[0059]
Note that in the node (not shown) adjacent to the upstream side of the new master node 10, the information of priority = 1 from the upstream disappears and the clock of priority = 4 is temporarily selected. Since the information of priority = 2 from the downstream has the highest priority, the clock path is quickly switched. Hereinafter, similarly, this switching control proceeds upstream, and the clock paths of the nodes 2 and 3 are switched. When the upstream nodes are switched in this way, priority information having a higher priority does not remain, so that there is no disturbance in clock path switching.
[0060]
FIG. 12 is a table showing the transmission modes of the priority information and the dependent stage number information. Each node constituting the network operates as an in-device dependent mode, an external dependent mode, or a master node according to the setting of the operation mode of the local station. In the case of the external subordinate mode, the priority information transmission mode differs depending on whether the clock path is a linear type or not. That is, in the case of the external subordinate node of the linear type clock path, the reception value of the priority information set for the device clock selection route (that is, the network synchronization device) is transmitted.
[0061]
FIG. 13 is a detailed block diagram of the clock switching unit 28 that realizes the operations of FIGS. Here, in the external subordinate node, by masking the priority information and subordinate stage number information from the lower clock path side, the master node priority information and subordinate stage number information remaining on the lower clock path side when the master node fails A configuration is shown in which the clock output to the network synchronizer is prevented from being disturbed in response to. Therefore, in the network configuration of the linear type clock path using the network synchronizer, even if the failure of the upper clock path occurs, the network synchronizer after the next stage does not refer to the priority information and dependent stage number information of the original master node. Does not propagate. Such an operation can be realized by having a mask setting for each route in the network synchronizer output clock arbitration means 17 of FIG.
[0062]
FIG. 14 is a diagram showing a part of a subordinate synchronization network using an external network synchronizer, and ensures the flexibility of clock path construction by individually controlling the output selection control to the network synchronizer and the own node clock generation selection control. The operation | movement at the time of doing is shown typically. When attention is paid to the node on the left side of the figure, arbitration of the network synchronizer output clock in the clock switching unit is performed for all the routes, and usually the clock input from the transmission path IF unit is selected. However, if priority level information and dependent stage number information cannot be received from the transmission path IF unit due to a transmission path abnormality or the like, a route from the external clock input / output IF unit (network synchronization device) is selected. However, in this state, an input from the network synchronizer is output to the network synchronizer, and the network synchronizer operates as a subordinate operation, and the clock path is in an abnormal state. Therefore, by detecting such a state and stopping output to the network synchronization device, control is performed so that a clock path can be established with the free-running clock of the network synchronization device.
[0063]
FIG. 15 is a detailed block diagram of a clock switching unit for realizing the operation of FIG. Separate the arbitration of the internal clock and the arbitration of the output clock to the network synchronizer, and set the transmission path used for the internal clock arbitration and the transmission path used for the network synchronizer output clock arbitration, respectively. A configuration that can be used. Arbitration for the network synchronizer output clock is performed for all routes, but the transmission path used for arbitration of the internal clock is the input clock from the network synchronizer, so the transmission route is external. It becomes the clock input / output IF unit. Therefore, when the network synchronization device is used, a means for masking the priority information and the dependent stage number information other than the external clock input / output IF unit by setting the input unit of the in-device clock arbitration block is provided.
[0064]
It is possible to increase the redundancy by increasing the number of external clock input / output IF units for receiving the clock from the network synchronization device. In this case, by setting the priority information and the dependent stage number information, respectively. , 0/1 type or working / standby type network synchronous clock switching control can be performed. The same applies to the transmission path IF unit, and a free configuration is possible until physical restrictions are imposed.
[0065]
FIG. 16 is a diagram showing a transmission format between the external IF unit and the clock switching unit. Transmission / reception of priority information and dependent stage number information between nodes is not performed at a fixed timing as in the prior art, but within a predetermined time. The case where it can respond to both the transmission system of STM and ATM by performing at arbitrary timing is shown. The external IF unit and the clock switching unit 28 in this embodiment recognize the arrival of the information frame related to the clock switching control from the other party by receiving (detecting) the FTOP signal indicating the start of the information frame related to the clock switching control. .
[0066]
In other words, in the past, for example, the receiving side received and processed the information frame related to the clock switching control transmitted at a period of 125 μS in synchronization with the time, but in the present invention, a specific FTOP signal was received. Thus, since the reception process of the information frame is started, there is no need to perform self-management with any strict cycle on the receiving side, and thus it is freed from time constraints. When this is applied to the STM system, the transmission side periodically transmits information frames, but the reception side only needs to operate by receiving the FTOP signal, and thus is freed from self-management of the period. On the other hand, when this is applied to the ATM system, the fluctuation of the information cell can be flexibly dealt with.
[0067]
FIG. 17 is a block diagram inside the node, schematically showing transmission / reception of information frames and signal processing related to clock switching control. By adopting the FTOP signal, information frames related to clock switching control can be basically exchanged at any timing. Preferably, however, a certain amount of time is determined in advance, and the arbitrary timing within the determined time is determined. It will be done in. In the clock switching unit, it is possible to set the reception period and transmission period of the priority information and the dependent stage number information, and the priority information and the transmission period within a certain period (for example, within about twice the predetermined period) on the information receiving side. An error occurs if the dependent stage number information cannot be received. On the other hand, the information transmission side sends priority information and dependent stage number information in the internal phase of the clock switching unit. In addition, when the external IF unit receives the priority information and the dependent stage number information from the clock switching unit, it quickly sends the priority information and the dependent stage number information to the transmission line.
[0068]
According to this method, it is not necessary to perform phase alignment for information transmission between the in-device frame phase, each internal frame phase, and the transmission path phase. Transmission of priority information and dependent stage number information between the external IF unit and the clock switching unit is performed at the reception transmission path phase and the internal phase of the clock switching unit, regardless of the frame timing specified in the device. Can be reduced. In particular, in the case of ATM transmission, the ratio of the priority information and the dependent stage number information in the main signal data can be freely set, so that the main signal band is not compressed. Also, in STM transmission, priority information and dependent stage number information can be output with the phase received from the transmission path, so that a frame phase change function that has conventionally existed is not necessary.
[0069]
18 to 20 are block diagrams (1) to (3) of the clock synchronous switching device according to the embodiment. The network of the present embodiment is configured by connecting a plurality of communication nodes via transmission lines of 1 to 11 systems regardless of the connection form, and data between communication nodes is an external IF unit in a format shown in FIG. Of these, a total of 32 bits of SOFT (2) to PTY (6) are transmitted to the adjacent nodes via the transmission path. This communication node includes an external IF unit (optical transmission line LIU, terminal LIU, external clock input / output LIU, etc.) in each route, and a configuration related to clock switching control (intra-device clock generation, network synchronization device output clock generation, device Internal clock arbitration, network synchronizer output clock arbitration, intra-device clock distribution, etc.).
[0070]
The external IF unit (corresponding to means 1 to 12 in FIG. 2) connects the transmission path and the communication node, and detects frame synchronization (or reception clock loss detection) and transmission path clock for the received data frame input from the transmission path. In the case of the transmission path IF unit, the priority information and the relay stage number information for the transmission / reception data frame are multiplexed / separated, and in the case of the external clock input / output unit, the set priority information and the relay stage number information Send.
[0071]
The part related to arbitration / selection of the in-device clock (corresponding to means 16 and 19 in FIG. 2) holds priority information for the communication node to become a master node in the register, and also receives priority information in the arbitration unit. Based on the in-node clock priority information that configures the upper value and the dependent stage number information as the lower value, and the priority information from each transmission path, the relay stage number information, and the synchronization detection signal, Run) Arbitration / selection is performed to select any one of the clock, the external clock, and the extracted clock of each transmission path as the in-device clock source. In this case, the arbitration logic conforms to FIG. The switching state transition is the same as in FIG. The relay logic for relaying the priority information and the relay stage number information according to the arbitration result conforms to FIG.
[0072]
The portion related to arbitration / selection of the network synchronizer output clock (corresponding to the means 17 and 20 in FIG. 2) holds priority order information for the communication node to become the master node in the register, and the priority in the arbitration unit Each transmission path is based on the clock priority information in its own node that configures the information as a higher value and the dependent stage number information as a lower value, and the priority information from each transmission path, the relay stage number information, and the synchronization detection signal. Arbitration / selection is performed to select any one of the extracted clocks as a clock source to be output to the network synchronization device. The arbitration logic at that time conforms to FIG. Further, the switching state transition is in accordance with FIG.
[0073]
The part related to the internal clock generation (corresponding to the means 21 in FIG. 2) converts the clock arbitrated and selected by the internal clock arbitration / selection part into the PLO reference frequency, and then generates the internal clock in the PLO. Do. Further, the part related to network synchronizer output clock generation (corresponding to means 22 in FIG. 2) divides the clock arbitrated / selected by the configuration related to network synchronizer output clock arbitration / selection to output the network synchronizer output. Generate a reference clock. Since the network synchronization apparatus has several types of input clock frequencies depending on the model, each corresponding external clock input / output IF unit converts the frequency according to the model.
[0074]
FIG. 21 shows a transmission format between the external IF unit and the clock switching unit of the embodiment. Information related to the clock switching control is composed of six areas (1) to (6), FTOP (1) is a bit indicating the start of a frame, SOFT (2) is a bit for lowering priority information by software control, CPST (3) is a bit indicating priority information, RHOP (4) is a bit indicating the number of dependent stages of the network synchronization device, SHOP (5) is a bit indicating the number of dependent stages in the device, and PTY (6) is a section of SOFT to SHOP. This is the target parity bit. Since FTOP (1) is a signal used only between the external IF unit and the clock switching unit, the information transmitted on the transmission path covers the section from SOFT (2) to PTY (6), and is between nodes. Check parity with.
[0075]
The external IF unit and the clock switching unit recognize the arrival of the frame by detecting the FTOP signal, not the frame phase supplied in the apparatus. Priority information and dependent stage number information are input from each path in separate frame phases, such as the phase received from the transmission path IF section and the phase related to the external clock from the external clock input / output IF section. Is done. For this reason, the propagation delay from the reception of the transmission path to the reception of the clock switching unit can be reduced. The priority information and the dependent stage number information received from each route are compared including the priority information and the dependent stage number information set in the own node, and the route with the highest priority is determined and relayed. .
[0076]
The network synchronization device dependent stage number information is information whose value is incremented (or decremented) every time it passes through the network synchronization device connection node starting from the master node, and an upper limit (or lower limit) is provided for the value. When the synchronization device dependent stage number information exceeds the upper limit (or lower limit), the clock priority information received at the same time is regarded as invalid. On the other hand, in-device dependent stage number information is information in which a value is incremented (or decremented) every time a slave node is relayed starting from a master node, and an upper limit (or lower limit) is provided for the value. When the stage number information exceeds the upper limit (or lower limit), the clock priority information received at the same time is regarded as invalid. In addition, when receiving each information, it considers that it is effective only when a frame synchronizing signal is normal.
[0077]
As described above, in this embodiment, the clock switching unit is provided with the external interface function for 11 routes, so that within this number of routes, a clock having a high degree of freedom can be used regardless of the type of the transmission route or the external clock. Path construction and switching control thereof can be performed.
[0078]
FIG. 22 is a block diagram of a clock synchronization switching apparatus according to the second embodiment, and shows a case where information on clock accuracy is taken into account for clock output control to the network synchronization apparatus. In the figure, 63 is a clock accuracy determination means for determining the clock accuracy for the clock of the arbitration output by the network synchronization apparatus output clock arbitration means 17, and 64 is a network synchronization apparatus output for controlling the clock output to the network synchronization apparatus according to the determination result. Clock control means. Other configurations may be the same as those described in FIG.
[0079]
FIG. 23 shows an example table defining the relationship between the clock priority information and the clock accuracy class. Through the network system, for example, when the clock priority is 1 to 99, it is a high-precision class clock, and when the clock priority is 100 to 199, it is a low-precision class clock. Such a table is provided in the clock accuracy determination means 63 of each node.
[0080]
Returning to FIG. 22, the clock accuracy determination unit 63 refers to the above table for the clock priority information arbitrated and selected by the network synchronizer output clock arbitration unit 17, and determines whether it is a high accuracy clock or a low accuracy clock. Do. The network synchronization device output clock control means 64 causes the network synchronization device to output the clock signal of the network synchronization device output clock generation means 22 in the case of the determination of the high precision clock according to the determination result, and the case of the determination of the low precision clock. Prevents the output of the clock signal.
[0081]
FIGS. 24 and 25 are diagrams (1) and (2) for explaining the operation of the clock synchronization switching device according to the second embodiment. An example of the operation in which clock accuracy information is effectively used on the network is shown. Show. FIG. 24 shows a normal case. In the figure, nodes A to D constitute, for example, a ring network, among which node A is a master node connected to network synchronization apparatus A, and node B is an external subordinate node connected to network synchronization apparatus B. . In the master node A, priority = 1 is set for the external clock from the network synchronization apparatus A, and the clock is identified as a high-precision class clock in each of the nodes A to D. In the external subordinate node B, the priority = 1 (high precision) clock input (route sine wave) is output to the network synchronizer B, and is subordinately synchronized with the external clock input from the network synchronizer B to give priority. Information of degree = 1 (or priority = 2) may be output to the downstream and upstream sides. On the other hand, the clock priority information setting means 13 of each of the nodes A to D sets priority = 100 to 103 for the clock generated by the clock generation means 15 of its own station. Nodes A to D are identified as low-precision class clocks.
[0082]
This network synchronization device B is subordinately synchronized with the route extraction clock with priority = 1, and the output external clock (high accuracy) is not only the node B but also other peers or lower networks (not shown). ). Such an external clock supply method is more general in an actual network configuration.
[0083]
In such a configuration, even when a failure occurs in the external clock from the network synchronization apparatus A, the node B continues to become the master node, so that the high-accuracy external clock from the network synchronization apparatus B is transferred to the node B and other peers or Can be supplied to the lower network. However, if a failure occurs in the supply of the external clock not only in the network synchronization device A but also in the route from the network synchronization device B to the node B, the network synchronization device B cannot be used in the node B. In the network synchronizer output clock arbitration at the node B, a free-run clock (low-precision clock) with a priority = 100 from the node A is selected. The device B is subordinately synchronized with the low-precision clock, and a slip alarm or the like is generated due to a decrease in the accuracy of the reference clock.
[0084]
Therefore, in the network configuration of FIG. 25, at least when the node B has the configuration of the second embodiment (FIG. 22), the clock output to the network synchronization device B is determined to be the low accuracy class. Prevents the output of the reference clock to the network synchronizer B. Accordingly, the network synchronization apparatus B in this case is free-running with its own transmitter, but can continue to provide a high-accuracy clock to other networks by adopting the high-accuracy transmitter.
[0085]
In the second embodiment, each node is provided with a table that defines the relationship between clock priority and clock accuracy. However, the present invention is not limited to this. For example, the clock priority information shown in FIG. 6 may be added to the clock accuracy information so as to be transmitted and processed. This increases transmission information, but there is no need to provide a table for each node. In addition, it is possible to arbitrarily set clock accuracy information for each clock source at each node.
[0086]
FIG. 26 is a block diagram of the clock synchronous switching device according to the third embodiment, showing a case where priority information (and dependent stage number information if necessary) can be arbitrarily set for the separated clock of the input side transmission path IF unit. ing. This switching device is suitable for controlling the clock priority of the lower network side in which the node is included, for example, by adopting it for the node on the lower network side.
[0087]
In the figure, 55 is first transmission path clock priority information setting means for setting clock priority information for the clock extracted from the first transmission path, and 56 is clock priority information separated from the first transmission path and first transmission. First transmission path clock priority information selection means (SEL) for selecting the clock priority information set by the path clock priority information setting means 55, 57 is a setting of clock dependent stage number information for the clock extracted from the first transmission path. The first transmission line clock dependent stage number information setting means 58 for performing the selection, the clock dependent stage number information separated from the first transmission line and the clock dependent stage number information set by the first transmission line clock dependent stage number information setting means 57 are selected. 1 transmission line clock dependent stage number information selection means (SEL), 59 in the same manner, 59 is the nth transmission line clock priority information setting means, 60 is n line clock priority information selection means (SEL), 61 n-th line clock dependent stage information setting unit, 62 is an n-th line clock dependent stage information selection means (SEL). Other configurations may be the same as those described in FIG. However, the clock accuracy determination means 63 and the network synchronization device output clock control means 64 may be omitted.
[0088]
In such a configuration, the selection means 56, 58, etc. are manually operated or controlled by the CPU, so that instead of the clock priority information separated from the input transmission path, arbitrarily set clock priority information (and clock dependency if necessary). (Stage number information) can be targeted for arbitration.
[0089]
FIG. 27 is a diagram for explaining the operation of the clock synchronous switching device according to the third embodiment. Clocks between a plurality of networks (for example, an upper network and a lower network) are set by a simple setting means provided in the input side transmission path IF unit. The case where the connection and its arbitration control can be performed more easily and flexibly is shown. The following description will be made mainly on the processing of the clock priority information, but the case where the clock dependent stage number information is added can be considered similarly.
[0090]
In the figure, nodes P to R constitute a part of an upper network, and nodes A to D constitute a lower network (for example, a ring network). Various other nodes (an internal subordinate node, an external subordinate node, etc.) may exist between the nodes P to R and between the nodes A to C. In this state, the node P is slave-synchronized with a clock source with priority = 100, and is connected to the node A using the clock. The node Q is subordinately synchronized with the clock source having the priority = 102, and is connected to the node B using the clock. The node R is subordinately synchronized with the clock source having the priority = 103, and is connected to the node C using the clock. On the other hand, the settings of the clock priority setting means 13 in the nodes A to D are as follows: node A has priority = 110, node B has priority = 111, node C has priority = 112, and node D has priority = 113. is there. Accordingly, the clock master source of the lower network in this case is greatly restricted by the connection configuration of the upper network.
[0091]
That is, in the illustrated example, the clock master source of the lower network is fixed to the selected clock of the priority = 100 in the node P, and from the standpoint of managing the master clock of the lower network as desired, the flexibility of the clock management Will be significantly lacking. Further, if the master clock source is changed due to the convenience of the upper network, the master clock source of the lower network is also changed accordingly. Therefore, clock management of the lower network becomes extremely complicated and difficult.
[0092]
Therefore, in the third embodiment, for example, the setting value of the first transmission path clock priority information setting unit 55 in the node B is set to priority = 3 equivalent to the external input clock from the network synchronization device, and By selecting the selection means 56 on the first transmission line clock priority information setting means 55 side, any priority information (and the number of dependent stages if necessary) can be used instead of the separation (extraction) information from the input transmission line. Information) can be set. Further, appropriate subordinate synchronization of the lower network with respect to the upper network is formed even with a simple connection only through the transmission path IF unit without using an external network synchronization device.
[0093]
FIG. 28 is a block diagram of the clock synchronous switching device according to the fourth embodiment, showing a case where priority information (and dependent stage number information if necessary) can be arbitrarily set for the output clock of the output side transmission path IF unit. ing. This switching device is suitable for controlling the clock priority on the lower network side connected to the node as desired, for example, by adopting it for the node on the higher network side. In the figure, reference numeral 65 denotes first transmission path clock priority / dependent stage number information setting means for setting clock priority information (and clock dependent stage number information if necessary) for the output clock of the first transmission path, and so on. Step 66 is an n-th transmission line clock priority / dependent stage number information setting means. Although not shown, the setting of these information for the output clock can be activated / deactivated by manual operation or CPU control. Other configurations may be the same as those described in FIG. However, the clock accuracy determination means 63 and the network synchronization device output clock control means 64 may be omitted.
[0094]
According to this configuration, arbitrarily set clock priority information (and clock dependent stage number information if necessary) can be re-assigned to the clock signal of the arbitration output in the node, and therefore the downstream and upstream nodes ( Clock priority information (and clock dependent stage number information if necessary) of other networks can be freely controlled.
[0095]
FIG. 29 is a diagram for explaining the operation of the clock synchronous switching device according to the fourth embodiment. Clocks between a plurality of networks (for example, an upper network and a lower network) are set by simple setting means provided in the output-side transmission path IF unit. The case where the connection and its arbitration control can be performed more easily and flexibly is shown. In the figure, the network configuration may be the same as that described in FIG. However, here, at least the node Q of the upper network is provided with the clock synchronous switching device according to the fourth embodiment (FIG. 28).
[0096]
In the fourth embodiment, the arbitration output information (selection priority) of the in-device clock arbitration means 16 can be set by arbitrarily setting the clock priority information reassigned by the output side transmission path IF unit of the node Q. = 102), for example, it is possible to reset priority = 3 which is equivalent to that of the external input clock. Therefore, the clock dependent synchronization control of the lower network based on the desired node Q is easily realized.
[0097]
In addition, although several embodiment suitable for the said invention was described, it cannot be overemphasized that the structure of each part, control, a process, and these combinations can be variously changed within the range which does not deviate from this invention. .
[0098]
(Additional remark 1) In the clock synchronous switching apparatus provided in each node of the subordinate synchronization system network which synchronizes sequentially with the clock of the master node, a plurality of interface units for terminating each signal connection between the transmission line and the external network synchronous apparatus A clock switching control unit that performs arbitration control of a clock path based on each predetermined information related to clock switching control extracted or generated respectively by unifying the types of the predetermined information to be arbitrated, What is claimed is: 1. A clock synchronization switching device comprising: a device for uniformly managing arbitration regardless of types of a transmission path extraction clock and a network synchronization device output clock.
[0099]
(Supplementary Note 2) The predetermined information includes clock priority information and clock dependent stage number information, and the clock switching control unit includes a first operation mode in which arbitration control is performed based only on the clock priority information, clock priority information, and clock And a second operation mode for performing arbitration control based on the dependent stage number information, and configured to be able to switch each operation mode manually or automatically.
[0100]
(Supplementary Note 3) When switching control is performed in the first operation mode, the clock switching control unit automatically enters the second operation mode when clock priority information higher than the selected priority is input. 3. The clock synchronization switching device according to appendix 2, wherein the clock synchronization switching device automatically switches back to the first operation mode after switching and after arbitrating a new clock path in the second operation mode. Therefore, even when the arbitration is based only on the clock priority information, if clock priority information higher than the selected priority is input, arbitration control based on the clock priority information and the clock dependent stage number information is performed. You can always select the optimal quality clock path.
[0101]
(Supplementary Note 4) The clock dependent stage number information includes network synchronous apparatus dependent stage number information indicating the number of stages dependent on the external network synchronous apparatus, and the clock switching control unit, when the clock priority information is the same, the network synchronous apparatus dependent stage number 3. The clock synchronous switching device according to appendix 2, wherein arbitration is selected preferentially for the one with less. Therefore, even when a plurality of transmission paths having the same clock priority information and different network synchronization device dependent stage number information are input, it is possible to select an optimal clock path with a small number of network synchronization device dependent stages.
[0102]
(Supplementary Note 5) The clock dependent stage number information includes in-device dependent stage number information indicating the number of stages dependent on the clock source in the apparatus, and the clock switching control unit, when the network synchronization apparatus dependent stage number is the same, 6. The clock synchronous switching device according to appendix 4, wherein arbitration is selected with priority on the one with less information. Therefore, even when a plurality of transmission paths having the same network synchronization device dependent stage number information and different in-device dependent stage number information are input, it is possible to select an optimal clock path with a small number of in-device dependent stage numbers.
[0103]
(Supplementary Note 6) The clock switching control unit performs arbitration selection of a clock source to be output to the network synchronization device based on each predetermined information related to the clock switching control extracted or generated by each interface unit. The clock synchronization switching apparatus according to appendix 1, further comprising: arbitration means; and intra-apparatus clock arbitration means that performs arbitration selection of the in-apparatus clock source based on the predetermined information.
[0104]
(Supplementary Note 7) The clock switching control unit provides the first clock signal selected by the network synchronization device output clock arbitration means to the external network synchronization device, and the second synchronized with the second network synchronization device. Appendix 6 characterized in that the clock signal is arbitrated and selected by the in-device clock arbitrating means, and the clock priority information relayed and output by the own station is the clock priority information set in advance in the second clock signal. The clock synchronous switching device as described.
[0105]
(Supplementary Note 8) In a slave synchronization type network system that sequentially synchronizes with the clock of the master node, a specific signal is added and transmitted at a predetermined position of information related to clock switching control exchanged between the nodes. A network system characterized by extracting and processing information related to clock switching control corresponding to reception of the specific signal. Accordingly, it is not necessary to extract and process the information by managing an accurate reception cycle (timing) on the receiving side as in the conventional case, and the circuit configuration and control are simplified. Further, such transmission / reception of the clock path control information can be preferably performed at a free timing within a roughly predetermined time, so that the processing load on the transmission / reception side is greatly increased. Alleviated. In addition, this method can be applied not only to the STM method but also to the ATM method. For example, in cell transmission using the ATM method, even if the cell fluctuates, the control information can be easily extracted and the appropriateness based on the information can be obtained. Clock path switching control.
[0106]
(Supplementary Note 9) Means for associating clock accuracy information with each clock source existing in the network and blocking the clock output when the clock source selected by the network synchronizer output clock arbitration means belongs to the low accuracy class. The clock synchronization switching device according to appendix 6, wherein the clock synchronization switching device is provided. Therefore, it is possible to effectively prevent a situation in which an external network synchronization device operates in synchronization with a low-accuracy clock source.
[0107]
(Supplementary Note 10) The input or output transmission path interface unit is provided with predetermined information setting means for clock switching control, and is replaced with predetermined information extracted from the input transmission path or predetermined information mounted on the output transmission path. The clock synchronous switching device according to appendix 1, wherein the setting information of the setting means can be inserted.
[0108]
【The invention's effect】
As described above, according to the present invention, the clock network synchronization control of various network configurations can be stably and reliably performed with a uniform simple configuration and arbitration control, and the flexibility and reliability of the slave synchronization network are improved. The place that contributes to is extremely large.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block diagram of a clock synchronization switching device according to an embodiment.
FIG. 3 is a diagram illustrating arbitration logic of an in-device clock.
FIG. 4 is a diagram illustrating the arbitration logic of a network synchronizer output clock.
FIG. 5 is a state transition diagram of the arbitration operation according to the embodiment.
FIG. 6 is a diagram illustrating a format of priority information and dependent stage number information.
FIG. 7 is a diagram (1) illustrating an operation for transmitting the number of dependent stages on the network.
FIG. 8 is a diagram (2) illustrating an operation of transmitting the number of dependent stages on the network.
FIG. 9 is a diagram (3) for explaining the operation of transmitting the number of dependent stages on the network.
FIG. 10 is a diagram (1) illustrating a clock switching operation of a linear clock path using the clock synchronization switching device according to the embodiment.
FIG. 11 is a diagram (2) illustrating a clock switching operation of a linear type clock path using the clock synchronous switching device according to the embodiment.
FIG. 12 is a diagram showing a transmission mode of priority information and dependent stage number information.
13 is a block diagram of the clock switching unit 28. FIG.
FIG. 14 is a diagram showing a subordinate synchronization network using a network synchronization device.
15 is a block diagram of the clock switching unit 28. FIG.
FIG. 16 is a diagram illustrating a transmission format between an internal IF unit and a clock switching unit.
FIG. 17 is a block diagram inside a node.
FIG. 18 is a block diagram (1) of the clock synchronous switching device according to the embodiment.
FIG. 19 is a block diagram (2) of the clock synchronous switching device according to the embodiment.
FIG. 20 is a block diagram (3) of the clock synchronous switching device according to the embodiment.
FIG. 21 is a diagram illustrating a transmission format between the external interface unit and the clock switching unit according to the embodiment.
FIG. 22 is a block diagram of a clock synchronization switching device according to a second embodiment.
FIG. 23 is a diagram illustrating a relationship between an example of clock priority information and a clock accuracy class.
FIG. 24 is a diagram (1) for explaining the operation of the clock synchronous switching device according to the second embodiment;
FIG. 25 is a diagram (2) for explaining the operation of the clock synchronous switching device according to the second embodiment;
FIG. 26 is a block diagram of a clock synchronization switching device according to a third embodiment.
FIG. 27 is a diagram for explaining the operation of the clock synchronization switching apparatus according to the third embodiment;
FIG. 28 is a block diagram of a clock synchronization switching device according to a fourth embodiment.
FIG. 29 is a diagram for explaining the operation of the clock synchronous switching device according to the fourth embodiment;
FIG. 30 is a block diagram of a conventional clock synchronization switching device.
FIG. 31 is a diagram (1) for explaining clock switching operation of a conventional linear type clock path;
FIG. 32 is a diagram (2) for explaining the clock switching operation of the conventional linear type clock path;
[Explanation of symbols]
1 First transmission path clock priority information separating means
2 First transmission line clock dependent stage number information separating means
3 First transmission line transmission line abnormality detection means
4 First transmission path clock extraction means
5 n-th transmission line clock priority information separating means
6 nth transmission line clock dependent stage number information separating means
7 nth transmission line abnormality detection means
8 nth transmission path clock extraction means
9 External clock input clock priority information setting means
10 External clock input clock dependent stage number information setting means
11 External clock input error detection means
12 External clock input clock extraction means
13 Clock priority information setting means
14 Clock dependent stage number information setting means
15 Clock generation means
16 In-device clock arbitration means
17 Network synchronization device output clock arbitration means
18 Clock priority information, clock dependent stage number information relay means
19 In-device clock switching means
20 Network synchronization device output clock switching means
21 In-device clock generation means
22 Network synchronization device output clock generation means
23 First transmission path clock priority information multiplexing means
24 nth transmission line clock priority information multiplexing means
28 Clock switching part
55 First transmission path clock priority information setting means
56 First transmission line clock priority information selection means (SEL)
57. First transmission line clock dependent stage number information setting means
58 First transmission line clock dependent stage number information selection means (SEL)
59 n-th transmission line clock priority information setting means
60 nth transmission line clock priority information selection means (SEL)
61 nth transmission line clock dependent stage number information setting means
62 nth transmission line clock dependent stage number information selection means (SEL)
63 Clock accuracy judgment means
64 Network synchronization device output clock control means
65 First transmission path clock priority / dependent stage number information setting means
66 nth transmission line clock priority / dependent stage number information setting means

Claims (9)

In the clock synchronization switching device provided in each node of the slave synchronization network that sequentially synchronizes with the clock of the master node,
Predetermined information related to clock switching control extracted by the interface unit that terminates each signal connection with the transmission line, and a clock generated by the interface unit that terminates each signal connection with the external network synchronization device A clock switching control unit that performs arbitration control of a clock path based on predetermined information related to switching control, wherein the type of each predetermined information to be arbitrated is determined between a transmission path extraction clock and a network synchronization device output clock. A clock synchronous switching device, comprising: a unit that performs arbitration management uniformly by unifying them without distinction .   The predetermined information includes clock priority information and clock dependent stage number information, and the clock switching control unit includes the first operation mode in which arbitration control is performed based only on the clock priority information, the clock priority information, and the clock dependent stage number information. 2. The clock synchronization switching device according to claim 1, further comprising a second operation mode for performing arbitration control based on the second operation mode, wherein each operation mode can be switched manually or automatically. The clock switching control unit automatically switches to the second operation mode when the clock priority information higher than the selected priority is input when performing the switching control in the first operation mode, 3. The clock synchronization switching apparatus according to claim 2, wherein after the arbitration of a new clock path in the second operation mode, the operation automatically switches back to the first operation mode. The clock dependent stage number information includes the network synchronous apparatus dependent stage number information indicating the number of stages dependent on the external network synchronous apparatus, and the clock switching control unit determines that the network synchronous apparatus dependent stage number is smaller when the clock priority information is the same. 3. The clock synchronous switching device according to claim 2, wherein arbitration is selected preferentially. The clock dependent stage number information includes in-device dependent stage number information indicating the number of stages dependent on the clock source in the apparatus, and the clock switching control unit has the smaller in-device dependent stage number information when the network synchronous device dependent stage number is the same. 5. The clock synchronous switching device according to claim 4, wherein arbitration is selected preferentially.   The clock switching control unit includes a network synchronization device output clock arbitration unit that performs arbitration selection of a clock source to be output to the network synchronization device based on each predetermined information related to the clock switching control extracted or generated by each interface unit, and 2. The clock synchronization switching apparatus according to claim 1, further comprising: an in-apparatus clock arbitration unit that selects an in-apparatus clock source based on the predetermined information. The clock switching control unit provides an external network synchronization device with the first clock signal selected by the network synchronization device output clock arbitration means, and the second clock signal synchronously reproduced by the network synchronization device. 7. The clock according to claim 6 , wherein arbitration is selected by the internal clock arbitration means, and clock priority information relayed and output by the local station is set to clock priority information set in advance in the second clock signal. Synchronous switching device. The clock accuracy information is associated with each clock source existing in the network, and the clock source selected by the network synchronizer output clock arbitration means is provided with means for blocking the output of the clock when belonging to the low accuracy class. The clock synchronous switching device according to claim 6 .   The input or output transmission path interface unit includes predetermined information setting means related to clock switching control, and the setting means replaces the predetermined information extracted from the input transmission path or the predetermined information mounted on the output transmission path. The clock synchronous switching device according to claim 1, wherein the setting information can be inserted.

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