JPH09116425A - Clock supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent one phase locked loop circuit(PLL) from being affected even in the case of the occurrence of abnormality in the other with respect to a clock supply circuit having dual PLLs. SOLUTION: When a fault detection circuit 5 or 6 of a current PLL circuit 1 or 2 detects a fault or fault detection circuits 5 and 6 of both PLL circuits 1 and 2 detect faults, first and second switch parts 3 and 4 give output signals of PLL circuits to each other as input signals, and these first and second switch parts 3 and 4 are so controlled by switching so that their turning-on/off states are opposite. Otherwise when the occurrence of abnormality of one of first and second reference oscillators is detected in accordance with output signals of fault detection circuits of first and second reference oscillators or PLL circuits to which one of output signals of reference oscillators is inputted through switch parts in common are faulty together, the normal reference oscillator or the reference oscillator which is not selected at present is selected by switching.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply circuit, and more particularly to a clock supply circuit having a dual clock supply source.

In recent years, in order to improve the reliability of the communication device, it is required to duplicate the communication device into an active system and a standby system.

For this reason, for example, also in a wireless device, a hot standby type wireless transmission section is used as shown in FIG.

That is, the transmission signal is the hybrid circuit 3
At 0, it is separated into two signals, and one transmission signal is B-U
A first system SYS1 including a (bipolar-unipolar) conversion board 31, a transmission digital processing board (TDPU) 32, a modulation board (MOD) 33, and a transmission board (TX) 34.
Becomes a transmission output via B, and the other transmission signal is B-U
The output is transmitted via the second system SYS2 which is composed of the conversion board 35, the transmission digital processing board 36, the modulation board 37, and the transmission board 38.

As described above, the wireless transmission unit is duplicated, and when the active system is switched so that the system does not go down due to the failure of each unit, the clock supply source prevents the clock from being interrupted by the switching of the clock. It is also necessary to duplicate.

[0005]

2. Description of the Related Art FIG. 10 shows a conventional clock supply circuit in which a clock supply source is duplicated.
In FIG. 1A, in the first system SYS1, the transmission digital processing boards 32 and 36 are oscillators (OSC) 3
9 supplies a common reference clock, the modulators (MOD) 33 and 37 share the oscillator 40, and the transmitters 34 and 38 also have an oscillator 41.
The clock sources are shared by sharing the above.

Further, the conventional example shown in FIG.
It is a technique proposed in Japanese Patent No. 6-169435,
A phase comparator 1a, a low-pass filter (LPF) 1b, an amplifier (AMP) 1c, and a voltage controlled oscillator (VCO) 1d. The output clock of the voltage controlled oscillator 1d is used as one comparison input of the phase comparator 1a. A synchronous oscillating circuit (hereinafter, may be simply referred to as a PLL) 1 and a PLL 2 having the same configuration are used, and the PLL 1 is provided, for example, in the transmission digital processing board 32 in the first system SYS 1 in the example of FIG. PLL2 to the second system SYS2
In the transmission digital processing board 36, the output clock of PLL1 is used as the other comparison input of the phase comparator 1a of PLL2, and the output clock of PLL2 is used as the other comparison input of the phase comparator 1a of PLL1.

In operation, the output clocks of the other PLLs are used as comparison inputs for comparing with the output clocks of their own PLLs. Therefore, for example, the output clocks of the transmission digital processing boards 32 and 36 have the same phase. Can be synchronized with each other.

Further, the conventional example shown in FIG. 10 (3) is a technique proposed in Japanese Patent Laid-Open No. 3-201822, in which PLL1 and PLL2 shown in FIG. 2 (2) are used, but they are mutually output. The reference oscillators 11 and 12 are independent of each other without adopting a configuration of inputting clock and.
And receives a reference clock from these reference oscillators 11 and 12.

The system composed of the reference oscillator 11 and the PLL 1 is used as the master side, and normally, the output clock of the reference oscillator 11 on the master side is commonly given to the PLL 2 on the slave side via the changeover switch 50. ing.

As a result, normally, PLL1 and PLL
Reference numeral 2 outputs the output clocks and based on the output clock from the reference oscillator 11.

The state of the output clock of the reference oscillator 11 is constantly monitored by the failure detection circuit 51. When the failure detection circuit 51 detects a failure of the reference oscillator 11, the changeover switch 50 is referenced from the reference oscillator 11 side. By switching to the oscillator 12 side, the reference clock is also given from the reference oscillator 12 to the PLL 1 on the master side so that an output clock can be obtained.

[0012]

In the case of the conventional example shown in FIG. 10 (1), the first and second systems SY are provided.
Since the transmission digital processing boards 32 and 36, the modulation boards 33 and 37, and the transmission boards 34 and 38 are operated by the output clocks of the oscillators 39 to 41 common to S1 and SYS2, respectively, when these common oscillators fail. Is system S
There is a problem that both the YS1 and the SYS2 systems are out of order.

Also, in the case of the conventional example shown in FIG. 2B, when one of the PLL output clocks becomes abnormal, as a result, both PLL outputs become abnormal, resulting in a radio transmission signal. There is a problem of causing an error.

Further, in the case of the conventional example shown in FIG. 3C, when the reference oscillator 11 on the master side fails, the output clock from the PLL2 can operate, but the output clock from the PLL1. Will be in a failure state until the reference oscillator 11 returns to a normal state, and again in this case, it will cause an error in the wireless transmission signal.

Therefore, the present invention provides a clock supply circuit in which a phase locked oscillator (PLL) is duplicated,
An object of the present invention is to realize a clock supply circuit without affecting the other PLL even when one of the PLLs has an abnormality.

[0016]

[Means for Solving the Problems]

[1] In order to achieve the above object, a clock supply circuit according to the present invention includes first and second phase-locked oscillator circuits 1 and 2 and one of the phase-locked oscillators, as shown in principle in FIG. Output signals of the phase-locked oscillator circuits 1 and 2, and first and second switch units 3 and 4 for mutually synchronizing by giving the output signal of the circuit (PLL) to the other phase-locked oscillator circuit as an input signal. Of the first and second failure detection circuits 5 and 6 for detecting the abnormality of the switch and the failure detection circuit of the currently used phase-locked oscillator circuit outputs a failure detection signal. And a circuit 7 that controls switching so that the OFF states are opposite to each other.

In the operation of the present invention, when the first phase-locked oscillator circuit 1 is in use as shown in the figure, the switching control circuit 7 turns off the first switch section 3 and turns on the second switch section. By controlling 4 to ON, system S
Mutual synchronization is achieved by using the output clock of the first phase-locked oscillator circuit 1 in YS1 as the input clock of the second phase-locked oscillator circuit 2 in system SYS2.

In such a state, the first failure detection circuit 5
Detects a failure of the output clock from the first phase-locked oscillator circuit 1, this detection signal indicates the switching control circuit 7
Since the switching control circuit 7 cannot use the output clock of the first phase-locked oscillator circuit 1, the first switch unit 3 is turned on and the second switch unit 4 is turned off. By doing so, the second phase-locked oscillator circuit 2 is used as the active system, the first phase-locked oscillator circuit 1 is used as the standby system, and the standby system is used as the standby system based on the output clock from the second phase-locked oscillator circuit 2. Phase-locked oscillator circuit 1
Are trying to synchronize each other.

Further, in the state of FIG. 1, when the switching control circuit 7 is informed that the second failure detection circuit 6 has detected the failure of the output clock from the second phase locked oscillator circuit 2, the switching control is performed. Since the first phase-locked oscillator circuit 1 is normal, the circuit 7 does not perform switching control and maintains the illustrated state.

That is, the ON / OFF states of the first switch unit 3 and the second switch unit 4 are controlled only when the failure of the active phase-locked oscillator circuit is detected, so that the states are reversed. I am trying.

[2] In the above invention [1], the first
And the second phase-locked oscillator circuits 1 and 2 simultaneously fail, the first failure detection circuit 5 and the second failure detection circuit 6
Upon receiving the failure detection signal from the switching control circuit 7, the switching control circuit 7 performs switching control so that the ON / OFF states of the first switch unit 3 and the second switch unit 4 are opposite to each other.

That is, when the phase-locked oscillator circuits 1 and 2 are in the failure state at the same time in the state of FIG. 1, the switching control circuit 7 turns on the first switch section 3 and turns on the second switch section 4. Switching control is performed so that it is turned off.

[3] In the present invention, as shown in principle in FIG. 2, first and second reference oscillators 11 and 12,
By selecting the output signals of the first and second phase-locked oscillator circuits 1 and 2 and one of the reference oscillators and applying them as input signals to the first and second phase-locked oscillator circuits 1 and 2, respectively. First and second switch units 13 and 14 for mutual synchronization, and first and second failure detection circuits 15 for detecting an abnormality in output signals of the reference oscillators 11 and 12,
16 and both switch parts 13 and 14 so as to select a normal reference oscillator when it is detected from the output signals of the first and second failure detection circuits 15 and 16 that one reference oscillator is abnormal. And a circuit 19 for switching control.

In the operation of the present invention, assuming that the first switch section 13 and the second switch section 14 are switching-controlled as shown in the figure, the output clock from the first reference oscillator 11 becomes the first clock. The phase-locked oscillator circuit 1 and the second phase-locked oscillator circuit 2 are commonly supplied to the system S.
It is provided as the output clocks of YS1 and SYS2.

In this state, for example, the first reference oscillator 11
When the first failure detection circuit 15 detects this, the switching control circuit 19 receiving the detection signal from the first failure detection circuit 15 causes the first switch unit 13 and the second switch unit 14 to operate. Switching control is performed so that both are connected to the second reference oscillator 12.

As a result, the normal second reference oscillator 12
Is applied to the first and second phase-locked oscillator circuits 1 and 2 to output the system SYS1 and S, respectively.
It will be given as the output clock of YS2.

[4] In the above-mentioned present invention [2], the third
Fault detection circuit 17 monitors the state of the first phase-locked oscillator circuit 1, and the fourth fault detection circuit 18 monitors the second phase-locked oscillator circuit 2 to switch the monitoring result. It is given to the circuit 19.

As a result, both the third and fourth failure detection circuits 17 and 18 are connected to the first and second phase-locked oscillator circuit 1.
And failure 2 are detected and the detection result is switched control circuit 1
When it is given to 9, it can be judged that it is not the failure of the phase-locked oscillator circuits 1 and 2 itself but the failure of the reference oscillators 11 and 12 (for example, frequency deviation). Therefore, the first switch unit 13 and the second switch If the section 14 is in the state as shown in the figure, the switching control circuit 19 selects the first reference oscillator which is not currently selected, that is, the output clock of the second reference oscillator 12. The first and second phase-locked oscillator circuits 1 and 2 are controlled based on the output clock from the second reference oscillator 12 to control the system SYS.
Output clocks of 1 and SYS2.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an embodiment (part 1) of a clock supply circuit according to the present invention [1]. In this embodiment, first and second phase-locked oscillator circuits 1 and 2 are provided. As the configuration of No. 2, as in the conventional example shown in FIG. 10 (2), the phase comparator 1a, the low-pass filter 1b, the amplifier 1c, and the voltage-controlled oscillator 1d are connected in series.

Further, the first and second switch sections 3 and 4
AND gate is used as
Output clock and control signal CO from the switching control circuit 7
NT1 is input and its output is given to the phase comparator 1a as a comparison input, and the AND gate 4 outputs the output clock of the PLL1 and the control signal CONT2 from the switching control circuit 7.
And are input, and the output is given to the phase comparator 2a as a comparison input.

The output signals from the failure detection circuits 5 and 6 to the switching control circuit 7 are ALM1 and ALM2, respectively. The rest of the configuration is similar to that shown in FIG.

The operation of the embodiment shown in FIG. 3 will be described below with reference to the operation explanatory diagram of the switching control circuit 7 shown in FIG.

(1) Now, for example, the transmission digital board TDPU in the system SYS1 (see "3 in FIG. 10 (1)").
2)), the output clock of PLL1 is used as the active system.
It is in a form synchronized with each other.

In such a state, the transmission digital board TDPU ("3" in FIG. 10 (1) in the system SYS1 is used.
6)), and the failure detection circuit 6 sets its output signal ALM2 to the H level to indicate that an alarm has occurred, the switching control circuit 7 outputs the control signal CO2.
The AND gate 3 is disabled by setting NT1 to L level and the control signal CONT2 is set to H level to AN.
The D gate 4 is enabled.

That is, it means that when the PLL on the spare side fails, the working / standby switching is not performed.

(2) On the contrary, when the PLL 2 is currently in use, the AND gate 3 is enabled and the AND gate 4 is disabled, the PLL is
When an abnormality occurs in 1, the output signal ALM1 from the failure detection circuit 5 becomes H level and the generation of an alarm is transmitted to the switching control circuit, but the switching control circuit 7 enables the AND gate 3 and the AND gate 4 Is disabled.

That is, also in this case, similarly to the above (1), the states of the AND gates 3 and 4 do not change before and after the failure detection, and when the PLL on the spare side becomes abnormal, the active / active state is set. This indicates that the spare switching is not performed.

(3) Similar to the above (1), when an abnormality occurs in the PLL1 when the PLL1 is in use, the output signal ALM1 of the failure detection circuit 5 becomes H level and the generation of an alarm is sent to the switching control circuit 7. As will be informed, the switching control circuit 7 sets the control signal CONT1 to H level, and the control signal CONT2
Is set to the L level, the AND gate 3 is enabled and the AND gate 4 is disabled.

As a result, when an abnormality occurs in the active PLL 1, the active / standby switching is performed.

(4) Similar to (2) above, when an abnormality occurs in the PLL2 when the PLL2 is in use, the output signal ALM2 of the failure detection circuit 6 becomes H level and an alarm signal is given to the switching control circuit 7. However, the switching control circuit 7 sets the control signal CONT1 to L level and sets the control signal CONT2 to H level.
By setting the level, the AND gate 3 is disabled and the AND gate 4 is enabled.

Therefore, also in this case, the active / standby switching is performed because the active PLL has become abnormal as in (3) above.

(5) PL as in (1) and (3) above
When an abnormality occurs in both PLL1 and PLL2 when L1 is in use, the output signals ALM of the failure detection circuits 5 and 6
Both 1 and ALM2 become H level and notify the switching control circuit 7 that an alarm has occurred.

As a result, the switching control circuit 7 causes the control signal CO
By setting NT1 to H level and the control signal CONT2 to L level, the AND gate 3 is enabled and the AND gate 4 is disabled.

That is, when both the active and standby PLLs become abnormal, the active / standby switching is performed.

(6) PL as in (2) and (4) above
When both PLL1 and PLL2 are in an abnormal state when L2 is in use, the failure detection circuits 5 and 6 both become H level and notify the switching control circuit 7 that an alarm has occurred, as in (5) above.

In response to this, the switching control circuit 7 sets the control signal CONT1 to L level and CONT2 to H level to disable the AND gate 3 and enable the AND gate 4.

Therefore, also in this case, when both the working and protection PLLs 1 and 2 are in an abnormal state, the working / protection switching is performed in the same manner as in (5) above.

Although not shown in FIG. 4, when the failure detection circuits 5 and 6 are both at the L level, the switching control circuit 7 maintains this state because the working and protection PLLs are normal. It goes without saying that it is something to do.

FIG. 5 shows an embodiment (No. 2) of the clock supply circuit according to the present invention [1]. In this embodiment, the PLLs 1 and 2 shown in FIG. 3 are modified, and FIG.
Instead of directly supplying the output clocks of the voltage controlled oscillators 1d and 2d to the phase comparators 1a and 2a as in the above embodiment, the frequency dividers 1e and 2e are provided and the voltage controlled oscillators 1d and 2d are provided.
The output clock of 2d is converted into a 1 / N frequency-divided signal and input to the phase comparators 1a and 2a.

In this embodiment, the system SYS1
And the output clocks of the SYS2 are given to the modulation boards MOD1 and MOD2 (corresponding to "33" and "37" in FIG. 10 (1)), respectively, and the output clocks 'and' from the frequency dividers 1e and 2e are the system respectively. SYS
1 and SYS2 transmission digital boards TDPU1 and TD
PU2 (corresponding to “32” and “36” in FIG. 10 (1))
Is to be given.

Further, in the AND gates 3 and 4, instead of inputting the output signals of the voltage controlled oscillators 1d and 2d as in the embodiment of FIG. 3, the output signals of the frequency dividers 1e and 2e are input. Are different.

The operation of this embodiment is similar to that of the embodiment (1) shown in FIG. 3, and the working / standby switching is carried out only when a failure occurs in the working PLL.

That is, when the PLL 1 is in use and the failure detection circuit 5 detects a failure based on its output signal, the switching control circuit 7 enables the AND gate 3 and disables the AND gate 4. The control signals CONT1 and CONT2 are generated so that the output signal of the frequency divider 2e in the PLL2 is supplied as a comparison input to the phase comparator 1a in the PLL1 through the AND gate 3, and the PLL2 becomes the active system, and the PLL becomes the active system.
1 serves as a standby system and mutually synchronizes with the currently used PLL 2.

FIG. 6 shows an embodiment (1) of the clock supply circuit according to the present invention [2]. In this embodiment, a selector (SEL) is used as the first and second switch sections 13 and 14. 13 and 14 are used, and out-of-synchronization detection circuits are used as the failure detection circuits 17 and 18.

As the configuration of PLL1 and PLL2, the phase comparators 1a and 2a, the low pass filters 1b and 2b, the amplifiers 1c and 2c, the voltage controlled oscillators 1d and 2d, and the frequency divider 1e are arranged as in the embodiment shown in FIG. , 2e. The failure detection circuits 15 and 16 output the output signal AL.
M11 and ALM21 are given to the switching control circuit 19, and the out-of-synchronization detection circuits 17 and 18 output signals ALM12 and ALM.
The LM 22 is given to the switching control circuit 19. Other configurations are the same as those shown in FIG.

FIG. 7 is an operation explanatory view of the switching control circuit 19 in the embodiment shown in FIG. 6. The operation of the embodiment (part 1) of FIG. 6 will be described below with reference to FIG. .

(1) If the switching control circuit 19 is controlling the selectors 13 and 14 to select the reference oscillator 11 and the reference oscillator 11 is abnormal due to signal disconnection or the like, the failure detection circuit is assumed. Output signal ALM from 15
The switching control circuit 19 notifies the switching control circuit 19 of the occurrence of an alarm when 11 becomes H level.
By setting NT1 to the H level and the control signal CONT2 to the L level, the reference oscillator 12 is selected and controlled so that its output clock is given to the PLL1 and the PLL2.

At this time, it is assumed that the out-of-synchronization detection circuits 17 and 18 each generate a normal output (L level).

(2) Now, assuming that the selectors 13 and 14 select the output clock of the reference oscillator 12 by the control signal from the switching control circuit 19 and apply it to the PLL1 and PLL2, the reference oscillator 12 at this time. If an abnormality such as a signal disconnection occurs in the switch, the output signal ALM21 of the failure detection circuit 16 goes to the H level to notify the switch control circuit 19 of the occurrence of the alarm. Therefore, the switch control circuit 19 sets the control signal CONT1 to the L level. By setting the control signal CONT2 to the H level, the output clock of the reference oscillator 11 is selected and the switching control is performed so that the output clock is commonly applied to the PLL1 and the PLL2.

At this time as well, it is assumed that the out-of-synchronization detection circuits 17 and 18 each generate a normal output (L level).

(3) The reference oscillator 11 as in (1) above.
Out of synchronization detection circuits 17 and 18
If both of them detect the occurrence of an abnormality, the output signal ALM
12 and ALM 22 both become H level to notify the switching control circuit 19 of the occurrence of the alarm, so that the switching control circuit 19 sets the control signal CONT1 to H level and the control signal C
By setting the ONT 2 to the L level, the reference oscillator is switched from the reference oscillator 11 to the reference oscillator 12.

This indicates that the out-of-synchronization detection circuits 17 and 18 both detect the out-of-synchronization, not the abnormality of the PLL1 and PLL2 itself, but the frequency deviation on the side of the reference oscillators 11 and 12 in the preceding stage, for example. The reference oscillator is selected and switched.

(4) Similar to (2) above, the reference oscillator 12
Is selected, and PLL1 and P are selected as in (3) above.
When an abnormality commonly occurs in LL2 and the output signals ALM12 and ALM22 of the out-of-synchronization detection circuits 17 and 18 both become H level to notify the switch control circuit 19 of the occurrence of the alarm, the switch control circuit 19 sends the signal to the selector 13. The control signal CONT1 is set to the L level, the control signal to the selector 14 is set to the H level, and the output clock of the reference oscillator 11 is selected.

That is, also in this case, since both PLLs are abnormal, the reference oscillator is selectively switched.

In the operation explanatory view of FIG. 7,
As a matter of course, even if a failure occurs in the reference oscillator that is not selected by the selectors 13 and 14, the switching control circuit 19 does not perform the switching control.

FIG. 8 shows an embodiment (No. 2) of the clock supply circuit according to the present invention [2]. In this embodiment, the selector 13 is provided between the selector 13 and the phase comparator 1a of the PLL1. A frequency divider 21 for frequency-dividing the output signal by 1 / M is provided, and 1 is similarly provided between the selector 14 and the phase comparator 2a.
The difference from the embodiment (part 1) in FIG. 6 is that a frequency divider 22 for performing / M frequency division is inserted.

In the case of this embodiment, the frequency dividers 21 and 2 are
By inserting 2, the frequency division ratio (1 / N) of the frequency dividers 1e and 2e in the PLL1 and PLL2 also changes.

Also in the operation of this embodiment, the switching control circuit 19 causes the selector 13 to operate when an abnormality occurs in the currently used reference oscillator as in the operation shown in FIG.
By controlling 14 and 14, the reference oscillator of the standby system is selectively switched, and when an abnormality occurs in the working and standby PLLs, the selective switching of the reference oscillator is similarly performed.

[0069]

As described above, according to the clock supply circuit of the present invention, when the failure detection circuit of the active phase-locked oscillator circuit detects a failure and the failure detection circuit of both phase-locked oscillator circuits. When the failure is detected, the output signal of one phase-locked oscillator circuit is applied to the other phase-locked oscillator circuit as an input signal.
Since the switching control is performed so that the N / OFF state is reversed, it is possible to prevent the other system from being affected when there is an abnormality in one PLL.

Further, according to the present invention, when it is detected from one of the output signals of the failure detecting circuits of the first and second reference oscillators that one of the reference oscillators is abnormal, and when any of the output signals of these reference oscillators is detected. When both phase-locked oscillator circuits that commonly input
Since it is configured to select the normal reference oscillator or the reference oscillator that is not currently selected, when one PLL has an abnormality, it should not affect the other system. You can

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle configuration of a clock supply circuit according to the present invention [1].

FIG. 2 is a block diagram showing a principle configuration of a clock supply circuit according to the present invention [2].

FIG. 3 is a block diagram showing an embodiment (1) of the clock supply circuit according to the present invention [1].

FIG. 4 is an operation explanatory diagram of the switching control circuit 7 shown in FIG.

FIG. 5 is a block diagram showing an embodiment (No. 2) of the clock supply circuit according to the present invention [1].

FIG. 6 is a block diagram showing an embodiment (1) of the clock supply circuit according to the present invention [2].

7 is an operation explanatory diagram of the switching control circuit 19 shown in FIG.

FIG. 8 is an embodiment (No. 2) of the clock supply circuit according to the present invention [2].

FIG. 9 is a block diagram showing a configuration of a hot standby type wireless transmission unit.

FIG. 10 is a block diagram showing a conventional example.

[Explanation of symbols]

1, 2 Phase-locked oscillation circuit (PLL) 3, 4, 13, 14 Switch section (AND gate, selector) 5, 6, 15, 16, 17, 18 Fault detection circuit 7, 19 Switching control circuit 11, 12 Reference oscillator In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A first and second phase-locked oscillator circuit, and first and second circuits for mutually synchronizing by giving an output signal of one phase-locked oscillator circuit as an input signal to the other phase-locked oscillator circuit. Switch section, first and second failure detection circuits that detect an abnormality in the output signal of each phase-locked oscillation circuit, and when the failure detection circuit of the active phase-locked oscillation circuit outputs a failure detection signal ON / OF of both switch parts
A clock supply circuit comprising: a circuit that controls switching so that the F states are opposite to each other. 2. The switching control circuit according to claim 1, wherein the switching control circuit turns on / off both switch parts even when the failure detection circuit of both phase-locked oscillator circuits outputs a failure detection signal.
A clock supply circuit characterized by performing switching control so that OFF states are opposite to each other. 3. A first and a second reference oscillator, a first and a second phase-locked oscillation circuit, and an output signal of one of the reference oscillators is selected to select the first reference oscillator.
And first and second switch parts for mutually synchronizing by giving them as input signals to the second and second phase-locked oscillator circuits, and first and second switches for detecting an abnormality in the output signal of each reference oscillator.
Of the failure detection circuit and the output signals of the first and second failure detection circuits, and controls switching of both switch units so as to select a normal reference oscillator when an abnormality is detected in one of the reference oscillators. A clock supply circuit comprising: a circuit. 4. The third and fourth failure detection circuits for detecting an abnormality in an output signal of each phase-locked oscillator circuit according to claim 3, wherein both output signals of the third and fourth failure detection circuits are detected. A clock supply circuit characterized in that when the failure of the phase-locked oscillator circuit is detected, the switching control circuit switches and controls both switch parts so as to select the reference oscillator which is not currently selected.