JPH0652975B2 - Uninterruptible power system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a plurality of inverters that are operated in parallel and a commercial power source, etc. in synchronization with a common frequency reference signal from a commercial power source or the like. The present invention relates to an uninterruptible power supply device that can be fed with either a direct power supply or a power supply, and particularly to an uninterruptible power supply device that stably continues parallel operation of inverters even when a common reference signal such as a commercial power supply is abnormal.

(Prior Art) In an uninterruptible power supply system using inverters, in order to improve its reliability, it is possible to operate a plurality of inverters in parallel and configure them with sufficient redundancy for the load capacity. Many.

In addition, the common output of the parallel operation inverter and the direct power supply such as commercial power can be switched by the changeover switch, so that if a serious malfunction such as a failure occurs in this parallel operation inverter, this direct change power supply By switching to, it is possible to continuously supply power to the load. This configuration improves the reliability of power supply to the load. In such an uninterruptible power supply, it is necessary that the output phases of the inverters match each other and the output phase of the inverters also match the phase of the direct power supply.

FIG. 2 is a block diagram showing a conventional control device for parallel operation of such inverters. In the figure, the first machine and the second machine are distinguished by adding subscripts a and b. 1a and 1b are direct current buses, to which a rectifier (not shown) for converting alternating current to direct current, a storage battery, or a direct current voltage obtained by using both of them together is supplied. 2a, 2b are inverters 3a, 3b for alternating the voltage of this DC bus are AC filters for improving the waveform of the inverter output into a sine wave, 4a, 4b are circuit breakers for performing parallel closing or parallel disconnection of each inverter, Reference numeral 5 is a commercial power supply serving as a direct power supply, 6 and 7 are static changeover switches (semiconductor switches) for switching between the inverter and the direct power supply without interruption, and 8 is a load.

On the other hand, the control device is a phase difference detector (PHD) 111a, 111b,
A synchronous control circuit (hereinafter referred to as P) including low pass filters (LPF) 112a and 112b and voltage controlled oscillators (VCO) 113a and 113b.
11a, 11b and ring counters 12a, 12b that generate gate pulses of each inverter by dividing the outputs of the PLL circuits 11a, 11b and the active power supplied by each inverter. Of the active power deviation (Δ) given to the low-pass filters 112a, 112b of the PLL circuits 11a, 11b.
P) Detection circuits 13a, 13b and phase correction circuits 17a, 17b, and direct transmission power supply determination circuits 15a, 15b for detecting an abnormality of the direct transmission power supply 5,
It is composed of phase reference changeover switches 16a and 16b for switching from the direct power supply 5 to the oscillators 14a and 14b as the phase reference of the PLL circuits 11a and 11b when the direct power supply is abnormal.

It should be noted that, in practice, voltage control for correcting the deviation of the reactive power is also necessary as control for operating the inverters in parallel, but it is omitted here.

The PLL circuit used for the synchronous control is a known technique, and the detailed operation of the configuration for correcting the deviation by feeding back the active power deviation of each inverter output to the synchronous control circuit as described above is described in Japanese Patent No. 1215332. Parallel operating device ".

The ΔP detection circuit 13 is a PLL when the direct power source 5 has an abnormality such as a power failure.
It is provided to correct the deviation of the active power sharing caused by the phase shift due to the frequency deviation of the oscillators 14a, 14b that are the phase reference of the circuits 11a, 11b, and give the deviation of the active power sharing to the low-pass filters 112a, 112b. The output frequency and phase of the voltage controlled oscillators 113a and 113b are automatically controlled so that the deviation becomes zero.

(Problems to be Solved by the Invention) However, in the above configuration, the oscillator 14a,
At the time of an abnormality such as a power failure in which the output of 14b is used as the phase reference of the PLL circuits 11a and 11b, the output frequencies of the oscillators 14a and 14b do not completely match due to individual differences, and the inverter outputs of the respective inverters are momentarily changed. The phase difference changes. For this reason, it is necessary to make the gain K of the phase correction circuits 17a and 17b considerably high so as to perform the phase correction sufficiently. However, on the contrary, the offset included in the active power deviation detection circuits 13a and 13b and the phase correction circuits 17a and 17b is also amplified by the high gain K and appears, so that the offset is easily affected by the temperature drift and the drift over time, and the circuit is adjusted. It wasn't easy either.

Also, the means for detecting the active power deviation is not necessarily a simple structure, including the parts to be exchanged by 13a, 13b and each organization, and the signals exchanged with each other are analog signals, and temperature drift and drift over time. Can not escape from the influence of.

Therefore, the present invention has been made in view of the above points, and is less susceptible to temperature drift and drift over time,
To provide an uninterruptible power supply consisting of multiple inverters that are always synchronized with a direct power supply such as a commercial power supply and that is equipped with a simple control device so that stable parallel operation can be continued even when the commercial power supply fails. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an output of a plurality of inverters that are operated in parallel or an output of a direct power supply such as a commercial power supply. In an uninterruptible power supply capable of supplying power to a load by selecting with a changeover switch, a first synchronous control circuit commonly provided to the plurality of inverters, and an output frequency of an inverter provided to each of the plurality of inverters. A second synchronization control circuit for controlling a frequency signal synchronized with the first frequency reference signal when the first frequency reference signal obtained from the direct power supply is normal. Is output as a second frequency reference signal, and when the first frequency reference signal is abnormal, the free-running oscillation frequency signal of the first synchronization control circuit itself is used as the second frequency reference signal. The second synchronization control circuit has a function of outputting, and outputs the signal synchronized with any one of the frequency reference signals to which the first frequency reference signal and the second frequency reference signal are applied. , If the first and second frequency reference signals are both abnormal, then the second
The synchronization control circuit itself has a function of outputting a free-running oscillation frequency signal.

(Operation) With the configuration described above, the first synchronization control circuit causes the second frequency signal synchronized with the first frequency reference signal to be transmitted to the second frequency signal when the first frequency reference signal obtained from the direct power source is normal. It is output as the frequency reference signal of. Therefore, the first frequency reference signal and the second frequency reference signal input to the second synchronization control circuit of each inverter are exactly the same.

Next, if the first frequency reference signal becomes abnormal due to a power failure or the like, the first synchronous control circuit determines that the first frequency reference signal is abnormal, and the synchronous control circuit itself oscillates. The frequency signal is output as the second frequency reference signal. Therefore, the second frequency reference signal, which was synchronized with the first frequency reference signal until immediately before the occurrence of the abnormality, is switched to the free-running oscillation frequency signal without interruption, so that the second phase reference signal which is also common to the inverters is used. The frequency and the phase are switched to the frequency reference signal without jumping. The free-running oscillation frequency signal output from the first synchronous control circuit is set to a value that does not exceed the abnormality determination standard in the second synchronous control circuit of each inverter.

Therefore, regardless of whether the first frequency reference signal obtained from the direct power supply 5 is normal or abnormal, each inverter is synchronized with the second synchronization reference signal that is the output of the first synchronization control circuit that has been uninterrupted. It operates and the output of the UPS is stable and smooth.

Further, even if the first synchronous control circuit fails, the second synchronous control circuits of all the inverters individually judge the abnormality of the second frequency reference signal, and the second synchronous control circuit determines the first frequency. Each inverter is controlled so as to be synchronized with the reference signal.

Further, even if the second frequency reference signal input to the second synchronization control circuit is not input to the second synchronization control circuit due to the disconnection on the input terminal side, the disconnected second synchronization control circuit is Of the frequency reference signal is determined, and the inverter is controlled so as to synchronize with the first frequency reference signal. First
Since the frequency reference signal of No. 2 and the second frequency reference signal to be originally input are exactly the same, the broken inverter on the side of the second synchronous control circuit continues to operate in synchronization with another inverter.

Therefore, even if an abnormality occurs in the first synchronous control circuit and its peripheral circuits, which are common parts, due to the uninterruptible power supply having such a configuration, all the inverters are synchronized with the same frequency reference and the uninterruptible power supply is provided. The output of can maintain stable and smooth operation.

(Embodiment) An embodiment of the present invention will be described below with reference to the block diagram of FIG.

In FIG. 1, the same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. Here, different points will be described.

That is, in FIG. 1, the first synchronous control circuit 18 is a storage battery 2 for making the output frequency reference signal uninterruptible.
1. The power supply 22 of the first synchronous control circuit is made uninterruptible by the storage battery 21.

The first synchronization control circuit 18 includes a determination circuit 181 for determining an abnormality of the first frequency reference signal obtained from the direct power source 5 such as a commercial power source, and a PLL for determining that the first frequency reference signal is abnormal. The circuit 183 itself comprises a selection circuit 182 for instructing the PLL circuit 183 to output a free-running oscillation frequency. The selection circuit 182 further causes the PLL circuit 183 to send the first signal to the PLL circuit 183 when it is determined that the first frequency reference signal is normal.
Command to output a signal synchronized with the frequency reference signal of. As a result, the free-running oscillation frequency of the PLL circuit 183 becomes a signal synchronized with the first frequency reference signal, the signal synchronized with this first frequency reference signal becomes the second frequency reference signal, and the first synchronization control circuit Is output from.

Therefore, when the first frequency reference signal obtained from the direct power supply is normal, the first synchronization control circuit 18 outputs the frequency signal synchronized with the first frequency reference signal as the second frequency reference signal, When the first frequency reference signal is abnormal, the free-running oscillation frequency signal of the synchronization control circuit itself is output as the second frequency reference signal.

Second synchronous control circuit provided in each inverter
Reference numeral 19 denotes a determination circuit 191 that determines whether or not the first frequency reference signal and the second frequency reference signal are applied to determine whether the reference signals are abnormal, and a PLL circuit 193 that determines the first frequency reference signal according to the determination result. The selection circuit 192 outputs a command to output a synchronized signal and a command to output a signal synchronized with the second frequency reference signal. In addition, the PLL circuit 193, when both the first and second frequency reference signals are abnormal, the PLL circuit 193
The L circuit itself has a function of outputting a free-running oscillation frequency signal that oscillates. Further, although not shown in FIG. 1, each inverter has a ΔP detection circuit 13 shown in FIG. Therefore, when the second synchronous control circuit outputs the free-running oscillation frequency signal, it is for correcting the deviation of the active power sharing caused by the phase shift due to the deviation of the free-running oscillation frequency signal. PLL circuit 19 so that
The free-running oscillation frequency of 3 is controlled.

Next, the operation of the present invention having the above configuration will be described.

When the direct power source 5 is normal, the first frequency control circuit 18
Since the determination circuit 181 of 1 determines that the first frequency reference signal is normal, the output of the first synchronization control circuit 18, that is, the second frequency reference signal is controlled so as to synchronize with the first frequency reference signal. It

In the second synchronous control circuit 19 provided in each inverter,
The first frequency reference signal and the second frequency reference signal are input. The determination circuit 191 forming the second synchronization control circuit,
It is determined that both the first and second frequency reference signals are normal. Therefore, each of the inverters 2a and 2b is controlled by the second synchronization control circuit so as to be synchronized with the frequency of the direct power supply, and the phases thereof match each other to perform stable parallel operation.

Next, when the direct power supply 5 becomes abnormal due to a power failure or the like, the determination circuit 181 of the first synchronous control circuit 18 immediately detects the abnormality, and the selection circuit 182 outputs the free-running oscillation frequency to the PLL circuit 183. Command to do so.

Determination circuit 191 of second synchronous control circuit 19 of each inverter
Determines that the second frequency reference signal is normal and the first frequency reference signal is abnormal. Therefore, each inverter 2
As in the normal state, a and 2b are controlled so as to be synchronized with the second frequency reference signal, and their phases match each other to continue stable parallel operation. That is, even if an abnormality occurs in the first frequency reference signal, stable parallel operation continues without switching both the synchronization function of the second synchronization control circuit 19 of each inverter and the synchronization reference signal.

When the direct power supply 5 is abnormal, the output of the first synchronous control circuit 18 has the free-running oscillation frequency, so that the inverters 2a and 2b also indirectly have the free-running oscillation frequency of the second synchronous control circuit 19. Will be controlled.

In this way, in this embodiment, by providing the synchronous control circuit which is operated in synchronization with the direct power supply 5 and which is made uninterrupted by the storage battery 21, even if the direct power supply is abnormal, the output of the common synchronous control circuit is changed to the frequency. Since each inverter is controlled as a reference, parallel operation control can be performed with a simple configuration that does not require phase correction due to active power deviation, and the problem of being susceptible to temperature drift and drift over time is eliminated.

Further, even if the second frequency reference signal input to the second synchronization control circuit is not input to the second synchronization control circuit due to the disconnection on the input terminal side, the disconnected second synchronization control circuit is the second synchronization control circuit. Of the frequency reference signal is determined, and the inverter is controlled so as to synchronize with the first frequency reference signal. Since the first frequency reference signal and the second frequency reference signal to be originally input are exactly the same, the disconnected inverter of the second synchronous control circuit continues to operate in synchronization with another inverter. In other words, the reference signal of each inverter is duplicated by the direct power supply and the second synchronization control circuit by the second synchronization control circuit, and it is possible to construct a highly reliable system.

In the above-mentioned embodiment, the control in the case where two inverters are operated in parallel has been described, but the present invention does not limit the number of inverters operated in parallel. Further, although the PLL circuit is provided as a component of the synchronization control circuit, it may be configured by feedback control such as digital control.

Further, in order to make the synchronous control circuit uninterruptible, a parallel output common bus voltage for coupling the outputs of the inverters may be used instead of the dedicated storage battery.

As described above, according to the present invention, the temperature drift,
It is possible to provide an uninterruptible power supply that is not easily affected by drift over time and that can stably continue parallel operation even when the frequency reference signal obtained from a direct power supply such as a commercial power supply is abnormal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an uninterruptible power supply according to the present invention, and FIG. 2 is a block diagram of a conventional uninterruptible power supply. 1a, 1b ... Directly transmitted bus, 2a, 2b ... Inverter, 3a, 3b ... AC filter, 4a, 4b ... Circuit breaker, 5a, 5b ... Directly transmitted bus, 6, 7 ... Changeover switch, 8a, 8b ... Load, 11a, 11b ... PLL circuit, 12a, 12b ... Ring counter, 13a, 13b ... .DELTA.P detection circuit, 14a, 14b ... Oscillator, 15a, 15b ... Judgment circuit, 16a, 16b ... Phase reference changeover switch, 17a, 17b ... Phase correction circuit, 18 ... first synchronization control circuit, 181 ... determination circuit, 182 ... selection circuit, 183 ... PLL circuit, 19a, 19b ... second synchronization control circuit, 191a, 191b ... determination circuit, 192a, 192b ... selection circuit, 193a, 193b ... PLL circuit, 21 ... storage battery, 22 ... power supply.

Claims (1)

[Claims] 1. An uninterruptible power supply device capable of supplying power to a load by selecting either the output of a plurality of inverters operated in parallel or the output of a direct power supply such as a commercial power supply with a changeover switch. A first synchronous control circuit provided commonly to the inverters, and a second synchronous control circuit provided to each of the plurality of inverters, wherein the first synchronous control circuit is obtained from the direct power supply. When the first frequency reference signal is normal, a signal synchronized with the first frequency reference signal is output as the second frequency reference signal, and when the first frequency reference signal is abnormal, the first frequency reference signal is output. The free-running oscillation frequency signal of the synchronization control circuit itself is set to the second
The second synchronization control circuit is applied with the first frequency reference signal and the second frequency reference signal and is synchronized with any of the frequency reference signals. If the first and second frequency reference signals are both abnormal, the second signal is output.
2. The uninterruptible power supply device having a function of outputting a free-running oscillation frequency signal of the synchronous control circuit itself, wherein each of the plurality of inverters is controlled by the second synchronous control circuit.