JP3424662B2 - Clock synchronization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit, and more particularly to a clock synchronizing circuit that can switch to another input clock signal when the input clock signal is abnormal.

[0002]

2. Description of the Related Art A conventional clock synchronizing circuit of this type will be described with reference to the drawings.

FIG. 4 is a block diagram showing an example of a conventional clock synchronization circuit.

In FIG. 4, this conventional example is disclosed in Japanese Patent Laid-Open No. 8-
The disclosed content of Japanese Patent No. 228149, showing the reference signal CK1
If the input is disconnected for a certain period or longer, the phase comparison result determination circuit 152 outputs an asynchronous detection signal, and the input disconnection detection circuit
1 40 outputs a switching signal to output switching a reference signal CK2 to the selector 130, the switch control circuit 153 supplies a reference signal CK2 switch 154 opening control to the phase locked loop by an input switching signal and the asynchronous detection signal When the phase difference between the reference signal CK2 and the divided clock becomes less than the release level, the phase comparison result determination circuit 152 stops the output of the asynchronous detection signal and the switch control circuit 153 stops the input of the asynchronous detection signal. Thus, the switch 154 is short-circuited and the reference signal CK2 is supplied to the phase-locked loop, and the timing of starting the synchronization operation with the new reference signal can be controlled.

[0005]

In this conventional example, the input of the first reference signal (CK1) is cut off for a certain period (a time corresponding to three to five clocks of the first reference signal CK1). The second reference signal (CK
It is a circuit for switching to 2), and the first reference signal CK
Since the number of clocks to be erased by 1 is not limited, there is a problem that the output phase fluctuation cannot be made smaller.

Further, in this conventional example, since switching is not performed due to fluctuations in the number of clocks of the reference signal, the system follows up even if the number of clocks fluctuates within a preset fixed period. However, there is a problem that malfunctions are likely to occur in the entire system.

Further, in this conventional example, the first reference signal (CK1) detects an input disconnection state for a certain period or more,
Switching to the next second reference signal (CK2)
Since there is no means for detecting the output state of the reference signal (CK1) for a certain period or longer, there is a problem that the malfunction of the entire system is likely to occur in this case as well.

[0008]

The clock synchronization circuit of the present invention comprises a first periodic signal of the output signal of the first frequency dividing circuit and a second periodic signal of the output signal of the second frequency dividing circuit. comparing the phase difference, the the phase-locked loop circuit the phase difference is output as a voltage (PLL), the output the second by varying the duration of one cycle by the voltage of the phase difference from the PLL Voltage controlled oscillator (V
CXO) and a clock synchronization circuit
A clock switching means for outputting switching a plurality of input clock signal serving as a basis for generation of the first periodic signal by a number of click in a predetermined order to said first frequency dividing circuit,
The input clock signal selected by this clock switching means.
Counting the number of clocks in the second periodic signal No.
Counting means and counting result by this counting means
A count storage means for storing the number, a setting means for setting a variation value of the number of clocks in one predetermined cycle ,
The first count output number from the counting means and the count
The difference from the second count output number from the storage means is
If it becomes larger than the dynamic value, to the clock switching means
Sends an alarm signal and switches to the next input clock signal.
And a clock number comparison means for instructing replacement,
Each of the frequency divider circuit and the second frequency divider circuit
The first period signal and the second period which are output signals
Setting each period of the signal by the setting means
And the count storage means is configured to store the second frequency division
The cow delayed by one cycle in the clock cycle divided by the road
Input clock signal from the input means.
By the way, the clock number comparing means is
Said first count output number and said count storage means
From one cycle before the first count output number from
We detect differences by comparing the second count output number.

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a clock synchronization circuit according to an embodiment of the present invention.

In FIG. 1, the clock synchronization circuit 1 of the present embodiment has an external input clock signal number of 3 as an example.
When selecting a clock from the input clock signal A11, the input clock signal B12, and the input clock signal C13 in a predetermined order and monitoring the clock signal input interruption, the currently selected clock signal becomes input interruption. A clock signal switching unit 14 that switches to the next selection candidate clock signal and selects the input clock signal A11, the input clock signal B12, and the input clock signal C13 in that order, and divides the clock from the clock switching unit 14 to perform phase synchronization. A frequency dividing circuit A16 input to the loop circuit (PLL) 17,
The clock signal of the voltage controlled oscillator (VCXO) 18 is frequency-divided and output to the PLL 17, and the clock number counting unit 19 and a frequency dividing circuit B16 that branches and outputs the same signal to the count result storage unit 23, and a frequency dividing unit. PLL17 that compares the clock signal divided by the circuit A15 and the clock signal divided by the divider circuit B16 and outputs the phase difference as a voltage to the voltage controlled oscillator (VCXO) 18;
A voltage-controlled oscillator (VC) which controls the output clock frequency by the control voltage from 7 and outputs the output clock signal 24.
XO) 18 and the number of clocks output from the clock switching unit 14 in the cycle of the frequency dividing circuit B16, and the number of clocks branched and output to the count result storage unit 23 and the clock number comparison unit 21. A count unit 19, a count result storage unit 23 that outputs the result from the clock number counting unit 19 to the clock number comparing unit 21 after delaying the result by one cycle with the clock period divided by the frequency dividing circuit B16, and a clock number counting unit. The output from 19 and the result from the count result storage unit 23, which is the number of clocks one cycle before, are compared, and when the difference is larger than the value set by the setting unit 22,
The clock switching unit 14 includes a clock number comparing unit 21 for sending an alarm signal to the clock switching unit 14, and a setting unit 22 for setting a variation value of the number of clocks allowed in the system in advance.

FIG. 2 is a waveform diagram for explaining an input clock signal switching operation in the clock synchronization circuit of the present embodiment.

Next, the switching operation of the input clock signal in the clock synchronization circuit of this embodiment will be described with reference to FIG.
This will be described with reference to FIG.

In FIG. 1, it is assumed that the voltage controlled oscillator 18 is synchronized with the clock of the input clock signal A11 whose frequency selected by the clock switching unit 14 is stable.

The frequency of the frequency dividing circuit A15 obtained by dividing the frequency of the input clock signal A11 is constant, and the frequency dividing result of the frequency dividing circuit A15 and the frequency dividing result of the frequency dividing circuit B16 are in synchronization with each other. Since the cycle of the frequency dividing circuit A15 that divides the clock is the same as the cycle of the frequency dividing circuit B16, the clock output from the clock switching unit 14 in one cycle of the frequency dividing circuit B16, that is, the input clock. The number of clocks in one cycle of the signal A11 becomes constant.

At this time, it is assumed that the setting section 22 has set "3". Here, considering the case where the output clock of the clock switching unit 14 changes as shown in FIG. 2, there are n clocks in the cycle of the frequency divider B16, and n-4 clocks in the next cycle. When it changes, the output result of the clock number counting unit 19 changes to n−4, and the output of the count result storage unit 23 outputs the number one cycle before the clock period divided by the frequency dividing circuit B16. So n
The clock count comparison unit 21 detects a difference of “4”.

The clock number comparison unit 21 is a fluctuation value setting unit 2
Since the difference is larger than "3" set from 2,
An alarm is output to the clock switching unit 14. The clock switching unit 14 detects the change from the normal state from the clock number comparing unit 21 to the alarm state, excludes the currently selected clock from the selection targets, and switches to the next selection candidate clock, that is, the input clock signal B12. Clock switching unit 14
Does not detect the change from the alarm state to the normal state, the input clock signal C13, which is the next selection candidate from the input clock signal B12, is output even when the alarm continues to be output after switching to the input clock signal B12. The alarm is released when it is synchronized with the input clock signal B12 without being switched to.

As described above, in the present embodiment, when the number of clocks in one cycle of the input clock signal fluctuates more than the fluctuation value preset by the setting unit 22, the next clock signal ordered in advance. Automatically switches to
An output clock signal with a stable cycle can always be obtained.

In the above description, the case where the number of clocks in one cycle of the input clock signal A11 fluctuates less than "3" set by the setting section 22 is explained. Even when there is a large fluctuation, the same operation as described above is performed and the input clock signal A11 is switched to the input clock signal B12.

The detailed operation after switching is the same as in the above case and will not be repeated.

FIG. 3 is a block diagram of a clock synchronization circuit according to the second embodiment of the present invention.

In FIG. 3, the clock synchronization circuit 1a of the second embodiment is different from the clock synchronization circuit 1 of the first embodiment shown in FIG.
And the period of the periodic signal which is each output signal of the frequency dividing circuit 16a is set by the setting unit 22a.
The other requirements are the same as those of the clock synchronization circuit 1 of the first embodiment, and the operations are also the same, so description thereof will be omitted.

[0024]

As described above, the present invention compares the phase difference between the first cycle of the output signal of the first frequency divider circuit and the second cycle of the output signal of the second frequency divider circuit. Output phase-locked loop circuit (hereinafter PL
L) and a voltage controlled oscillator (hereinafter referred to as VCXO) that varies the period of one cycle by the voltage of the phase difference from the PLL and outputs the output to the second frequency dividing circuit, A clock switching means for switching a plurality of input clock signals, which is the basis of generation of the first cycle, and outputting the first clock to the first frequency dividing circuit according to the number of clocks; and a second output signal of the second frequency dividing circuit. Input clock signal to clock switching means when the number of synchronizing input clock signals and the number of input clock signals in the next cycle of the input clock signal fluctuate more than a predetermined fluctuation value in one cycle. This effect is obtained by including a switching alarm signal output means for outputting an alarm signal instructing to switch from the input clock signal to another input clock signal.

That is, since the input clock signal is switched when the number of input clocks fluctuates more than a predetermined fluctuating value, the output phase fluctuation can be suppressed to a smaller extent than in the prior art. Also has the effect of making it possible to prevent malfunction of the entire system from occurring.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining an input clock signal switching operation in the present embodiment.

FIG. 3 is a block diagram showing a clock synchronization circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional clock synchronization circuit.

[Explanation of symbols]

1,1a Clock synchronization circuit 11 Input clock signal A 12 Input clock signal B 13 Input clock signal C 14 Clock switching section 15,15a Frequency divider A 16, 16a frequency divider B 17 Phase locked loop circuit (PLL) 18 Voltage controlled oscillator (VCXO) 19 clock count section 21 Clock number comparison unit 22,22a setting section 23 Count result storage 24 Output clock signal

Claims (3)

(57) [Claims] 1. A phase difference between a first periodic signal of the output signal of the first frequency divider circuit and a second periodic signal of the output signal of the second frequency divider circuit is compared, and the phase difference is taken as a voltage. A phase-locked loop circuit (PLL) for outputting and a voltage-controlled oscillator (VCXO) for varying the period of one cycle by the voltage of the phase difference from the PLL and outputting the output to the second frequency dividing circuit. a clock synchronization circuit comprising bets, output switches in a predetermined order a plurality of input clock signal serving as a basis for generation of the first periodic signal by the number of clocks to the first frequency dividing circuit Clock switching means, counting means for counting the number of clocks in the second periodic signal of the input clock signal switched and selected by the clock switching means, and a count result by the counting means is stored. A count storage means, setting means for setting the number of variation of the clocks in one period predetermined second count output from the first count output count and said counting storage means from said counting means And a clock number comparing means for sending an alarm signal to the clock switching means and instructing switching to the next input clock signal when the difference from the number becomes larger than the fluctuation value. Clock synchronization circuit. 2. Each of the first frequency dividing circuit and the second frequency dividing circuit sets the period of each of the first periodic signal and the second periodic signal, which is an output signal thereof, by the setting means. The clock synchronization circuit according to claim 1 , wherein the clock synchronization circuit can be set by 3. The count storage means stores the number of clocks of the input clock signal from the counting means delayed by one cycle from the clock frequency divided by the second frequency dividing circuit, and the clock number comparison is performed. The means detects the difference by comparing the first count output number from the count means and the second count output number one cycle before the first count output number from the count storage means. The clock synchronization circuit according to claim 1, wherein: