JP2004015659A - Pll controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of a phase difference of at most one clock period to a reference clock signal supplied to a PLL circuit during a switching operation due to the loss of a selected input clock signal. <P>SOLUTION: When either of the input clock signals of two systems received by clock reception units 1, 2 is selected and supplied to the PLL circuit 8, if the fault of the selected clock signal is detected, the selection is switched to the other input clock signal, and a pulse signal is inserted during the switching operation so as to adjust a phase. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a PLL (Phase Locked Loop) control device for controlling a PLL circuit.
[0002]
[Prior art]
In general, two systems of input clocks supplied to a PLL circuit of a device such as a transmission device are prepared in order to ensure reliability, and when one input clock is lost, it is switched to the other input clock to operate. Thus, it is designed such that normal operation can be continued.
[0003]
FIG. 6 is a block diagram showing the configuration of a conventional PLL control device. In the figure, reference numerals 11 and 12 denote clock receiving units, 13 and 14 denote input abnormality detecting units, 15 denotes an input clock selecting unit, and 16 denotes an input clock selecting unit. The control unit 17 is a PLL circuit.
[0004]
Next, the operation will be described.
The clock receiving unit 11 receives an input clock signal CLKA from outside. The clock receiving unit 12 receives an input clock signal CLKB from outside. The input abnormality detection unit 13 detects an abnormality (such as disappearance) of the input clock signal CLKA input to the clock reception unit 11 and provides an input abnormality detection signal to the input clock selection control unit 16. The input abnormality detection unit 14 detects an abnormality of the input clock signal CLKB input to the clock reception unit 12, and provides an input abnormality detection signal to the input clock selection control unit 16. The input clock selection unit 15 selects one of the two input clock signals CLKA or CLKB output from the clock reception unit 11 or 12 in response to a selection signal from the input clock selection control unit 16, and The selected clock signal SELCLK is supplied to the PLL circuit 17 as a reference clock signal.
[0005]
Now, the input clock selection unit 15 selects the input clock signal CLKA according to a selection signal (for example, a high-level selection signal) from the input clock selection control unit 16 and supplies the selected clock signal SELCLK to the PLL circuit 17. Suppose you are. In this state, when the pulse of the input clock signal CLKA has disappeared, the input abnormality detection unit 13 supplies an input abnormality detection signal to the input clock selection control unit 16. As a result, the input clock selection control section 16 supplies a low-level selection signal to the input clock selection section 15. Therefore, the input clock selector 15 selects the input clock signal CLKB output from the clock receiver 12, and supplies the selected clock signal SELCLK to the PLL circuit 17 as a reference clock signal. The PLL circuit 17 sends out an output clock signal OUTCLK synchronized with the reference clock signal to the outside.
[0006]
As described above, the two input clock signals are received, one of the input clock signals is selected and supplied to the PLL circuit as the reference clock signal, and an abnormality such as disappearance occurs in the selected input clock signal. In this case, the normal operation of the PLL circuit 17 can be continued by switching to the other input clock signal.
[0007]
[Problems to be solved by the invention]
Since the conventional PLL control device is configured as described above, the switching is performed after detecting the disappearance of the selected input clock signal. Therefore, a phase difference occurs up to one clock cycle, and the PLL circuit is unnecessary. As a result of performing the synchronous operation, there is a problem that the output fluctuation of the PLL circuit becomes large. For example, in FIG. 7, when the pulse p1 of the selected input clock signal CLKA has disappeared, the input clock signal CLKB is selected at the time of occurrence of switching, and the selected clock signal SELCLK is supplied to the PLL circuit 17 as a reference clock signal. In this case, a phase difference of up to one clock cycle occurs during the switching period.
Further, if the abnormality detection of the input clock signal being selected is delayed, a phase difference of two clock cycles or more occurs.
[0008]
Further, since the conventional PLL control device is configured as described above, even when an abnormal pulse is received in one of the two input clock signals, the switching operation is performed after the abnormal pulse is received. There is also a problem that the circuit 17 is affected by an abnormal pulse. For example, in FIG. 8, when an abnormal pulse n1 occurs in the selected input clock signal CLKA, the input clock signal CLKB is selected at the time of switching, and the selected clock signal SELCLK is supplied to the PLL circuit 17 as a reference clock signal. In this case, the abnormal pulse n1 remains in the selected clock signal SELCLK.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has a phase difference of up to one clock cycle between a reference clock signal supplied to a PLL circuit during a switching period when a selected input clock signal disappears. It is an object of the present invention to obtain a PLL control device that prevents the occurrence of an error.
Another object of the present invention is to provide a PLL control device that detects an abnormality of an input clock signal at a high speed.
It is another object of the present invention to provide a PLL control device that prevents a PLL circuit from being affected by an abnormal pulse even when an abnormal pulse occurs in a selected input clock signal.
[0010]
[Means for Solving the Problems]
A PLL control device according to the present invention includes a signal receiving unit that receives two input clock signals input from the outside, and selects one of the two input clock signals and supplies the input clock signal to a PLL circuit. Signal selection means for transmitting a reference clock signal for phase synchronization, abnormality detection means for detecting an abnormality of an input clock signal and generating an abnormality detection signal and a pulse insertion request signal, and one input according to the abnormality detection signal. Selection control means for transmitting a selection signal for switching the clock signal to the other input clock signal to the signal selection means, and a reference clock signal which is not obtained during the switching period of the input clock signal by the signal selection means in response to the pulse insertion request signal And a phase adjusting means for adjusting the phase by inserting a pulse signal.
[0011]
The PLL control device according to the present invention is configured to include a signal generation unit that generates a high-speed clock signal for detecting an abnormality of an input clock signal and supplies the high-speed clock signal to an abnormality detection unit.
[0012]
The abnormality detection means of the PLL control device according to the present invention is configured to detect an abnormality of an input clock signal according to a high-speed clock signal obtained from a PLL circuit.
[0013]
The abnormality detecting means of the PLL control device according to the present invention is configured such that an input cutoff signal for cutting off an input for a predetermined period within one cycle is provided to the signal receiving means in accordance with the cycle of the input clock signal.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a configuration of an embodiment of the present invention will be described with reference to the drawings. Embodiment 1 FIG.
FIG. 1 is a block diagram illustrating a configuration of a PLL control device according to a first embodiment. In the figure, reference numerals 1 and 2 denote a clock receiving unit (signal receiving unit), and reference numerals 3 and 4 denote input abnormality detecting units (abnormality detecting unit). 5 is an input clock selection unit (signal selection unit), 6 is an input clock selection control unit (selection control unit), 7 is a clock frequency adjustment unit (phase adjustment unit), 8 is a PLL circuit, 9 is a monitoring unit, and 10 is a monitoring unit. It is a high-speed clock generation unit (signal generation means).
[0015]
Next, the operation will be described.
The clock receiving unit 1 receives an input clock signal CLKA from outside. The clock receiving unit 2 receives an input clock signal CLKB from outside. The input abnormality detection unit 3 detects an abnormality (such as disappearance) of the input clock signal CLKA input to the clock reception unit 1, supplies an input abnormality detection signal to the input clock selection control unit 6 and the monitoring unit 9, and inserts a pulse. The request signal PREQA is supplied to the clock frequency adjusting unit 7. The input abnormality detection unit 4 detects an abnormality of the input clock signal CLKB input to the clock reception unit 2 and provides an input abnormality detection signal to the input clock selection control unit 6 and the monitoring unit 9, and outputs a pulse insertion request signal PREQB. It is given to the clock frequency adjusting unit 7. The input clock selection unit 5 selects one of the two input clock signals CLKA or CLKB output from the clock reception unit 1 or 2 in response to a selection signal from the input clock selection control unit 6, and The selected clock signal SELCLK is supplied to the PLL circuit 8 as a reference clock signal. The PLL circuit 8 sends out an output clock signal OUTCLK synchronized with the reference clock signal to the outside. The monitoring unit 9 notifies the user of the abnormal state by display or voice or via communication means in response to the abnormality detection signal from the input abnormality detection unit 3 or 4. The high-speed clock generation unit 10 supplies the generated high-speed clock signal to the input abnormality detection units 3 and 4 to speed up the abnormality detection of the input clock signals CLKA and CLKB.
[0016]
Now, the input clock selection unit 5 selects the input clock signal CLKA in response to a selection signal (for example, a high-level selection signal) from the input clock selection control unit 6 and changes the selected clock signal SELCLK to the clock frequency adjustment unit 7. And supply it to When the pulse insertion request signal PREQA is not supplied from the input abnormality detection unit 3, the clock frequency adjustment unit 7 supplies the selected clock signal SELCLK to the PLL circuit 8 as a reference clock signal.
[0017]
In this state, as shown in FIG. 2, when the pulse p1 of the input clock signal CLKA has disappeared, the input abnormality detection unit 3 sets the input clock signal CLKA in accordance with the high-speed clock signal given from the high-speed clock generation unit 10. Is detected at a high speed, an input abnormality detection signal is supplied to the input clock selection control unit 6, and a pulse insertion request signal PREQA indicated by r1 in the figure is supplied to the clock frequency adjustment unit 7. As a result, the input clock selection controller 6 supplies a low-level selection signal to the input clock selector 5. Therefore, the input clock selection unit 5 selects the input clock signal CLKB output from the clock reception unit 2 at the switching timing t. In addition, the clock frequency adjusting unit 7 inserts the pulse signal p2 into the selected clock signal SELCLK output from the input clock selecting unit 5 in response to the pulse insertion request signal PREQA at the switching timing t, and uses the PLL as the reference clock signal PLLCLK. Supply to circuit 8. Also, when a phase difference of two or more clocks occurs, monitoring is performed every period, and if a pulse has disappeared, normal operation can be continued by inserting a pulse each time.
[0018]
As described above, according to the first embodiment, when one of the two input clock signals is selected and supplied to the PLL circuit 8 as the reference clock signal, the selected input clock When a signal abnormality is detected, one input clock signal is switched to the other input clock signal, and the phase is adjusted by inserting a pulse signal instead of the reference clock signal that cannot be obtained during the switching period. In the switching period when the input clock signal is lost, it is possible to prevent the reference clock signal supplied to the PLL circuit 8 from generating a phase difference of up to one clock cycle.
[0019]
Further, according to the first embodiment, since the high-speed clock generator 10 for generating the high-speed clock signal for performing the abnormality detection of the input clock signal and providing the high-speed clock signal to the input abnormality detectors 3 and 4 is provided, the input clock signal The effect of being able to detect abnormalities at high speed is obtained.
[0020]
According to the first embodiment, the monitoring unit 9 notifies the user of the abnormal state according to the abnormality detection signal from the input abnormality detecting unit 3 or 4, so that the abnormal state of the input clock signal can be easily recognized. The effect is obtained.
[0021]
Embodiment 2 FIG.
FIG. 3 is a block diagram illustrating a configuration of a PLL control device according to the second embodiment. In the figure, the same components as those in the first embodiment are denoted by the same reference numerals. The configuration of the second embodiment is different from the configuration of the first embodiment, as shown in FIG. 3, in which the abnormal pulse mask signals MASKA, MASKA, MASKB is given.
[0022]
Next, the operation will be described.
The input abnormality detection units 3 and 4 specify an allowable range and an abnormal phase range of the input clock signals CLKA and CLKB according to the cycles of the input clock signals CLKA and CLKB, respectively. For example, assuming that the input clock signal CLKA is currently selected, the input abnormality detection unit 3 specifies an allowable range and an abnormal phase range of the input clock signal CLKA as shown in FIG. Then, an abnormal pulse mask signal MASKA having an allowable range of a low level and an abnormal phase range of a high level is supplied to the clock receiving unit 1. The clock receiving unit 1 cuts off the input clock signal CLKA and does not supply it to the input clock selection unit 5 during the period when the abnormal pulse mask signal MASKA is at the high level.
[0023]
Therefore, as shown in FIG. 4, even when the abnormal pulse n1 occurs in the abnormal phase range of the input clock signal CLKA, the input clock signal CLKA ′ supplied from the clock receiving unit 1 to the input clock selecting unit 5 is cut off. Since the abnormal pulse n1 is not included, the abnormal pulse n1 does not appear in the selected clock signal SELCLK output from the input clock selecting unit 5. When detecting the abnormal pulse n1, the input abnormality detection unit 3 supplies an abnormality detection signal to the input clock selection control unit 6, so that after the switching timing t, the normal input clock signal CLKB is output from the clock reception unit 2 to the input clock selection unit. 5.
[0024]
As described above, according to the second embodiment, input abnormality detecting units 3 and 4 interrupt the input during a predetermined period within one cycle in accordance with the cycle of input clock signals CLKA and CLKB. Since the signals MASKA and MASKB (input cutoff signals) are supplied to the clock receiving units 1 and 2, even if an abnormal pulse occurs in the selected input clock signal, the PLL circuit 8 is prevented from being affected by the abnormal pulse. The effect that can be obtained is obtained.
[0025]
Although not shown in FIG. 4, in the second embodiment, a pulse signal is inserted in place of the reference clock signal which cannot be obtained during the switching period of the input clock signal, similarly to the first embodiment. The phase of the reference clock signal supplied to the PLL circuit 8 during the switching period when the selected input clock signal disappears, thereby preventing a phase difference of up to one clock cycle from occurring. Is obtained.
[0026]
Further, also in the second embodiment, similarly to the first embodiment, a high-speed clock generator for generating a high-speed clock signal for detecting an abnormality of an input clock signal and supplying the high-speed clock signal to input abnormality detectors 3 and 4. Because of the provision of 10, the effect that the abnormality of the input clock signal can be detected at high speed can be obtained.
[0027]
Embodiment 3 FIG.
FIG. 5 is a block diagram showing the configuration of the PLL control device according to the third embodiment. In the figure, the same components as those of the first embodiment are denoted by the same reference numerals. In the third embodiment, unlike the first and second embodiments, a high-speed clock generator is not provided. As shown in the figure, the high-speed clock signal generated by the PLL circuit 8 is given to the input abnormality detection units 3 and 4. That is, the PLL circuit 8 of FIG. 5 has a configuration in which the frequency of the internal oscillator is sufficiently higher than the frequencies of the input clock signals CLKA and CLKB.
[0028]
Next, the operation will be described.
In the third embodiment, a high-speed pulse signal generated in the phase synchronization process of the PLL circuit 8 is supplied to the input abnormality detection units 3 and 4, and the abnormality of the input clock signals CLKA and CLKB is detected at high speed. Therefore, the high-speed clock generator can be omitted.
[0029]
As described above, according to the third embodiment, the abnormality of the input clock signal is detected according to the high-speed clock signal obtained from the PLL circuit 8, so that the abnormality of the input clock signal can be obtained without providing the high-speed clock generation unit. Can be detected at high speed.
[0030]
In the third embodiment, as in the first embodiment, when either one of the two input clock signals is selected and supplied to the PLL circuit 8 as a reference clock signal. When an abnormality of the selected input clock signal is detected, one input clock signal is switched to the other input clock signal, and a pulse signal is inserted in place of the reference clock signal that cannot be obtained during the switching period to change the phase. Since the adjustment is performed, an effect is obtained that a phase difference of up to one clock cycle can be prevented from occurring in the reference clock signal supplied to the PLL circuit 8 during the switching period when the selected input clock signal disappears.
[0031]
Further, also in the third embodiment, similarly to the second embodiment, input abnormality detection units 3 and 4 operate according to the cycles of input clock signals CLKA and CLKB in a predetermined period within one cycle. Since abnormal pulse mask signals MASKA and MASKB (input cutoff signals) for interrupting the input are supplied to the clock receiving units 1 and 2, even if an abnormal pulse occurs in the selected input clock signal, the PLL circuit 8 causes the abnormal pulse to occur. The effect of being able to prevent from being affected by is obtained.
[0032]
【The invention's effect】
As described above, according to the present invention, the PLL control device is provided with a signal receiving means for receiving two input clock signals input from the outside and a signal receiving means for receiving one of the two input clock signals. Signal selection means for transmitting a reference clock signal for phase synchronization to be selected and supplied to a PLL circuit; abnormality detection means for detecting an abnormality of an input clock signal to generate an abnormality detection signal and a pulse insertion request signal; Selection control means for transmitting a selection signal for switching one input clock signal to the other input clock signal in response to the signal to the signal selection means, and a switching period of the input clock signal by the signal selection means in response to the pulse insertion request signal Phase adjustment means for adjusting the phase by inserting a pulse signal instead of a reference clock signal that cannot be obtained The switching period when the input clock signal is lost, the phase difference of up to one clock period to the reference clock signal supplied to the PLL circuit 8 is an effect of being able to prevent the occurrence.
[0033]
According to the present invention, the PLL control device is configured to include the signal generation unit that generates the high-speed clock signal for detecting the abnormality of the input clock signal and provides the high-speed clock signal to the abnormality detection unit. There is an effect that detection can be performed at high speed.
[0034]
According to the present invention, the abnormality detection means of the PLL control device is configured to detect the abnormality of the input clock signal according to the high-speed clock signal obtained from the PLL circuit. Therefore, the signal generation means for generating the high-speed clock signal is provided. Without this, there is an effect that abnormalities in the input clock signal can be detected at a high speed.
[0035]
According to the present invention, the abnormality detecting means of the PLL control device is configured to supply the signal receiving means with the input cutoff signal for cutting off the input during a predetermined period within one cycle in accordance with the cycle of the input clock signal. Even if an abnormal pulse occurs in the middle input clock signal, there is an effect that the PLL circuit can be prevented from being affected by the abnormal pulse.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a PLL control device according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart showing a switching operation of an input clock signal according to the first embodiment of the present invention;
FIG. 3 is a block diagram showing a configuration of a PLL control device according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing a switching operation of an input clock signal according to a second embodiment of the present invention;
FIG. 5 is a block diagram showing a configuration of a PLL control device according to a third embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration of a conventional PLL control device.
FIG. 7 is a timing chart showing a switching operation of an input clock signal in a conventional PLL control device.
FIG. 8 is a timing chart showing a switching operation when an abnormal pulse occurs in an input clock signal in a conventional PLL control device.
[Explanation of symbols]
1, 2 clock receiving section (signal receiving section), 3, 4 input abnormal detecting section (abnormal detecting section), 5 input clock selecting section (signal selecting section), 6 input clock selecting control section (selecting controlling section), 7 clocks Frequency adjustment unit (phase adjustment unit), 8 PLL circuit, 9 monitoring unit, 10 high-speed clock generation unit (signal generation unit), 11, 12 clock reception units, 13, 14 input abnormality detection unit, 15 input clock selection unit, 16 Input clock selection controller, 17 PLL circuit.

Claims (4)

Signal receiving means for receiving two input clock signals input from outside;
Signal selection means for selecting one of the two input clock signals and transmitting a reference clock signal for phase synchronization to be supplied to the PLL circuit;
Abnormality detection means for detecting an abnormality of the input clock signal and generating an abnormality detection signal and a pulse insertion request signal,
Selection control means for sending a selection signal for switching the one input clock signal to the other input clock signal in response to the abnormality detection signal to the signal selection means,
A PLL control device comprising: a phase adjusting unit that adjusts a phase by inserting a pulse signal instead of a reference clock signal that cannot be obtained during a switching period of an input clock signal by the signal selecting unit in response to the pulse insertion request signal. 2. The PLL control device according to claim 1, further comprising signal generation means for generating a high-speed clock signal for detecting an abnormality of the input clock signal and supplying the high-speed clock signal to the abnormality detection means. 2. The PLL control device according to claim 1, wherein the abnormality detecting means detects an abnormality of the input clock signal according to a high-speed clock signal obtained from the PLL circuit. 4. The abnormality detecting unit according to claim 1, wherein the abnormality detecting unit supplies the signal receiving unit with an input cutoff signal for cutting off an input during a predetermined period in one cycle of the input clock signal. The PLL control device according to claim 1.

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