JPS63136855A - Frame buffer memory device - Google Patents

Abstract

PURPOSE:To attain a high speed processing with an extremely simple constitution and with low cost by detecting the leading end of frame data through the use of a FIFO (First-In.First-Out) memory, and detaching a frame generation circuit which is used at the time of starting. CONSTITUTION:If a reception circuit 1 receives a packet, it outputs a signal informing a write control part 3 of the reception. In answer to this, the write control part 3 generates to the FIFO memory 2 a control signal for writing the received packet of the reception circuit 1 into the FIFO 2 and it executes writing. If the FIFO memory 2 is full, a read/transmission control part 5 reads the packet from the FIFO memory 2 and temporarily stores it in a transmission circuit 4. The read/transmission control part 5 checks whether data in the transmission circuit 4 is the leading end of the frame or not. If it is, said part changes over a transmission selection switch 6 from the side of a frame generation circuit 61 to the side of the transmission circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention solves the problems of frame reception processing and high-speed processing and an increase in the scale of logic circuits when starting up a high-speed LAN. -F
The present invention provides a frame buffer memory device that detects the beginning of frame data using an irst-Out memory and disconnects it from a frame generation circuit used at startup.

[Industrial application field]

The present invention relates to a frame buffer memory device, and more particularly to high-speed LAN (local area network) activation control of a frame buffer memory device used in a monitoring node.

Figure 3 shows the overall system configuration of the LAN.
A plurality of general nodes IN and one monitoring node Sv are configured in a loop with an optical cable transmission path.

The general node IN has a function of transmitting and receiving data from an accommodating terminal (not shown), synchronizing with the monitoring node SN using a clock signal extracted from transmission path data, and transmitting and receiving packets.

As shown in FIG. 4, the monitoring node SN extracts a reception clock signal from the data on the transmission path, and extracts the reception data in the reception circuit 54 using a timing signal from a timing generation circuit 53 for timing within the loop. After that, it is input to the frame buffer memory device FBM.

The transmission data from the frame buffer memory device ifFBM is transmitted to the general node IN from the repeater 56 based on the transmission clock signal from the oscillator 55 via the code converter 52.
sent to.

In this manner, the monitoring node SN performs state management and failure management of the transmission path, general nodes, etc. by performing writing and reading in the frame buffer memory device FBM and performing frame control.

In a high-speed LAN, it is necessary to perform frame control at high speed in the frame buffer memory device.

[Conventional technology]

A schematic diagram of a conventionally known frame buffer memory device is shown in FIG. :(7) 71/- The buffer memory device FBM schematically includes a frame generation circuit 61, a control circuit 62, and a transmission selection switch 63, as shown in the figure.
, and a memory circuit 64, and as a result, ■
Performs frame transmission control, ■write control, ■readout control, and ■flag control.

These control processes will be schematically explained with reference to the specific circuit shown in FIG.

■Frame transmission control: At the time of initialization to start up the LAN, the frame counter section 71 and frame generation section 72 are operated by the transmission clock signal supplied from the oscillator 55 (FIG. 4) in the monitoring node SN, and the selector 74 and FF (flip flop)7
5, frames are continuously transmitted to the transmission path. At this time, the transmission control unit 73 selects the selector 74 from the frame generation circuit 6.
Switching to side 1.

■Write control: Timing generation circuit 53 of monitoring node SN (Fig. 4)
After being notified that the transmission path has been synchronized, the write control unit 77 and write counter 78 write the received data to FF79 and FF80 to 83 in synchronization with the reception clock supplied from the code conversion unit 52 of the monitoring node SN. serial-to-parallel conversion is performed and the address selector 88 is set to RA.
Switching is made to the writing side of the M memories 84-87, and writing to the RAM memos 84-87 is performed.

■Reading control: After writing to the RAM memories 84 to 87 is started,
The RAM memory 8
Start reading numbers 4 to 87. After the data is moved to each of the registers 91 to 94 on the reading side, reading is interrupted.

Thereafter, when the data in each register 91 to 94 is sent to the transmission path by data transmission on the RAM memory side, reading from the RAM memory is started.

■Flag system? IIl: The flag control unit 76 converts the parallel data stored in the read-side registers 91 to 94 of the RAM memories 84 to 87 into
Registers 95 to 98 provided for each RAM memory are used to adjust the timing of data reception and transfer between the transmission clock signal and the reception clock signal.

The data in registers 95 to 98 is transmitted to the transmission control unit 73.
FF10 in turn via internal selector 99 under the control of
At this time, the data of FF100 is sent to the transmission control unit 73, and the transmission control unit 73 determines that the beginning of the frame has arrived and switches the selector 74 to the FF100 side.
Executes data transmission.

[Problem that the invention seeks to solve]

Such a conventional frame buffer memory device has a plurality of RAM memories, a plurality of registers and write/read counters for synchronizing access (writing, reading) of these RAM memories, and has a plurality of RAM memories. In order to access the read timing using the same clock signal, an 'aN1 processing mechanism is required.
This led to higher costs.

Furthermore, since a RAM is used as the memory circuit and the structure for read control and flag control is composed of complicated logic circuits, access delays are caused, which poses a problem in use as a high-speed LAN.

Therefore, an object of the present invention is to realize a frame buffer memory device in a monitoring node that has a simple structure and has a high processing speed that can be used for starting a high-speed LAN.

[Means for solving problems]

FIG. 1 shows a conceptual diagram of a frame buffer memory device according to the present invention to achieve the above object, where l is a receiving circuit that receives data, and 2 is a FIFO that writes received data from the receiving circuit 1. 3 is a write control unit that controls writing from the receiving circuit 1 to the FIFO memory 2; 4 is a transmitting circuit that sequentially stores and transmits data in the FIFO memory 2; and 5 is a transmitting circuit when the FIFO memory 2 is full. A readout/transmission control unit performs readout control to 4 and generates a selection signal only when detecting the beginning of a frame from the data of the transmission circuit 4, and 6 is a transmission unit that switches from the frame generation circuit 61 to the transmission circuit 4 based on the selection signal. It is a selection switch.

[For production]

In FIG. 1, when receiving circuit 1 receives a packet,
The receiving circuit 1 outputs a signal notifying the write control unit 3 of the reception fε. In response to this, the write control section 3 generates a control signal to the FIFO memory 2 to write the received packet of the receiving circuit 1 to the FIFO memory 2, and writes the received packet to the FIFO memory 2.

When the FIFO memory 2 becomes full, in response to this, the readout/transmission control unit 5 reads the packet from the FIFO memory 2 and temporarily stores it in the transmission circuit 4. The read/transmission control unit 5 checks whether the data in the transmission circuit 4 is at the beginning of the frame, and if so, switches the transmission selection switch 7 from the frame generation circuit 6 side to the transmission circuit 4 side.

After this, normal LAN will be used without frame generation.
Continue operation.

〔Example〕

Embodiments of the frame buffer memory device according to the present invention will be described below.

FIG. 2 shows an embodiment of the frame buffer memory device of the present invention conceptually shown in FIG. 1. In FIG. 2, the transmitting circuit 4 includes FFs 21 and 22, 5 includes a read control circuit 31 and a transmission control circuit 32, reading from the FIFO memory 2 to the FF21 is performed under the control of the read control circuit 31, and the FF2
Data transfer from FF 1 to FF 22 is performed under the control of transmission control circuit 32.

In this embodiment, FFs 41 and 42 are provided to transfer data from the frame generation circuit 61 to the transmission selection switch 6 and to send data from the selection switch 6 to the transmission path, respectively.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, in the initial state when the power is turned on (when the LAN is started), a frame signal is sent from the frame generation section 72 to the FF4 according to the frame length determined by the frame counter section 71.
1 to the transmission selection switch 6. This frame signal is used to confirm whether the LAN network is normal or not. In this initial state, the transmission selection switch 6 is switched to the frame generation circuit 61 side, so the frame signal is transmitted to the transmission selection switch 6 and the FF.
42 and sent out to the transmission path.

The frame signal circulates on the network and returns again as received data (packets).

The received data is individually formed by the FFI as a receiving circuit, and at the same time, a received data detection (flag) signal a is sent to the write control section 3. The write control unit 3 outputs a write pulse b.
is generated to instruct writing from the FFI to the FrFO memory 2. When data is gradually written into the FIFO memory 2 and it becomes full, an available signal C is sent to the readout control circuit 31 of the readout/transmission control unit 5, and the readout pulse d is sent from the readout control unit 31 to the FIFO memory 2.
The data is sent to the memory 2 and sent from the IIFO memory 2 in order to the FF 21 of the transmitting circuit 4 and read control circuit 3.
The data is once stored by the latch signal e from 1, the data is reformed, and then sent to the FF 22. The FF 22 forms data again using the transmission clock and notifies the transmission control circuit 32 of the data f in the FF 22.

The transmission control circuit 32 checks whether the notified data f is the beginning of the frame, and if it is the beginning frame, it sends a switching signal g to the transmission selection switch 6 and switches the switch 6 from the frame generation circuit 61 side to the transmission circuit 4. Switch to the side. If the data f is not the beginning of the frame, the switching signal g is not generated and the switch 6 remains connected to the frame generation circuit 61 side.

In other words, if the LAN network is normal, the first frame should be returned first; otherwise, if any of the received data is returned, or if the first frame is lost, nothing will happen. Since the network failure has occurred, the transmission selection switch 6 is kept in its initial state.

Note that in the above embodiment, the FF 1, the write control section 3,
An asynchronous clock format is used in which the reception clock signal for the FF 21 and the readout control circuit 31 is separated from the transmission clock signal for the FF 22, the transmission control circuit 32, the transmission selection switch 6, the frame generation circuit 61, and the FF 41. The clocks may be the same, in which case only one of the FFs 21 or 22 may be used.

〔Effect of the invention〕

As described above, according to the frame buffer memory device of the present invention, compared to the conventional example in which writing and reading access to the memory circuit using the RAM configuration is performed using complicated flag control etc. at the time of starting the LAN. Since the FIFO memory can be used and its writing and reading can be controlled simultaneously and asynchronously, high-speed processing can be achieved with an extremely simple configuration and low cost.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a frame buffer memory device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the frame buffer memory device shown in FIG. 1, and FIG. 3 is a schematic diagram of a general LAN. FIG. 4 is a block diagram showing a schematic configuration of a monitoring node in a LAN loop. FIG. 5 is a schematic block diagram of a conventional frame buffer memory device used in a monitoring node. 6 is a circuit diagram specifically showing the frame buffer memory device of FIG. 5; FIG. In Figures 1 and 2, 1 is a receiving circuit, 2 is a FIFO memory, 3 is a write control section, 4 is a transmitting circuit, 5 is a search/transmission control circuit, 6 is a transmission selection switch, and 21.22 is a transmission selection switch. 31 is a readout control circuit, 32 is a transmission control circuit, and 61 is a frame generation circuit. In the drawings, the same reference numerals indicate the same or corresponding parts. Patent applicant Fujitsu Co., Ltd. Agent Patent Attorney
Mori 1) Hiroshi (1 other person) Diagram showing an example of this defense Figure 2 Yokote U diagram of the monitoring node Party diagram 4

Claims (3)

[Claims] (1) A receiving circuit (1) that receives data, and a FIFO memory (2) that writes the received data from the receiving circuit (1).
); a write control unit (3) that controls writing from the receiving circuit (1) to the FIFO memory (2); a transmitting circuit (4) that sequentially stores data in the FIFO memory (2); Read/transmit control that controls reading to the transmitting circuit (4) when the FIFO memory (2) is full, and generates a selection signal only when the beginning of a frame is detected from the data of the transmitting circuit (4). A frame buffer memory device comprising: a transmission selection switch (6) that switches from the frame generation circuit (61) to the transmission circuit (4) according to the selection signal. (2) the readout/transmission control section (5) is composed of a readout control circuit (31) and a transmission control circuit (32);
The transmitting circuit (4) includes two flip-flops (21,
22), the read control circuit (31) controls one of the flip-flops (21), and the transmission control circuit (32) controls the other flip-flop (22).
2. A frame buffer memory device according to claim 1, wherein the frame buffer memory device controls: (3) Claim 1 in which the write clock and read clock of the FIFO memory (2) are asynchronous.
Frame buffer memory device as described in .