JP2737361B2 - Data processing device and data processing system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device. For more information,
The present invention relates to a data processing device that is connected to each other using a cable to configure a system, and to reduce a data processing failure in each data processing device caused by jitter included in data.

2. Description of the Related Art In recent years, networking of various data processing systems has advanced, and the frequency of configuring one system by connecting a plurality of data processing devices via a network has been increasing. Accordingly, it is desired to increase the reliability of data transmitted on a network.

Hereinafter, an example of the above-described data processing system will be described with reference to the drawings. FIG. 9 is a block diagram showing an example of a conventional data processing system.

In FIG. 9, reference numerals 901 to 904 denote the first components of the system.
To a fourth data processing device, 905 to 907 are input connectors, 90
Reference numerals 8 to 911 denote output connectors, and reference numerals 912 to 914 denote optical fibers for connecting the respective data processing devices. Each data processing device advances data processing while exchanging data via an optical fiber. For example, the first data processing device 901
The data transmitted from to the third data processing device 903 is
The data is output from the output connector 908 of the first data processing device 901, and is input from the input connector 906 of the third data processing device 903 via the second data processing device 902. The first data processing device 901 generates a clock serving as a reference for transmitted data, and the other data processing devices perform processes such as data latching according to the clock extracted from the input data. Here, a data processing device that generates a clock is referred to as a parent device, and other data processing devices are referred to as child devices.

FIG. 10 and FIG. 11 are block diagrams of a master unit and a slave unit constituting the data processing system of FIG. 9, respectively.

In FIG. 10, 1001 is a data processing means, 1002 is a clock generation means, and 1003 is an output connector. The data processing means 1001 generates output data based on the first clock generated by the clock generation means 1003.

In FIG. 11, 1101 is a data processing means, 1102 is a clock extracting means, 1103 is an input connector, and 1104 is an output connector. The data processing unit 1101 executes all data processing according to the second clock extracted by the clock extraction unit 1102.

However, in the above-described configuration, each data processing device extracts a second clock from input data using a PLL or the like, and outputs data based on the second clock. Therefore, there is a problem in that the jitter included in the data increases as the data sequentially propagates through a plurality of data processing devices, and the error rate deteriorates.

The present invention has been made in consideration of the above problems, and has as its object to provide a configuration that reduces the propagation of jitter between data processing devices and reduces the disturbance of data processing in each data processing device caused by jitter included in data. And

Means for Solving the Problems To achieve the above object, a data processing apparatus according to the present invention (claim 1) comprises an input connector, a data processing means, a clock generation means, a clock extraction means, a clock switching means, , An output connector, an external cable is connected to the input connector, input data is sent to the data processing means and the clock extracting means, the clock generating means generates a first clock, The clock extracting unit extracts a second clock included in data input from the input connector, and the clock switching unit includes:
A third clock is selected from the first clock and the second clock, the data processing device generates output data based on the third clock, and the output connector is connected to the output data. It sends out to an external cable.

Further, the data processing system of the present invention (claim 2)
By using a plurality of the above data processing devices, an input connector of one data processing device and an output connector of another data processing device are sequentially connected by a cable, and data is transmitted through the cable.

Further, a data processing device according to the present invention (claim 3) includes, in addition to the above data processing device, a clock request generating unit, wherein the clock request generating unit sends a clock request command to the data processing device. Is generated.

Further, the data processing system of the present invention (claim 4)
By using a plurality of the above data processing devices, an input connector of one data processing device and an output connector of another data processing device are sequentially connected in a loop by a cable, and data is transmitted through the cable.

According to the above configuration, the data processing device of the present invention (claim 1) determines which of the first clock generated internally and the second clock extracted from the input data is more suitable for the data to be transmitted. The third clock is selected and used as a reference when transmitting data.

Further, the data processing system of the present invention (claim 2)
In the case where a clock does not need to be preserved in data transmission from one data processing device constituting the system to another data processing device, the internally generated first clock is used as a reference for data transmission.

Further, the data processing apparatus according to the present invention (claim 3) generates a command for requesting a transmission destination to transmit a clock used as a reference for data transmission, prior to data transmission.

Further, the data processing system of the present invention (claim 4)
In transmitting data from one data processing device constituting the system to another data processing device, a transmission source data processing device sets a data transmission reference to a transmission destination data processing device before starting data transmission. Requests transmission of a clock, and transmits data based on the clock transmitted from the data processing device of the transmission destination via the loop, and the data processing device of the transmission destination uses the clock generated by itself. To process the data.

Embodiment Hereinafter, a data processing apparatus according to an embodiment (first embodiment) of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a data processing apparatus according to an embodiment of the present invention (claim 1), 101 is a data processing means, 102 is a clock extracting means, 103 is a clock generating means, and 104 is an input. A connector 105 is an output connector, and 106 is a clock switching means.

In FIG. 1, a clock generating means 103 generates a first clock and sends it to a clock switching means 106. Input connector 104
Transmits the input data from the connected cable to the data processing means 101 and the clock extraction means 102. The clock extracting means 102 extracts the second clock from the input data, and sends it to the data processing means 101 and the clock switching means 106.
The clock switching means 106 selects one of the first clock and the second clock according to the instruction from the data processing means 101 and outputs the selected clock as the third clock. The data processing means 101 processes the input data with reference to the second clock, creates output data with reference to the third clock, and sends the output data to the output connector 105. The output connector 105 sends output data to the connected cable.

FIG. 2 is a block diagram of a data processing system according to the present invention (claim 2), wherein 201 to 204 are first to fourth data processing devices constituting the data processing system, 205 to 208 are input connectors, and 209 to 209. Reference numeral 212 denotes an output connector, and reference numerals 213 to 215 denote optical fibers for connecting the respective data processing devices. Each data processing device exchanges data via optical fiber,
Proceed with data processing. For example, data transmitted from the first data processing device 201 to the third data processing device 203 is output from the output connector 209 of the first data processing device 201, and is output via the second data processing device 202. , Third
Is input from the input connector 207 of the data processing device 203.

FIG. 3 is a block diagram showing one configuration example of the clock extracting means 102 in FIG. 1, where 301 is a phase comparator, and 302 is
VCO 303 is a frequency divider.

In FIG. 3, the phase comparator 301 compares the phase of the input data with the phase of the output of the frequency divider 303, and sends the difference to the VCO 302 as an error voltage. The VCO 302 oscillates according to the error voltage. Divider
303 divides the output of the VCO 302 and sends it to the phase comparator 301.
This clock extraction means is well known as PLL,
For example, when the frequency division ratio of the frequency divider 303 is 2, the VCO 302 oscillates synchronously at twice the frequency of the basic clock of the input data.

FIG. 4 is a block diagram showing an example of the configuration of the clock switching means 106 in FIG.
Reference numerals 405 denote gate circuits which constitute switches for switching clocks.

In FIG. 4, the control input is given from the data processing means 101 of FIG. The switching control circuit 401 sends a switching signal to the gates 404 and 405 according to the control input. The first clock from the clock generator 103 is input to the gate 404, and the second clock from the clock extractor 102 is input to the gate 403. In this example, the control signal is "high" if the gate 404 is opened to select the first clock, the second
Becomes "low level" when selecting the clock of. The output of the closed gate is fixed at “low level”, and the output of the open gate is output as the third clock via the gate 402.

FIG. 5a is a pad diagram showing the processing flow of the data processing apparatus (the first data processing apparatus 201 in the example) of the transmission source shown in FIG. 2, and reference numerals 501 to 508 denote steps of each processing.

FIG. 5b shows a processing flow of the data processing device (for example, the second data processing device 202) through which the data of FIG. 2 passes and the data processing device of the transmission destination (the third data processing device 203 in the example). It is a pad diagram, and 521-531 shows the step of each process.

The operation of the data processing device and the data processing system configured as described above will be described below with reference to FIG. Here, a system including voice transmission, which has recently become popular, is taken as an example.

Now, consider the case where the first data processing device 201 in FIG. 2 transmits voice data to the third data processing device 203. When reproducing audio data, it is necessary to accurately reproduce the sampling frequency at the time of recording. In other words, the clock of the first data processing device 201 must be preserved during data transmission (this kind of data is called real-time data here, as shown in the pad diagram of FIG. 5).

First, the processing flow of the first data processing device 201 is described in 5a.
This will be described with reference to the drawings. Step 501 is the start of the process.
In step 502, it is determined whether the data is real-time data. For real-time data such as voice, step 50
In step 3, the destination information (for example, the third data processing device 203) is added to the attached information (here, called the header) attached to the data.
In addition to the above, the fact that the data is "real-time data" is recorded. If not, at step 504, the fact that the data is "non-real-time data" is recorded. Since it is the data transmission source, the clock switching means 106 is set to the first clock side in step 505, and the data is transmitted in steps 506 and 507. After completion, the process ends in step 508.

Next, the processing flow of the second data processing device 202 is described as 5b
This will be described with reference to the drawings. Step 521 is the start of the process.
In steps 522 and 523, necessary processing is added to the input data.
Subsequently, it is determined whether or not the data output in step 525 is real-time data. If the data is real-time data, the clock switching means 106 is set to the second clock side in step 526 in order to save the clock, and the transmission destination (the third data processing device 203 in the example) is stored in the header in step 527;
Record that it is “real-time data”. If not, in step 528, the clock switching means 106 is set to the first clock side, and in step 529, "non-real-time data" is recorded. Step 530 indicates the sending of data. After repeating the above procedure as necessary as shown in step 524, the process ends in step 531. The processing flow of the third data processing device 203 is also 5b
As can be seen from the figure, there is no data to be transmitted because the data processing device is the transmission destination, and the steps related to data transmission in steps 524 to 530 are not executed.

As described above, in the present embodiment, in the case of real-time data, in the data processing device through which the data passes,
Since data is transmitted using the second clock extracted from the input data, the clock of the transmission source is preserved, and normal data processing can be performed. On the other hand, when transmitting data other than real-time data, each data processing device detects this from the header, and uses the internally generated first clock for data transmission. As a result, the clock jitter is not transmitted beyond the data processing device, and it is possible to prevent the error rate from deteriorating due to an increase in the number of data processing devices through which data passes.

FIG. 6 is a block diagram showing a configuration of a data processing device according to an embodiment (second embodiment) of the present invention (claim 3), 601 is a data processing means, 602 is a clock extracting means, 60
3 is a clock generation means, 604 is an input connector, 605 is an output connector, 606 is a clock switching means, and 607 is a clock generation request means. Clock extraction means 60 in FIG.
2. The clock switching means 606 is the same as in FIG.
Please refer to FIG. 3 and FIG.

In FIG. 6, the clock request generating means is added to the embodiment of FIG.
607 has been added. The clock request generation unit 607 generates an instruction for requesting the transmission destination to transmit a clock serving as a transmission reference before transmitting the data from the data processing unit 601 as necessary.

FIG. 7 is a block diagram of a data processing system according to the present invention (claim 4), wherein 701 to 704 are first to fourth data processing devices constituting the device, 705 to 708 are input connectors, and 709 to 7
Reference numeral 12 denotes an output connector, and reference numerals 713 to 716 denote optical fibers for connecting the respective data processing devices. Each data processing device advances data processing while exchanging data via an optical fiber. For example, data transmitted from the first data processing device 701 to the third data processing device 703 is output from the output connector 709 of the first data processing device 701, and is output via the second data processing device 702. , From the input connector 707 of the third data processing device 703.

FIG. 8a is a pad diagram showing the processing flow of the data processing device (the first data processing device in the example) of the transmission source shown in FIG. 7, and reference numerals 801 to 815 denote steps of each processing.

FIG. 8b is a pad diagram showing the flow of the clock transmission process of the data processing device (third data processing device in the example) of the transmission destination shown in FIG. 7, and 821 to 826 show steps of each process.

The operation of the data processing device and the data processing system configured as described above will be described below with reference to FIG.

The features of the second embodiment are that each data processing device is connected in a loop and that the clock generation request means requests the data processing device of the transmission destination to transmit a clock as a reference for transmission. is there. Here, transmission of audio data is taken as an example.

Now, consider a case where the first data processing device 701 in FIG. 7 transmits audio data already recorded on a recording medium such as a CD to the third data processing device 703. In this case, the data to be transmitted is real-time data.

First, the processing flow of the first (transmission source) data processing device 701 will be described with reference to FIG. 8a. Step 801 is the start. In step 802, it is determined whether the output data is real-time data. Steps 812 to 815 are for the case of non-real-time data, and are the same as those in the first embodiment. If the output data is real-time data, a clock transmission request is transmitted to the third (transmission destination) data processing device 703 in step 804. Steps 805 and 806 are waiting times until the requested clock arrives. In step 807, the transmission destination and "real-time data" are set in the header. In step 808, the clock switching means 106 is set to the second clock. Steps 809 and 810 indicate transmission of data. In this embodiment, audio data recorded on a recording medium such as a CD is read and transmitted using the second clock. After the end, a stop of the clock is requested to the transmission destination in step 811, and the process ends in step 803. The processing procedure of the second data processing device 702 through which data passes is the same as that of the second data processing device 202 of the first embodiment.

Next, the processing flow of the third (transmission destination) data processing device 703 will be described with reference to FIG. 8B. The procedure for processing the input data is the same as that in FIG. 5b, and here, the processing for the clock transmission request will be described. In FIG. 8B, step 821 is the start of the interrupt processing of the request command.
At step 822, it is determined whether or not the request is a clock transmission request, and if so, clock transmission is started at step 823. In step 824, it is determined whether or not the request is a clock stop request. If so, the clock transmission is stopped in step 825. Thereafter, in step 826, the interrupt processing ends and the routine returns.

As a result, the first (transmission source) data processing device 701
Performs reading and transmission of data based on the clock transmitted from the third (transmission destination) data processing device 703, so that the third (transmission destination) data processing device 703 uses the first (transmission source) The data processing is performed using a clock that is exactly the same as that of the data processing device 701 and does not include jitter, and the sound is reproduced correctly and without distortion.

Effect of the Invention As described above, according to the present invention, jitter included in data transmitted between data processing devices connected by a cable can be suppressed from accumulating due to an increase in the number of data processing devices. Can provide a data processing system in which troubles caused by the data are reduced. Further, since data transmission from the transmission source data processing device is performed with reference to the clock supplied from the transmission destination data processing device, it is possible to reduce the trouble due to jitter even in the case of transmitting real-time data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a data processing system constituted by connecting a plurality of data processing devices of FIG. 1, and FIG. FIG. 4 is a block diagram showing a configuration example of the clock extracting means in FIG. 1, FIG. 4 is a block diagram showing a configuration example of the clock switching means in FIG. 1, and FIG. 5 explains the operation of the data processing system in FIG. FIG. 6 is a block diagram showing a data processing device according to a second embodiment of the present invention. FIG. 7 is a block diagram of a data processing system constituted by connecting a plurality of data processing devices shown in FIG. 8 is a pad diagram for explaining the operation of the data processing system of FIG. 7, FIG. 9 is a block diagram showing the configuration of a conventional data processing system, and FIGS. 10 and 11 are diagrams of a data processing apparatus in the conventional example. Show configuration FIG. 101,601 ... data processing means, 102,602 ... clock extraction means, 103,603 ... clock generation means, 104,205 to 208,70
5 to 708 …… Input connector, 105,209 to 212,605,709 to 712
…… Output connector, 106,606 …… Clock switching means, 21
0,701 ... first data processing device, 202,702 ... second data processing device, 203,703 ... third data processing device, 20
4,704 ... the fourth data processing device, 213-215,713-715 ...
… Optical fiber, 301… phase comparator, 302… VCO, 303…
… Frequency divider, 401 switching control circuit, 402 to 405 gate circuit, 607 clock request generation means.

Claims (4)

(57) [Claims] An input connector for connecting a cable from an external device; clock generating means for generating a first clock; extracting a clock component of input data input via the input connector; Clock extracting means for outputting one of the first clock and the second clock, and clock switching means for outputting the third clock as a third clock; and processing the input data according to the second clock. A data processing unit for generating output data in accordance with the third clock; and an output connector for sending output data of the data processing unit to a cable connected from the outside. A data processing device for selecting a second clock in the case of real-time data. 2. A data processing device comprising a plurality of data processing devices according to claim 1, wherein an input connector of one data processing device and an output connector of another data processing device are sequentially connected by a cable, and data is transmitted through the cable. system. 3. An input connector for connecting a cable from an external device; clock generating means for generating a first clock; and a clock component of input data input via the input connector, Clock extracting means for outputting one of the first clock and the second clock, and clock switching means for outputting the third clock as a third clock; and processing the input data according to the second clock. A data processing means for generating output data in accordance with the third clock; an output connector for sending output data of the data processing means to a cable connected from outside; transmitting the output data before sending the output data And clock request generating means for generating a clock request command for requesting clock transmission. The clock switching means selects a second clock when the output data is real-time data, and the data processing means outputs the clock request command from the output connector as needed. 4. A plurality of data processing devices according to claim 3, wherein an input connector of one data processing device and an output connector of another data processing device are sequentially connected in a loop by a cable, and data is transmitted through the cable. Data processing system.