JPH0511692B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-speed optical bus using optical fibers that transmits large amounts of information at high speed in information processing systems such as electronic computers and electronic exchanges.

(Conventional technology) As information processing using electronic computers and other devices becomes faster and more distributed, the need for high-speed optical buses using optical fibers that can transmit large amounts of information at high speed and with high quality is increasing. . The present invention relates to this high-speed optical bus.

FIG. 3 is a block diagram showing an example of a general high-speed optical bus using N optical fibers.
In the figure, 301 is a transmitter, 302(1) to 30
2(N) is the data line, 302 _(N+1) is the synchronization line, 303(1)
~303 _(N+1) is the electrical/optical converter (EO), 304(1)
~304 _(N+1) is an optical fiber, 305(1) ~305 _(N+
1) is the optical/electrical converter (OE), 306(1) to 306 _(N+
1) is a wideband amplifier (A), 309(1) to 309(N) are identification and reproducing circuits (DEC), and 301 is a receiving section.

As shown in FIG. 3, the synchronization clock transmitted from the transmitter 301 and N pieces of parallel information synchronized with this synchronization clock are connected to the synchronization line 302 _(N+1) and data lines 302(1) to 302(N), respectively. The electrical signals are transmitted using N+1 electrical/optical converters 303(1) to 303 _(N+1) and converted from electrical signals to optical signals. This optical signal is N+1
It is transmitted to the receiving side using optical fibers 304(1) to 304 _(N+1) , and converted into electrical signals by N+1 optical/electrical converters 305(1) to 305 _(N+1) on the receiving side. It is converted into a synchronous clock and reception information. Furthermore, the aforementioned N
The received information transmitted using the main data lines 302(1) to 302(N) is transmitted to the identification and reproducing circuits 309(1) to 309.
At _{(N+1), the signal} undergoes waveform identification shaping and reproduction processing using the synchronization clock transmitted using the synchronization line 302 _(N+1), and then is transmitted to the receiving section 310.

(Problems to be Solved by the Invention) In FIG.
03 _(N+1) , optical/electrical converter 305(1) to 305 _(N+1
) , the broadband amplifiers 306 (1) to 306 _(N+1) are generally composed of electric elements such as transistors, light emitting elements such as laser diodes and light emitting diodes, and light receiving elements such as avalanche photodiodes. Each of these elements has individual variations in characteristics. For example, electric devices have variations in waveform response characteristics, light-emitting devices have variations in emission wavelength,
Furthermore, there are variations in the temperature characteristics of each element. Further, among the optical fibers 304(1) to 304 _(N+1) , there are variations in fiber dispersion characteristics and the like.

When transmitting parallel data at high speed, variations in these element characteristics and pattern effects of transmitted signals particularly increase skew (phase distortion) between data of transmitted information and delay variations between signals. Further, phase variations between signals also occur due to distance accuracy between installed cables. Receiving section 3
The signal received by the reproducing circuit 30 identifies the synchronization clock transmitted using the synchronization line 302 _(N+1).
In addition to 9(1) to 309(N), this signal identifies and reproduces the signal waveform of transmission information to absorb skew between data and variation in delay between signals.

However, the synchronized clock and transmitted information are
Waveform jitter is present due to variations in element characteristics, pattern effects of transmitted signals, etc. Furthermore, the phase relationship between the synchronization clock used to absorb skew of transmitted information and the transmitted signal is uniquely determined at the time of bus installation. Therefore, the phase relationship between the transmitted signals and between the synchronized clocks is not necessarily optimal, and in addition, due to jitter between the transmitted signals and between the synchronized clocks, the identification and regeneration circuits 309(1) to 309(N) The rate of occurrence of code errors increases when identifying and reproducing waveforms using . Therefore, the transmission error rate between the transmitting section 301 and the receiving section 310 decreases. These drawbacks are a factor that hinders the further increase in speed of high-speed optical buses using optical fibers. Furthermore, providing a synchronous clock line separately from the data line to transmit the synchronous clock requires extra light-emitting/light-receiving elements, electric elements, etc. for the synchronous clock, resulting in an increase in the number of circuits. If the wire is accidentally disconnected, the clock will not be transmitted to the receiving side, making it impossible to identify the information on the receiving side, resulting in a decrease in reliability.

SUMMARY OF THE INVENTION Therefore, an object of the present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to identify a transmitted signal without error without transmitting a synchronized clock from a transmitting side to a receiving side, and to identify data transmitted in parallel. An object of the present invention is to provide a high-speed optical bus that controls the phase of transmitted data so that the phase states between the two are in the same phase.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a high-speed optical bus that includes N electrical/optical converters to which N data sequences are respectively input, and the N optical fibers each having one end connected to the N electrical/optical converters; N optical delay means connected to the other end of the N optical fibers and controlling the propagation time of the optical signal; N optical/electrical converters each inputting the outputs of the N optical delay means; N timing extraction means each extracting a clock component from the outputs of the N optical/electrical converters; N
The output of a predetermined specific timing extracting means among the timing extracting means is used as a common clock component, and the output of the predetermined timing extracting means
N-1 phases for performing a phase comparison between the clock component obtained as an output of one of the timing extraction means and the common clock component, and outputting a delay control signal to the optical delay means corresponding to each clock component; The present invention is characterized in that it includes a comparator and N identification and reproducing circuits that respectively identify the outputs of the N optical/electrical converters based on the clock components output by the N timing extraction means.

(Function) In realizing a high-speed optical bus, it is desirable to reduce the number of circuits to be configured as much as possible, and absorb skew between data and delay variations between signals without transmitting a synchronized clock from the transmitter to the receiver. As a result, a high-speed optical bus can be realized with fewer circuit configurations.

In addition, the information transmitted from the transmitter is converted into an electrical signal by an optical/electrical converter via an optical delay means.
After being amplified by a broadband amplifier, it is branched into two. 2
One of the branched signals is input to a timing extraction circuit, which extracts a timing signal from its own data. The timing signals extracted by this timing extraction circuit are each input to an identification circuit, and N
N-1 timing signals excluding an arbitrary M-th timing extraction circuit output from among the data series are input to each phase comparator. On the other hand, the M-th timing extraction circuit output is commonly input to N-1 phase comparators, and phase comparisons with N-1 timing signals are performed, respectively. This phase comparator applies M
An electric signal (delay control signal) for controlling increase/decrease in the amount of delay is supplied so that the timing signal and each of the N-1 timing signals are in the same phase. As a result, the phases of the N timing signals, that is, the synchronized clocks, all become the same phase, and the output signal of the wideband amplifier is identified and reproduced by the identification circuit using this timing signal, so that skew between data and delay variations between signals are reduced. It becomes possible to absorb data, and it becomes possible to reliably obtain synchronization between data. Furthermore, since the synchronous clock (timing signal) of the present invention is obtained entirely by a method of extracting the timing signal from data, deterioration in the bit error rate caused by phase jitter of the synchronous clock can be suppressed. It becomes possible.

(Example) The operating principle of the high-speed optical bus of the present invention will be explained below.

FIG. 1 is a configuration diagram of a high-speed optical bus showing an embodiment of the present invention, in which 101 is a transmitter, 102 ₍₁₎ to 1
02 _(N) is a data line, 103 ₍₁₎ to 103 _(N) are electrical/
Optical converter (EO), 104 ₍₁₎ to 104 _(N) optical fiber, 105 ₍₁₎ to 105 _(N) are optical/electrical converters (OE), and 106 ₍₁₎ to 106 _(N) are broadband amplifiers. (A),
107 ₍₁₎ to 107 _(N) are timing extraction circuits (TIM) (“Basics and new technology of PCM communication”, Hiroshi Inose,
(detailed explanation is given in Sanho), 109 ₍₁₎ ~ 109 _(N
) is identification and reproduction circuit (DEC), 108 ₍₁₎ ~ 108 _(N-1)
is a phase comparator (PC) (“How to use PLL-IC KAI”,
Co-authored by Masayasu Hata and Keisuke Furukawa, there is a detailed explanation) 1
11 ₍₁₎ to 111 _(N) are optical delay circuits, 112 ₍₁₎ to 11
2 _(N) is an optical fiber (or lens), and 110 is a receiving section. In the figure, N pieces of parallel information transmitted from the transmitter 101 are transmitted through data lines 102 ₍₁₎ to
102 _(N) , and is converted from an electrical signal to an optical signal in N electrical/optical converters 103 ₍₁₎ to 103 _(N) , and then transmitted through N optical fibers 104 _(1).
~104 _(N) . Optical fiber 104 ₍₁₎ ~
The optical signal sent to 104 _(N) is transmitted to the receiving side, and is further transmitted through N optical fibers (and optical lenses: 112 ₍₁₎ to 111 _(N)) through optical delay circuits 111 _{(1) to 111 (N).}
111 _(N) by N optical/electrical converters 105 ₍₁₎
~105 _(N) . N pieces of parallel information converted from optical signals to electric signals by N pieces of optical/electrical converters 105 ₍₁₎ to 105 _(N) are sent to N pieces of wideband amplifier 1.
06 ₍₁₎ to 106 _(N), the received information is amplified to a sufficient amplitude level (for example, 1.0 V _pp ). The output signal reception information of the wideband amplifiers 106 ₍₁₎ to 106 _(N) is branched into two, and one of the signals is sent to the timing extraction circuit 107 ₍₁₎ to 107 _(N).
is input as timing extraction information. Timing extraction circuits 107 ₍₁₎ to 107 _(N) extract timing signals from the received information input from wideband amplifiers 106 ₍₁₎ to 106 _(N) , and output these signals as synchronized clocks. A method of extracting a timing signal from received information is called a "self-timing extraction method," and for example, a method using a SAW filter (surface acoustic wave filter) is known. Each of the synchronized clocks extracted by the timing extraction circuits 107 ₍₁₎ to 107 _(N) is branched into two, and the signal output from the timing extraction circuit 107 ₍₁₎ (in this embodiment, the first series is used). may be any M-th clock) is input to the phase comparators 108 ₍₁₎ to 108 _(N) as a reference phase synchronized clock. The output signals of timing extraction circuits 107 ₍₂₎ to 107 _(N) are output to phase comparators 108 ₍₁₎ to 108 _(N-1) , respectively.
is input to. Phase comparator 108 ₍₁₎ to 108 _(N-1)
Then, the phase difference between the synchronous clocks input from the timing extraction circuits 107 ₍₂₎ to 107 _(N) and the synchronous clock input from the timing extraction circuit 107 ₍₁₎ is detected, and the optical delay circuit 111 _{(2) )} ~
111 _(N) , respectively, outputting control signals for controlling increase/decrease in the amount of delay. Optical delay circuit 111 ₍₂₎ ~111
_(N) , the amount of delay is changed by the control signal input from the phase comparators 108 ₍₁₎ to 108 _(N-1) , and the phase of the received information in the optical signal state is changed. Setting the total delay amount of the optical delay circuits 111 ₍₂₎ to 111 _(N) more than necessary may cause an increase in the optical power loss of the optical signal, so it is necessary to make a decision in consideration of the transmission birate. (For example, it is designed for one time slot). In addition, the optical delay circuit 11
The initial delay amount from 1 ₍₂₎ to 111 _(N) should be 1/1 of the total delay amount in order to have enough margin for increasing and decreasing the delay amount.
It is necessary to set the control signal from the phase comparator so that the delay amount is 2. Furthermore, the optical delay circuit 11
The set delay amount of 1 ₍₁₎ is the optical delay circuit 111 ₍₂₎ to 11
In order to prevent the control operation of optical delay circuits 111 _{( 2)} to 111 _{(N) from becoming saturated, it is necessary to design the delay amount to be slightly larger than that of the optical delay circuits 111 (2) to 111 (N)} . Optical delay circuit 111
₍₁₎ to 111 _(N) can be realized in various ways, such as an optical fiber delay circuit, but in this embodiment, an optical waveguide will be described as an example. There are various crystals used to form the optical waveguide, such as LiNbO ₃ and GaAs. When an electric field is applied from the outside to these materials, the refractive index changes due to the first-order electro-optic effect. In other words, it is possible to equivalently change the propagation optical path length of an optical signal propagating within an optical waveguide.
There is a detailed explanation on p284).

In this way, the parallel reception information made in phase by the optical delay circuits 111 ₍₁₎ to 111 _(N) is transmitted to electrical elements, light emitting and light receiving at the output terminals of the broadband amplifiers 106 ₍₁₎ to 106 _(N). This is a state in which skew between data and variation in delay between signals caused by variations in element characteristics, dispersion characteristics of optical fibers, pattern effects of transmission signals, etc. are absorbed. Therefore, the received information in the identification circuits 109 ₍₁₎ to 109 _(N) is transmitted to the timing extraction circuits 107 ₍₁₎ to 10
By identifying and reproducing the synchronized clocks of the same phase extracted in step 7 _(N) , synchronized data can be sent to the receiving unit 110 between the parallel received information with delay variations and skew removed. It becomes possible.

In the explanation so far, we have described an embodiment in which the clock signals used in the N identification and regeneration circuits are the clock signals extracted by the N timing extraction circuits, but as shown in Figure 2, the reference synchronous clock to the phase comparator is It may also be a mode in which the information is commonly input to N identification and reproducing circuits.

(Effects of the Invention) As described above, it can be seen that when the high-speed optical bus according to the present invention is used, the transmission error characteristics due to the synchronous clock phase and phase jitter are significantly improved compared to the high-speed optical bus having the conventional configuration.

In this way, the present invention aligns the phases of parallel received information and extracts parallel synchronized clocks of the same phase, and can be used at high speed in information processing systems such as electronic computers, or in parallel data transmission systems. It is expected that it will be used in various devices that need to transmit information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a high-speed optical bus according to one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional high-speed optical bus. be. 101, 301... transmitter, 110, 310...
...Receiving section, 102 ₍₁₎ ~ 102 _(N) , 302 ₍₁₎ ~ 30
2 _(N+1) ...Data line, 103 ₍₁₎ ~ 103 _(N) , 30
3 ₍₁₎ ~303 _(N+1) ...Electric/optical conversion section, 104 ₍₁₎
~104 _(N) ,304 ₍₁₎ ~304 _(N+1) ...Optical fiber, 105 ₍₁₎ ~105 _(N) ,305 ₍₁₎ ~305 _(N+1)
...Optical/electric conversion section, 106 ₍₁₎ ~ 106 _(N) , 30
6 ₍₁₎ ~306 _(N+1) ... wideband amplifier, 109 ₍₁₎ ~
109 _(N) , 309 ₍₁₎ ~ 309 _(N) ... Identification regeneration circuit, 107 ₍₁₎ ~ 107 _(N) ... Timing extraction circuit, 108 ₍₁₎ ~ 108 _(N-1) ... Phase comparison vessel, 11
1 ₍₁₎ ~111 _(N) ... Optical delay circuit, 112 ₍₁₎ ~11
2 _(N) ...Optical fiber (optical lens).

Claims (1)

[Claims] 1 N electrical/optical converters into which N data sequences are input, N optical fibers each having one end connected to the N electrical/optical converters, and the N optical fibers. N optical delay means that are connected to the other end and control the propagation time of the optical signal; and N optical delay means that input the outputs of the N optical delay means, respectively.
N optical/electrical converters, and clock components are extracted from the outputs of the N optical/electrical converters, respectively.
and the output of a predetermined specific timing extracting means among the N timing extracting means as a common clock component, and the output of the N-1 timing extracting means other than the specific timing extracting means. N-1 phase comparators each perform a phase comparison between the clock component obtained as an output and the common clock component and output a delay control signal to the optical delay means corresponding to each clock component; The clock component outputted by the timing extraction means is used to extract the N lights/
and N identification/regeneration circuits for respectively identifying electrical converter outputs.