JP2671670B2 - Microcomputer system bus expansion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus expansion device which enables connection of the system buses of two microcomputer systems placed apart from each other.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a system bus of a conventional microcomputer system. In FIG.
Is a first microcomputer system, 2 is a second microcomputer system, 3 is a priority determining circuit, 4 is a bus clock signal (BCLK), 5 is a bus request signal (BREQ), 6 is a bus request signal (BREQ), 7 is a bus priority signal (BPR
N) and 8 are bus priority signals (BPRN), and 9 is a bus busy signal (BUSY). In FIG. 3, the address bus, the data bus and other control signals are omitted. FIG. 4 shows an example of the timing of the signals 4 to 9 in FIG.

For example, consider a device in which two microcomputer systems are connected to one system bus as shown in FIG. First microcomputer system 1
When data is exchanged with the second microcomputer system 2 using the system bus, the following procedure is performed. First, the first microcomputer system 1 sends a bus request signal 5 (hereinafter referred to as BREQ5) to the priority determining circuit 3 in order to obtain the right to use the bus. In response to this, the priority determination circuit 3 returns a bus priority signal 7 (hereinafter referred to as BPRN7). In response to this, the first microcomputer system 1 enables the busy signal 4 (hereinafter referred to as BUSY4). When the busy signal becomes valid, the second microcomputer system 2 cannot use the bus until it becomes invalid.

As described above, the acquisition of the right to use the bus is completed, and data is exchanged on the data bus.
When two microcomputer systems request the bus, the one who requests the bus first gets the right to use. When a bus request is issued at the same time, a system with a predetermined high priority acquires the right to use, and a system with a low priority cannot use the system until the high system abandons the bus.

FIG. 4 shows the timing when the first microcomputer system 1 having a high priority makes a bus request after the second microcomputer system 2 makes a bus request. As shown in A, the second microcomputer system 2 synchronizes with BCLK4 and BREQ.
When 6 is sent, the priority decision circuit 3 returns BPRN7. As shown in B, the second microcomputer system 2 enables BUSY9 in synchronization with BCLK4,
Start using the bus. Next, as shown in C, when the first microcomputer system 1 issues BREQ5, the priority determining circuit 3 stops the output of BPRN8 and issues BPRN7 to the first microcomputer system 1 with high priority. The first microcomputer system 1 cannot use the bus because the BUSY signal 9 is already valid. As shown in D, when the second microcomputer system 2 finishes using the bus, it invalidates BREQ6 and then BUSY9 and abandons the bus. As shown in E, when the first microcomputer system 1 confirms that BUSY9 has been disabled, it enables BUSY9 and starts using the bus. That is, the bus can be acquired when the busy signal is invalid after the bus priority signal is received. As shown in F, when the first microcomputer system 1 finishes using the bus, it invalidates BREQ5 and then disables BUSY and abandons the bus. Further, the priority determining circuit 3 invalidates the BPRN7. In this way, the acquisition of the right to use the bus is performed in synchronization with BCLK4.

[0006]

Since the conventional microcomputer system bus is constructed as described above, the first microcomputer system 1 and the second microcomputer system 2 are separated from each other by using a cable. When connecting, there is a problem that two microcomputer systems may compete on the bus and cannot exchange data depending on the timing, as described below.

FIG. 5 shows a case where the first microcomputer system 1 and the second microcomputer system 2 are connected to each other at a distance and using a cable. In FIG. 5, 1 to 9 are the same signals as in FIG. Reference numeral 10 is a first driver / receiver circuit, and 11 is a second driver / receiver circuit. BCLK12, BREQ13, BPRN14, B on the second microcomputer system side
USY15 is BCLK4, BREQ6, BPRN8, BUS on the first microcomputer system 1 side.
It is the same signal as Y9, but there is a time difference due to the first driver / receiver circuit 10, the second driver / receiver circuit 11, and the cable.

FIG. 6 shows the timing when the buses compete with each other. As shown by A in FIG. 6, when the second microcomputer system 2 outputs BPRN6, the signal is delayed by the second driver / receiver circuit 11 and then reaches the priority determining circuit 3 to output BPRN8. In response to this, the second microcomputer system 2 enables BUSY 15 as shown at B and starts using the bus. On the other hand, as shown in C, when the first microcomputer system 1 having a high priority requests the bus and issues BREQ5, the priority determining circuit 3 stops the output of BPRN8 and outputs BPRN7.
At this time, as indicated by E, BUSY9 in the system bus on the first microcomputer system 1 side is still invalid, so the first microcomputer system 1 enables BUSY9 and starts using (bus is expanded. If it does not exist, BUSY becomes valid one clock after the output of BREQ6, but this occurs when BUSY is not valid within two clocks after the output of BREQ6 as in this example.) . Therefore, as shown in G, when BUSY 15 of the second microcomputer system 2 arrives after the delay, the competition for the bus starts.

The present invention has been made in order to solve the above-mentioned problems, so that the system buses of two microcomputer systems which are spaced apart from each other can be connected to each other by using a cable so that they can access each other. The purpose is to do.

[0010]

An expansion device for a microcomputer system bus according to the present invention uses a driver / receiver circuit for connecting two microcomputer systems, a cable and a forced busy signal generating circuit.

[0011]

In the expansion device for the microcomputer system bus according to the present invention, by using the forced busy signal generating circuit, bus competition is prevented and the expansion of the system bus is realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 15 are exactly the same as those in FIG. Reference numeral 16 is a forced busy signal generation circuit.

In FIG. 1, when the second microcomputer system 2 requests the bus and outputs BREQ13, the priority determining circuit 3 returns BPRN8. In the conventional method, the second microcomputer system 2 enables the BUSY 15 after receiving the BPRN 14, but in the present invention, the compulsory busy signal generation circuit 16 is provided on the first microcomputer system 1 side as soon as the BPRN 8 is output. BUSY9 on the system bus is forcibly enabled. By doing so, it is possible to prevent bus contention that occurs when the first microcomputer system 1 having a high priority requests the bus after the second microcomputer system 2 requests the bus in the conventional method.

The reason will be described with reference to FIG.
As shown by A in FIG. 2, when the second microcomputer system 2 issues BREQ13, the priority determination circuit 3 returns it to BPRN8. As indicated by I, the forced busy signal generation circuit 16 enables BUSY 9 on the system bus of the first microcomputer system 1.
The second microcomputer system 2 enables BUSY 15 after receiving BPRN 14 as shown at B. This BUSY 15 is transmitted to the system bus of the first microcomputer system 1 after a delay as shown by G. Further, as shown in C, the first microcomputer system 1 having a high priority requests the bus and BR
When EQ5 is issued, the priority determination circuit 3 is BPRN8
And outputs BPRN7 instead. In the conventional method, since the BUSY which has become valid on the side of the second microcomputer system 2 is not yet transmitted at this point, the first microcomputer system 1 having a high priority can use the bus by enabling BUSY. However, since the BUSY is enabled first as indicated by I, the bus cannot be used until the second microcomputer system 2 disables BUSY as indicated by D and E. In this way, bus contention is avoided and buses are used in the order of earliest demand.

[0015]

As described above, according to the present invention, since the first microcomputer system receives the BUSY signal first by adding the forced busy signal generating circuit, the contention of the bus due to the delay of the signal is avoided. The system bus can be expanded.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a timing of the embodiment of the present invention.

FIG. 3 is a diagram showing a conventional microcomputer system bus.

FIG. 4 is a diagram showing timing of a conventional microcomputer system bus.

FIG. 5 is a diagram showing a case where a conventional microcomputer system bus is expanded by using a driver / receiver circuit and a cable.

FIG. 6 is a diagram showing a timing when a conventional microcomputer system bus is expanded by using a driver / receiver circuit and a cable.

[Explanation of symbols]

 1 1st microcomputer system 2 2nd microcomputer system 3 priority determination circuit 4 BCLK 5 BREQ 6 BREQ 7 BPRN 8 BPRN 9 BUSY 10 1st driver / receiver circuit 11 2nd driver / receiver circuit 12 BCLK 13 BREQ 14 BPRN 15 BUSY 16 Forced busy signal generation circuit

Claims (1)

(57) [Claims] 1. A system bus expansion device for connecting a first microcomputer system and a second microcomputer system, wherein said first device receives a bus request signal from said first and second microcomputer systems. A first driver / receiver circuit connected to a first system bus connecting the priority determining circuit for outputting a bus priority signal to the second microcomputer system and the first microcomputer system, A second driver / receiver circuit connected to a second microcomputer system, a system bus connection cable connecting the first and second driver / receiver circuits, and the second microcomputer from the priority determining circuit. Bus prior to system And a forced busy signal generation circuit for generating a forced busy signal on the first system bus for forcibly validating the bus busy signal on the system bus on the side of the first microcomputer system when a priority signal is generated. An expansion device for a microcomputer system bus, which is characterized in that