SU1457643A1 - Majority-redundant trunk-line modular computing system - Google Patents

Abstract

The invention relates to computing, and can be used in the construction of highly reliable systems. The purpose of the invention is to expand the functionality by backing up active modules. The system consists of voting blocks, synchronizers, processors, active modules, passive modules, blocks of main drivers, data address register, clock generator. The purpose of the invention is achieved by detecting the outgoing block by a voting unit and turning on a separate synchronizer for each subsystem. 2 hp f-ly, 11 ill. ;

Description

cl

The invention relates to computing technology and may find application in the construction of information processing systems of high reliability.

The purpose of the invention is to expand the functionality by backing up active modules.

FIG. 1, 2. shows the structural scheme of the proposed major-redundant backbone modular computing system; Fig, 3, 4 is a block diagram of a synchronizer; in fig. 5 - functions 1-onal-diagram of the synchronization nodes of sigialov synch pulses of the active device. Input characteristics, passive device sync pulses, requirements pr. my access, interrupt request, direct access grant, interrupt grant and confirmation of choice; Fig. 6 shows functional; on the diagram of the output signal synchronization node; in fig. 7 is a functional diagram of the node generating delayed torsional signals; in fig. 8 - the voting unit is functional; in fig. 9 is a timing diagram of the main signals of the reserved subsystem in case of an error in the operation; FIG. 10 is a timing diagram of the main signals in case of an error in performing the Record operation; in fig. And is the timing diagram of the program interruption in case of an error in the formation of the interrupt vector.

The major-redundant backbone modular computing system (see Fig. I, 2) contains M in parallel and synchronous operation of the transducer.

sd

one

Reserved | x subsystems, each of which includes a block of the first voting, synchronizer 2, and sor. 3 .1 active modules 4, m of passive modules 5, block 6 of the trunk — Hbbt of drivers of the block of voice and block 7 / of the main forms , processor units, J2t blocks of main units of active modules,. blocks 7., -. 7 main drivers of passive devices, register 6 data addresses. and clock generator 9,

ten

FIG. Figure 9 shows the timing diagrams of the main signals one on; 1dsnsten when performing the Read Data (Input) operation in cjjynae, when errors occur during the transfer. giving both addresses and data. The system works like this.

On address / data (YES) buses 71 (see FIG. 2), the active module or processor sets the address and sets the synchronization signal 72 of the active device (SIL), after synchronizing (see FIGS. 3, 4) Co-connection of 15 and more signals 72 SIL on

keeps nodes 10, -lOj synchronizing and entering the synchronization node JO (see,

signals respectively sync pulse FIG. 3, 4) at its output appears

active input device, snn-signal 73 SIAG, which, through the element

passive device's throat pulses, OR 12 form a 74 Strobe signal

20

direct access requests, interrupt requests, direct access requests, interrupt assignments, selection acknowledgments, signal synchronization node 1 1 to the output.

errors submitted to the block 1 vote (see Fig. 8). The SIAH signal is delayed by the delay element 25 at the time of the error analysis in the voting block 1. Once established,

elements OR 12–16, / elements AND 17–24, 25 signal-75 signal URergo form delay elements 25–29, elements NOT drivers 7 of a malfunctioning subsystem and

30-31 and the node 32 of the formation of the delayed control signals.

Nodes V0, (see FIG. 5) contain a voting element 33, an AND 30 34 element, a delay element 35, an AND 36 element and an OR 37 element.

The node .11 (see Fig. 6) contains the voting element 38, the AND element 39 delay element 40, the AND element 41, the OR element 42 and the NOT element 43. The delayed control signal formation node 32 (see Fig. 7) contains elements And 44-48, delay elements 49-52, elements HE 53-55 and triggers 561-59.

The topics switch to data reception, and, therefore, the delivery of the incorrect address from the faulty active module 4 or processor 3 to the trunk stops. Simultaneously at signal 75 Error is being recorded

35

the addresses in the register 8 are data addresses and are opened to transfer data to the buses 71 of the driver 6, thereby correcting the wrong code value. addresses (the first shaded area in FIG. 9); Error 75 also goes to node 32 of generating 40 delayed control signals of synchronizer 2 (see FIG. 7). In node 32, the signal 75 through the element And 45 and the trigger 57 generates a signal 76 Za45

50

Block 1 vote by whom. FIG. eight). contains n (n block size) voting elements 60, element OR 61, delay elements 62, 63, elements NOT 64-66, elements AND 67, 68, element OR 69 and trigger 70.

Positions 71-99 in FIG. denotes control signaling buses.

As standard protocols, exchange standards in any of the known trunk systems can be selected. The transition from one JC standard to the Other will require a change in the operation of the synchronizer. 2..

Let us consider the operation of the system on the example of the widely used interface of the electronic computer Electronika-60.

40

FIG. Figure 9 shows the timing diagrams of the main signals one on; 1dsnsten when performing the Read Data (Input) operation in cjjynae, when errors occur during the transfer. giving both addresses and data. The system works like this.

On address / data (YES) buses 71 (see FIG. 2), the active module or processor sets the address and sets the synchronization signal 72 of the active device (SIL). After receiving, 12 generates a strobe signal 74

errors submitted to the block 1 vote (see Fig. 8). The SIAH signal is delayed by the delay element 25 at the time of the error analysis in the voting block 1. Once established,

Signal-75 signal error Error 7 drivers incorrectly working subsystem

The topics switch to data reception, and, therefore, the delivery of the incorrect address from the faulty active module 4 or processor 3 to the trunk stops. Simultaneously at signal 75 Error is being recorded

thirty

35

the addresses in the register 8 are data addresses and are opened to transfer data to the buses 71 of the driver 6, thereby correcting the wrong code value. addresses (the first shaded area in FIG. 9); Error 75 also goes to node 32 of generating 40 delayed control signals of synchronizer 2 (see FIG. 7). In node 32, the signal 75 through the element And 45 and the trigger 57 generates a signal 76 Over 5

0

pret CB, which through the element NOT 31 prohibits the passage of the delayed signal 73 SIAG and the signal 77 Input 1, With the delay required to set the correct address, the node 32 through element 52, element AND 44 and trigger 56 generate a signal 78. which through element OR 13 causes the appearance of a trunk signal 79 SILM. On signal 79 fic-. The occurrence of its own address on buses 71 in the control circuits of that of modules 4 and 5, to which this address corresponds and with which the IMM is established, is the exchange of magnets.

With the delay necessary for the hatentized fixation of its address, the signal 75 is removed. Error 75 shapers 6 and 7 return to their normal state; 6 - on receiving data from pin 71, 7 - to receive mode - transmission, depending on the control signals of the corresponding modules.

At that time, as the address is being adjusted on the buses 71, the active device sets the signal 80 Input, After the arrival of K and. More signals Inputting the input of the synchronization node 10 at its output appears signal 77 Input I. Signal 75 Error, having generated Signal 76 Forbid CB, does not allow the passage of the-signal 77 Input 1 through the terminal And 23.

With the delay required for the module to fix its address, and after the formers 6 and 7 return to normal through the delay element 49, the AND 47 and the trigger 58 are generated at the output of the node 32, a signal 81, which through the OR element 14 causes the appearance of the main signal 82 Input M. The selected module of the subsystem responds to the signal 82 with the passive device synchronization signal 83 (CIP). At this moment, subsynchronization of the subsystems takes place, which is provided in this case by node 10. Signal formation delays 83 SIPs on the incorrectly working highway, associated with the need to correct the address, are not 250-300 compared to a good highway. Therefore, the delay value (delay element 35) in the corresponding node. 10 is taken equal to 500 not so that the subsystems after the address error in one of them did not go out of synchronicity. At the output of node 10 a SIPG signal 84 is formed. This signal through the element And 17 and the element OR 12 generates 74 signal Error gate and with a delay for analyzing the error situation through the delay element 27 enters the inputs of elements And 19 and 20. In the case of the signal 75 Error is similar to the correction

addresses data is corrected gg pa 8 data addresses. At that time in (the second shaded area of the nanormally operating subsystems

FIG. 9), and the signal is 84 SIPG with a delay, (signals 75 Error and, therefore, through the element AND 20, the element for-but, 86 Prohibition B is absent) in delays, 29 and the element OR 16 (the signal. more signals 88 logout

85 SIPA) is fed to the inputs of the active module 4 and processor 3.

In response to the SIPA signal 85, the active module 3 or 4 removes the signal of 80 Input. In this case, the signals of 77 Input I, 75 Error are successively removed, the formers 6 and 7 return to normal, the signal of 82 Input M is removed. In response to this SIP signal 83 is cleared, and then SIPG signals 84 and SIPA 85 are terminated. The loop is terminated by signals 72 SIA, 73 SIAG, 76 Barred CB, 79 SIAM.

At this point, the subsystem is defective late in time with respect to properly working. Full synchronization of subsystems will occur at the beginning of the next cycle of exchange on the trunk with the arrival of signals 72 SIA corresponding nodes 10; synchronization will generate 73 SIM signals simultaneously in all subsystems). /

In FIG. IU shows the timing diagrams of the main signals of one

from the subsystems during the operation Write Data (Output) in the case when there are errors in the transfer of both the address and the data on the highway.

 The address on the buses 71 YES and the signals 73 SIAG, 75 Error, 79 SIAM are set when updating and transferring the address via the trunk in the same way as in the case of the operation. Enter. In addition, the signal 75 Error through the element I-46 and the trigger 59 enters the signal 86 Forbid B, which enters the input of the element HE 43 and until the transmission of the address through the trunk and installation is transmitted: data on the pins 71 delays the appearance of the signal 87 Output I on output node 11;

Appearance 88 Output to. the output of the active module is preceded by the setting on the output tires of the gears. data. Therefore, until the adjustment of the address is completed, its value is read into the trunk with the register

 14

through node 11 and delay delay 26,

element AND 24 iji elements OR 15 signal 89 will be set. Conclusion M. The modules of the subsystems (there is one in each subsystem) are output to the signal 89: the IPS signal 83. Starting from this moment, the subsystem will normally be suspended due to a delay in the delay element 35 until the CIP signal from the module in the faulty subsystem appears. With its occurrence, the synchronization will occur in parallel with the operation of these subsystems.

In a faulty subsystem, as represented in FIG. 8, signal 87 The output I is based on the output of the node I1 after the removal of the signal 86 Disable B. At this time, the transmitted data is installed on the buses 71 of all the masters. Signal 87 The output of I through the element OR 12 generates a signal 74 Error gate. When a signal appears 75 An error from the voting block causes the switching of the shaping units 6 and 7 from the data correction on the buses 71. The signal, 87 Conclusion 1, which is delayed by the delay element .26 in the analysis of the erroneous situation, comes in this case through element 18 to the input of the delay element 28. The delay element 28 delays the signal Output I at the time of switching the drivers 6 and 7 and correcting the data on the tires 71. Then this signal from the output of the hold element 28 through the element OR 5 forms the trunk signal 89 Output M. Signal CIP 83 appears on signal 89, with the arrival of which subsynchronization takes place. At this point, a SIPG signal 84 is generated, which, through element 21 and element OR 16, causes the appearance of SIPA signal 85. The arrival at the input of the active module or processor signal 85 leads to the removal of the signal 88 Output and successive switching off of signals 87 Output I, 89 .; Conclusion M, cleared 75 Error, - return to normal condition of the formers 6, 7 and clearing of the signals 84 SIPG, 85 SIPA, 73 SIAG and 79 SIAM. On this backbone

is running out. Performing a backbone operation

 Conclusion

Input pause - output is a combination of the various stages of the operations Input and Output.8

0

five

25

0

thirty

i The time frame for the provision of direct memory access in the system under consideration differs from the standard exchange protocol only in that the control signals 90 Requirement, direct access (TFD), 91 Provision of direct access (TFD) and 92 Confirmation of Choice (PV a) pass through the corresponding synchronization nodes 10, where they are sub-synchronized and the formation of 93 TPDA, 94. PPDM and 95 PVA signals, which can be considered as analogs of the corresponding control signals; standard exchange protocol.

FIG. Figure 11 shows the timing of the program crash in the event of an error when generating the address of the interrupt vector.

The operation of the system in this case begins with the formation by the modules in the signal subsystems 96 of the Interrupt Requirement (TPD), which, passing through the synchronization node 10, causes the TPRA signal 97 to be input to the processor 3. Processor 3 satisfies the requirement by first generating an 80 Input signal, and then 98 Pre-Delivery Grant (RR). Signal 80 Input through the node 10, the element And 23 and the element OR 14 forms the signal 82 Input M, and the signal 98 RPS through the node 10 enters the signal 99 RTU.

In response to signals 82 and 99, modulates the signal 96 TPD and set the address of the interrupt vector on the tires 71, after which the signal g

al 83 CIP. The signal 83, having passed through the node 10, causes the appearance of the signal 84 of the STG, which through the element 17 and the element OR 12 forms the signal 74, the error gate. In response to the signal.

74 voting block 1 generates a signal 75 Error if the vector address is incorrectly set. By signal 75, the formers 6, 7 are switched and the address of the interrupt vector is corrected. The signal 75 permits the signal SIPG 84, delayed on the delay element 27, to pass through the element AND 20 to the input of the control element. . 29, where it is delayed by the time

necessary to adjust the address of the vector and then through the element OR 16 generates a SIPA signal 85, In response to the signal 85, processor 3 removes the signal 80 Input. After this, afterwards, 1457643 °,

Signals 82 are input. Input of the first formers of the i-th (, p) M, 75 Error is switched, switches to the normalized subsystem. The condition of the drivers 6, 7 is connected and the signals of 83 CIP, 8A are reset to SIPG, and 85 SIPA. the interrupt Bektopa adras transfer operation ends.

If all modules are computing

ten

Since systems are working, or are working, at least those modules that are involved in the exchange of information on a highway at a given point in time, then the exchange protocol is practically no different. It comes from a standard protocol. In this case, only rasynchronization of the trunk signals in the subsystems can be observed, caused by differences in the speed of signal propagation along the same type of electrical circuits. 20 Delay elements 35 and 40 at synchronization nodes 2 and 10 of synchronizers 2 will occur during each exchange cycle on the trunk. The operation of supporting subsystems in synchronism. In addition to TOGO), additional delays compared with the standard exchange protocol are necessary for analyzing an erroneous situation on the magistracy information inputs of the i-th group of voting blocks, in each reserve information subsystem the information outputs of the reservation are connected to the information inputs of the data address register, outputs of which connected to the inputs of the system main drivers block whose inputs / outputs through the bus of the address of the data of the reserved subsystem are connected to the inputs-outputs of the first groups of blocks master formers, active modules of the group, blocks of trunk drivers of naccHBfiix modules of the group and block of processors of trunk drivers, the output of the signal of the presence of an error of the voting unit is connected to the input of the signal of the presence of the error of the synchronizer, the input of the block of the main trunk formers , block of processor main drivers, blocks of main drivers of active modules of the group and blocks

25

AGD;} c./ ilv rii. y, .-к.ъ

LI. These delays are formed by the elements of the 30 main shapers by passivating the delays 25, 26 and 7.7 of the nasators 2,

synchronous modules of the group, the output of the sync pulse of a passive sync device is connected with the same inputs of the sync pulses of a passive

Claims (3)

Invention Formula I. Majority-redundant backbone modular computing system containing a clock generator and N redundant subsystems, where N is the redundancy ratio, each of the redundant subsystems contains a processor and a group of passive modules, the output of the clock generator is connected to the clock inputs of all processors, and It is necessary to expand the functionality by reserving the active modules, each subsystem contains a voting block, the address register is Block system of main generators, main processor block formers, a group of active modules. modules of the group, the output of the sync pulse of the passive device of the syncizer is connected with the same inputs of the sync pulses of the passive or devices of processors of active and passive modules, the outputs of the error gate signals, the input of the sync pulse of the active device and the output of the first group of the synchronizer are connected to 40 of the same inputs of the voting unit, the output of the clock signals of the active device, the input and output of the second group of the synchronizer are connected to the same inputs of the active 45 and passive modules, the output of the grant signal of the direct access of the donor is connected to the inputs of the provision of direct access of active modules, the output of providing the synchronization of the synchronizer is connected to the inputs of the provision of interruption of the passive modules, the output of the active generator, signal outputs a group of blocks of trunk form-55 active pulse pulses. active units of modules, a group of blocks of main drivers of passive modules and a synchronizer, with the outputs of the blocks of systemic magvvod, output, provision of interruption and provision of direct access to the processor and active; 1st modules. i-th (redundant subsystem splinter forks i-th (, p) redundant subsystem are connected 0 0 with the information inputs of the i-th group of voting blocks, in each backup gye foy subsystem the information outputs of the redundancy are connected to the information inputs of the data address register, the outputs of the kotor are connected to the inputs of the system main drivers unit whose inputs and outputs through the data address bus of the reserved Subsystems are connected to the inputs-outputs of the first groups of blocks of trunk forms. builders, active modules of the group, blocks of main drivers of naccHBfiix modules of the group and block of processors of main drivers, the output of the error signal of the voting block is connected to the input signal of the synchronizer error, the synchronization input of the data address register and the block of processor main drivers , blocks of main shapers of active modules of the group and blocks five main shapers of the passive modules of the group, the output of the sync pulse of the passive device sync. nizator connected with the same inputs of passive sync pulses devices of processors of active and passive modules, the outputs of the error gate signals, the input of the sync pulse of the active device and the output of the first synchronizer group are connected to with the same inputs of the voting unit, the output of the sync pulse signals of the active device, the input and output of the second synchronizer group are connected to the same inputs of the active and passive modules, the output signal of the direct access of the donor is connected to the inputs of the direct access of active modules, the output of the synchronizer interrupt is connected to the inputs of the interruption of the passive modules, the output of the active generator is connected to the clock of the active modules, the outputs of signals  with the pulse of active devices. input, output, provision of interruption and provision of direct access to the processor and active; 1st modules. i-th (redundant subsystem ten 15 20 25 combined and connected to the i-th resolution of the input groups, respectively, the sync pulses of the active devices, input, output, interrupt provision and direct access of all synchronizers, outputs of the direct access demand signals and confirmation of the choice of the active modules ( i "1, N) of the redundant subsystem is connected to the i-th bit of the input groups, respectively, of the signals of direct access and confirmation of the choice of all synchronizers, the outputs of the signals of the sync pulses of the passive device and the requirement of The i-th (, N) passive devices of the redundant subsystem are connected to the i-th inputs of the input groups of the sync pulse signals of the passive device and the requirement of interrupting respectively all synchronizers, outputs of direct access requirements, confirmation of the i-th synchronizer The redundant subsystem is connected respectively to the inputs of the direct access requirement, acknowledgment of the choice and the demand of the processor of the i-th redundant subsystem (, N).  2, The system in accordance with claim 1, 1 and 2, so that the synchronizer contains the synchronization node of the clock of the active module, the synchronization node of the input signals, the synchronization node of the output signals, the synchronization node of the clock pulses of the passive module direct access node, interrupt request signal synchronization node, interrupt supply signal synchronization node, direct access providing signal synchronization node, selection confirmation signal synchronization node, five elements OR, eight elements AND, five delay elements, two elements NOT and a node fo1 111rova-go g  35 thirty 40 45  35 of the third. Elements and node form. neither the delayed control of their signals, the first input of the second element AND of the node for generating delayed control signals and the inputs of the first delay element and the first element of the node for forming delayed control signals; the input group of the synchronizer input signals is connected to the inputs of the synchronization node of the input signals whose output is connected with signal output. input of the first group of outputs of the synchronizer, the third input of the fourth element And the node of the formation of delayed control signals and the input of the second element the delay of the node forming the delayed control signals, the first input of the first element I, the output of which is connected to the third one of the delayed control signals; a catch that contains four triggers pa, three elements NOT, five, And elements and four elements of the delay element, in the node forming the delayed control of the first house OR element, the output of the output signals of the first element is connected to the output of the delay signal connected to the first synchronizer error terminal , the group element I, the output of which the co-pa of the input signals of the output signals is synchronized with the input of the installation in the unit of the unit. 0 five 0 five go The first trigger, the output of the second element And is connected to the installation input, into the unit of the second trigger, the output the first element is NOT connected to the installation inputs to zero of the first and second triggers, the output of the second element is NOT connected to the first input of the third element I, the output of the second element and the delay through the third element is NOT connected to the installation input to zero of the third trigger, the output of the first trigger is connected to the first inputs of the fourth and fifth elements And the inputs of the third and fourth delay elements, the output of the third delay element connected to the second input of the fourth element And the output of which is connected to the input of the unit in unit t retrigger trigger, odd output; the right delay element is connected to the second input of the fifth element I, the output of which is connected to the installation input to zero, the fourth trigger, the installation input unit of which is prepared by the keys to the output of the third element I, -, the synchronization pulse signal input group of the synchronizer active device sync pulses of an akTHB module, the output of which is connected to the first input of the first OR element and connected via the first delay element to the second inputs of the first and 5 of the third. Elements and node form. neither the delayed control of their signals, the first input of the second element AND of the node for generating delayed control signals and the inputs of the first delay element and the first element of the node for forming delayed control signals; the input group of the synchronizer input signals is connected to the inputs of the synchronization node of the input signals whose output is connected with signal output. input of the first group of outputs of the synchronizer, the third input of the fourth element And the node of the formation of delayed control signals and the input of the second element the delay node of the formation of the delayed control signals, the first input of the first element And, the output of which is connected to the third input 0 45 gg is the house of the first OR element, the output of which is connected to the output of the synchronizer error gate signal, the group of inputs of the synchronizer output signals is connected to the information 13 ten 15 20 25 the inputs of the signal synchronization node, the output whose output is connected to: the third input of the first element OR, the signal output, the output of the first group of outputs of the synchronizer, the input of the second element NOT of the generating unit for delayed control signals, and through the second delay element connected to the first input of the second element And, the group the inputs of the sync pulses of the passive synchronizer device are connected to the inputs of the synchronization node of the sync) pulses of the passive module, whose output is connected to the BTopbiM input of the first element And, through the third delay element is connected to the first inputs of the third and fourth elements And, as well as the first input of the fifth element R, the error signal input of the synchronizer is connected to the third inputs of the first and third elements And the node forming the delayed control signals, the second input of the second an item. And the node forming the delayed control signals, the second inputs of the third and fourth elements AND, the input of the first element NOT, the output of the first delay element is connected to the first input of the sixth element AND, the output of which is connected to the first input of the second ISh, whose output is connected to the output of the sync pulse In the active device, the second rpyn-Lz py synchronizer outputs, the output of the second trigger of the node generating delayed control signals through the second element is NOT connected to the second input of the sixth And element and the first, Q in one of the seventh AND element, the output of which is connected to the first input of the third element OR, the output of which is connected to the signal output, input of the second group of synchronizer outputs, the second input of the sixth AND element connected to the output of the output signals synchronization node, the output of the first signal terminal is NOT connected to the second the input of the third element And the first input of the eighth element And, the output of which is connected to the first input of the fourth - the element OR, the output of which is connected to the second input of the fifth element And and the output of the signal of the second group rows synchronizer second-output AND element via a fourth delay element coupled to a second input of the fourth OR gate, the output thirty 45 50 delay element is connected to ten 15 20 25 z, Q thirty 45 0 the second input of the eighth element AND, the output of the third element AND is connected by the first input of the fifth element OR, the output of which is connected to the clock outputs of the passive device of the second group of synchronizer outputs, the output of the fourth element I through the fifth element of the fifth element OR, the third input of which is connected to the output of the fifth element AND, the output of the first trigger of the node for the formation of delayed control pulses is connected to the second input of the second IP element and the output of the sync pulse the module of the first group of outputs of the synchronizer, the output of the third and fourth triggers of the node for the formation of delayed control signals are connected respectively to the second, the input of the third element OR and the prohibitance input of the output signals synchronization loop, the input group of the direct access request of the synchronizer is connected to the inputs of the synchronization node of the direct access request signals, the output of which is connected to the output of the direct access of the synchronizer, the input signal of the synchronizer providing direct access connected to the inputs of the node synchronization signals of the direct access, the output of which is connected to the output of the signal of the direct access synchronization To the torus, the group of inputs of the synchronizer interrupt provision signals is connected to the inputs of the synchronization node of the interrupt provision signals, the output of which is connected to the output of the synchronizer provide signals, the group of inputs of the synchronizer selection confirmation signals is connected to the inputs of the synchronization node of the selection signals, the output of which is connected to the output of the synchronous signal Nala. Confirmation of the choice of the synchronizer. 3. The system of claim 1, wherein the unit is a voice; The NIN contains M voting signals, where M is the width of the addresses of the data of the reserved subnetwork, trigger, two elements of the SP, two elements of AND, three elements of N., two delay elements, and the jth bit of the i-th group W.1 information x1gx entering the block of connectors with the 1st input of the j-th voting element (il.Nj. j-Py), the information output of the j-th voting element is connected to the j-th bit of the information outputs of the block ( jl, M), the outputs of the error signal of the voting elements are connected to the inputs of the first OR element, the output of which is connected to the information input igger. The output of which is connected to the output of the error signal of the block, the input of the gate of the error of the block is connected to the synchronization input of the trigger, the input signal of the sync pulse of the active device connecting to the first input of the first element I and through the first delay element f (t.f connected to the second input of the first element AND, the output of which is connected to the first input of the second element OR, the output of which is connected to the first input of the second element AND whose output is connected to the input of setting the trigger to zero, the signal input block input through the first element is NOT connected to the second input the second element OR, the signal input block output through the second element is NOT connected to the third input of the second OR element, the output of which is connected to the input of the third element NOT, whose output is connected to the second input through the second delay element House second element I. 75, n, g3, k, s9 9 {itt .77 tft. ig.5 FIG. 7 Fi, c. 6 NE 74- 75 ig.v Y j (///// mk J Thebes. 9 . Ui FIG. ten .AND