SU1509916A1 - User to computer interface - Google Patents

Abstract

The invention relates to computing and can be used to build computing systems based on multiplexed serial channels. The purpose of the invention is to increase the reliability of information transmission due to the hardware monitoring of the state of a computer channel trunk. The device contains an amplifier-receiver, amplifier-transmitter, coder, decoder, pulse generator, three switches, two registers, shift register, two triggers, three delay elements, two OR elements, AND element and NAND element. 1 il.

Description

The invention relates to computing and can be used to build computing systems based on multiplexed serial channels.

The purpose of the invention is to increase the reliability of information transmission due to hardware control of the main line of the computer channel.

The drawing shows a block diagram of the device.

The device contains amplifier-receiver 1, decoder 2, register 3, element OR 4, delay element 5, element OR 6, pulse generator 7, delay elements 8 and 9, shift register 10, register 11, switches 12-14, triggers 15 and 16, the element AND-NOT 17, the element And 18, the amplifier-transmitter 19, the encoder 20, the inputs 21 and the output 22 of the serial channel, the input 23 of the selection of the mode of operation, the input 24 of the encoder, the input 25 of the choice

type of transmitted word, outputs-26 and inputs 27 of the parallel channel.

The decoder 2 has information inputs 28, strobe output 29, information output 30, output 3 of the word presence feature, synchronization input 32 and output 33 Data / command.

Encoder 20 has a start input 34, a data / command input 35, an information input 36, a synchronization input 37, a word transmission feature output 38, a synchronization output 39, and information outputs 40.

Amplifier receiver 1 serves to match the levels of the signals from input 21 to inputs 28 of the decoder. The decoder 2 provides verification of incoming information to the inputs 28 for compliance with the code used, converts the signals at the inputs 28, which are received in a paraphase code into a serial code at the output 30,

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generates a signal at output 29, accompanying each output bit, determines the type of the incoming word ((service, informational). The decoder 2 can be implemented using a 588VGZ chip,

Register 3 serves to convert the serial code at the output 30 of the decoder 2 into the output parallel code. The element OR 4 serves to determine whether there is a transmission of information in the channel. Element 5 of the delay eliminates the false appearance of a signal indicating the absence of information transmission in the channel when the time error of the para-phase signals in the channel. The element OR 6 provides the formation of a signal about the absence of transmission in the channel, taking into account the possible temporal discrepancy of signals in the channel. The pulse generator 7 generates a sequence of signals synchronizing the operation of decoder 2 and encoder 20. Delay element 8 serves to delay the transmission of the output signal; 3 decoder 2 through switch I3 to the input of encoder 20 relative to the signal at output 33 of decoder 2. Element 9 delay provides a delay in the transmission of the output 30 of the decoder 2 to the input 36 of the encoder 20 at the time generated by the clock encoder 20. The shift register 10 converts the parallel code from the output of the register 11 into a serial code, transmitting it es switch 14 to the input 36 of the encoder 20. The register 11 serves to store ochered- Nogo transmitted word. The switch 12 provides a signal transfer to the synchronous input of the trigger 15 from the output of the decoder 2 or from the input 25 of the device depending on the signal at the input 23 of the device. The switch 13 serves to transmit a signal to the synchronous input of the trigger 16 from the output 31 of the decoder 2 via the delay element 8 or from the output 24 of the device depending on the signal at the input 23 of the device. The switch 14 serves to transmit a signal to the input 36 of the encoder 20 from the output 30 of the decoder 2 through the delay element 9 or from the output of the register 10, depending on the signal at the output 23 of the device. Triggers 15 and 16 provide for storing signals at the outputs of switches 12 and 13. AND-N17 element serves

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to generate a start blocking signal for the encoder 20. Element And 18 blocks the triggering of the encoder 20 in the presence of information on the channel.

Amplifier transmitter 19 provides matching of the levels of the signals at the outputs 40 20 and the outputs 22 of the device. Encoder 20 converts the serial code at input 36 into the output paraphase code at outputs 40, generates, depending on the signals at input 35, output signals of a certain type (service, informational), generates a word transmission feature, signals that synchronize the transmission of information bits. Inputs 21 and outputs 22 provide a connection to the main lines of the channel. The inputs 24 and 25 of the device are given signals that determine the start of the encoder 20 and the type of trigger word, respectively. The outputs 26 and the inputs 27 of the device are used to connect a parallel channel.

The operation of the device is carried out in two modes Exchange and Retransmission. Mode selection is determined by the signal at input 23 of the device.

In the Relay mode, using the signal at the device input 23, output 33 of decoder 2 is connected to the synchronous input of trigger 15, output 31 of decoder 2 via delay element 8 and switch 13 to the synchronous input of trigger 16, output 30 of decoder 2 via delay element 9 and switch 14 to the output 36 of the encoder 20, In addition, signal transmission through the AND-HE element 17 is blocked by this signal.

In the Exchange mode, in accordance with the signal at input 23 of the device, the input 25 of the device is connected via switch 12 to the synchronous input of the trigger 15, input 24 via the switch 13 to the synchronous input of the trigger 16, and the output of the register 10 via the switch 14 to input 36 of the encoder 20.

In the Exchange mode, the inputs 21 and the outputs 22 of the device are connected to a single trunk line. When receiving from the channel, the data in the bipolar phase-controlled paraphase code is fed to the inputs 21 of the device and then to the inputs of the amplifier-receiver 1, using the amplifier-receiver 1, the levels are converted

incoming information to standard levels of logic signals. From the output of the amplifier-receiver 1, the information is fed to the inputs of the element OR 4 and to the information inputs 28 of the decoder 2, the Decoder 2 checks for the correctness of the encoding of the received information and, if it is recognized as reliable, generates a signal at the output 31 indicating the arrival of a valid word, and output 33 is a signal that identifies the incoming word as informational or service, depending on the type of clock in the received word. From the output 31 of the decoder 2, the signal goes to the input of the register 3, allowing reception m in it information. Then

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In the code and at any time, at least one output of the amplifier-receiver 1 contains a single signal. As a result, a single signal is generated at the output of the OR 4 element for the period of the presence of the information parcel in the trunk of the channel (device inputs 27). A single signal from the output of the OR 4 element arrives at one of the inputs of the OR element 6, causing a single signal at its output signal. In addition, from the output of the element OR 4, the signal is fed to the input of the element 5 delay and from its output to the other input of the element OR 6, the signal from the output OR 6 is fed to the input of the element AND NOT 17, After installing the trigger 15 at the output of the

as information appears on the IS-17 output, if there is a transfer

De 30 of the decoder 2 is carried out over-information in the trunk is formed

writing it with a shift to register 3 is a zero signal, from the output of the element

to the rising edge of the signals coming in AND-NOT 17 the zero signal arrives at

from output 29 of decoder 2. Element I 18, blocking, at the reception of the last bit, a block is received at its trigger output

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The signal from the output 31 of decoder 2 is removed and the recording of information in register 3 is stopped. Thus, at the outputs of register 3 there is a parallel code received from the AOR channel of a word, arriving at the outputs 26 of the device. Subsequent words from the channel are received in the same way.

During the transmission, the transmitted information is preliminarily entered from the device inputs 27 into the register 11. Next, a signal defining the type of the transmitted word (service, information) is set at the device input 25. If the dd transmission of the overhead word is performed, then on the leading edge of the signal from the input 25, coming through the switch 12 to the synchronization code of the trigger 15, this trigger is set. Then 45 to the input 24 is given a start signal transmission word, on the leading edge of which is the installation of the trigger 16. The signal from the output of the trigger 15 is fed to the one of the inputs 50 of the element I-E 17, If at the start of the transfer service input (for example, command response), transmitted at the beginning of the array in the form of a cap, on the trunk there is a false transmission of information due to the failure of one of the channel devices, then the outputs of the amplifier-receiver 1 generate information in the paraphase

transfer.

Thus, if there is a false transmission of information of the channel backbone and, if necessary, the transfer of a service word (trigger 15 is set), for example, which is an array header, the start of transmission of this word to the channel backbone is blocked. Since the word is not transmitted to the trunk, then the output 38 of the encoder 20 contains a zero signal and the flip-flop triggers 15 and 16, and no new information is written to the register 10. After the termination of the false transmission to the trunk at the outputs 28 of the amplifier-receiver 1, a single signal is removed. At the output of the OR 4 element, a zero signal is formed, which is fed to the input of the OR 6 element and the input of the delay element 5. After a time delay on the element 5, a zero signal is generated at its output, which arrives at the input of the element OR 6 ,. At the output of the element OR 6, a zero signal appears, which arrives at the input of the element AND-NOT 17. At the output of the element AND-NOT 17, a single signal is formed, which arrives at the input of the element And 18, When the trigger 16 is set, the output of the element And 18 appears a single trigger signal arriving at the input 34 of the encoder 20, At the outputs 40 of the encoder 20, a sync pulse is generated in the para-phase code,

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transfer.

Thus, if there is a false transmission of information of the channel backbone and, if necessary, the transfer of a service word (trigger 15 is set), for example, which is an array header, the start of transmission of this word to the channel backbone is blocked. Since the word is not transmitted to the trunk, then the output 38 of the encoder 20 contains a zero signal and the flip-flop triggers 15 and 16, and no new information is written to the register 10. After the termination of the false transmission to the trunk at the outputs 28 of the amplifier-receiver 1, a single signal is removed. At the output of the OR 4 element, a zero signal is formed, which is fed to the input of the OR 6 element and the input of the delay element 5. After a time delay on the element 5, a zero signal is generated at its output, which arrives at the input of the element OR 6 ,. At the output of the element OR 6, a zero signal appears, which arrives at the input of the element AND-NOT 17. At the output of the element AND-NOT 17, a single signal is formed, which arrives at the input of the element And 18, When the trigger 16 is set, the output of the element And 18 appears a single trigger signal arriving at the input 34 of the encoder 20, At the outputs 40 of the encoder 20, a sync pulse is generated in the para-phase code,

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stepping on the inputs of the amplifier-transmitter 19 and, further, in the bipolar phase-shift keyed code to the outputs 22 of the device. After the sync pulse shaping has been completed, a single signal arrives at the output of the encoder 38 and enters the register 10. The signals from the output 39 of the encoder 20 indicate that the transfer of the next bit is completed, the information in the register 10 is shifted The 10 regular bit of information is fed through the switch 14 to the input 36 of the encoder 20. After the last bit is transmitted, the signal at the output 38 of the encoder 20 is reset. On the trailing edge of this signal, the triggers 15 and 16 are reset, and the next information word, previously entered in register 11, is recorded in register 10, then a signal defining the type of the transmitted word is set at input 25, and a trigger signal is fed to device 24 When transmitting the information word at the input 25, there is a zero signal and the installation of the trigger 15 is absent. The zero signal from the output of the trigger 15 blocks the transmission of the signal from the output of the element IS-NOT 17 to the input of the element 18, Thus, after the transmission of information from the jcTBa device (transmission of the service word) starts, the transmission delay of the next words of the transmitted array is blocked.

If the edges of the paraphase code do not coincide, the outputs of the amplifier-receiver 1 due to the time difference of the signals at the inputs 21 at the output of the OR 4 element may result in a zero signal. However, the output of element 5 is supported by a single signal, therefore, at the output of element OR 6: a single signal is also supported. The delay time interval on the element 5 is selected taking into account the maximum possible time difference of the signals at the inputs 21 of the device.

In the Relay mode, a zero signal is applied to the input 23 of the device, blocking the left signal at the output of the NAND 17 element, as well as connecting the output 33 of decoder 2 via switch 12 to the sync input of the trigger 15, output 31 of decoder 2 through the delay element 8 and the switch 13 to the trigger 168 synchronous input

16, output 30 through delay element 9 and switch 14 to output 36 of encoder 20. In this mode, inputs 21 and outputs 22 of the device are connected to different trunk lines,

From the inputs 21, the information is fed to the inputs of the amplifier-receiver I and from its outputs to the inputs 28 of the decoder 2. In accordance with what was described with the correctness of the received information code, a single signal appears at the output 31 of the decoder 2. In addition, at the same time, at output 33 of decoder 2, depending on the type of incoming word (service, informational), a corresponding signal is generated that arrives at the input of switch 12 and from its output at the synchronous input of trigger 15 If the received word is service, at output 33 of decoder 2 through is a single signal, on the edge of which the trigger 15 is set; From the trigger output 15, the signal arrives at the input 35 of the encoder 20; the type of output word is determined; From the output 31, the signal arrives at the input 8 delay element, from which 12 es the switch - on. the trigger trigger 16, As a result, the trigger 16 is set to one. At its output, a signal arrives at the input of an element AND 18, at the other input of which there is a single signal. At the output of the element 18, a signal is generated, on the leading edge of which the encoder 20 is started. At the outputs 40 of the encoder 20, signals appear corresponding to the paraphase clock code determined by the signal at input 35 of the encoder 20. From the outputs 40 of the encoder 20 are formed. Signals are fed to the amplification inputs. l -transmitters 19 and from its outputs through the outputs of the device 22 to the highway. As the information bits appear at the output 30 of the decoder 2, they are transmitted to the input of the delay element 9 and from its output through the switch 14 to the input 36 of the encoder 20. The delay time interval on the element 9 is selected taking into account the timing of the formation of the sync pulse by the encoder 20. After receiving The last bit of information from the input 31 of decoder 2 is removed. After the last bit is transmitted, the signal at the output 38 of the encoder 20 is removed. Back to front 1

The signal from output 38 of encoder 20 triggers 15 and 16 are reset. Further operation of the device is carried out as described.

Claims (1)

Invention Formula A device for interfacing a subscriber with a computer containing an encoder, a decoder, two registers, a shift register, the first switch, the information output of the first register and the information input of the second register being the output and input of the device for connecting respectively the information input and the information output the first information input of the first switch is connected to the Data / decoder command output, the output of the word presence indication, the information output and the gate output of which are connected with the recording input, with the information input and with the sync input of the first register, the information output of the second register is connected with the information input of the shift register, the sync input and the recording input of which are connected respectively with the synchro pass and with the output of the transfer sign of the coder word, which differs from , in order to increase the reliability of information transmission due to the hardware monitoring of the state of the main line of the computer channel, the amplifier-receiver, amplifier-transmitter, pulse generator, two switches are entered into the device, two triggers, three delay elements, two OR elements, the AND element, the NAND element, the information inputs of the amplifier receiver and the information outputs of the transmitter amplifier are the inputs and outputs of the device for connecting respectively to the information channels of the computer channel, the first input of the element NAND is connected to the first, second control inputs of the first, second, and third switches and is the input to the device's mode selection, the second information input ten 15 AND 0991610 the first switch and the first information input of the second switch are the word selection input and the device start input, the first and second information outputs of the amplifier receiver being connected to the first, second information inputs of the decoder and to the first, second inputs of the first OR element whose output is connected to the first the input of the second OR element and the input of the first delay element, the output of which is connected to the second input of the second OR element, the output of which is connected to the second input of the NAND element, the output of which is connected Inen with the first input element And, the output of which is connected to the input of the start of the encoder, the input Data 20 / command which is connected to the third input of the NAND element and the output of the first trigger, the zero input of which is connected to the zero input of the second, the trigger and the output of the sign of the word transfer of the encoder, the synchronous input of which is connected to the synchronous input of the pulse generator and the synchronous input of the decoder, the output of the presence of the word and information output connected to the inputs of the second and third -. respectively, the outputs of which are connected to the second information input of the second switch and the first information input of the third switch, respectively, the first, second information inputs of the amplifier-transmitter, are connected to the first, second information outputs of the encoder, respectively, in-. The formation input of which is connected to the information output of the third switch, the second information input of which is connected to the information output of the shift register, the second Another element input is connected to the output of the second trigger, the information outputs of the first, second switches are connected to the synchronous inputs of the first and second triggers, respectively, and the 50 inputs of which are connected to the unit potential bus. thirty 35 "Sj Gssj