SU1269174A1 - Information transmission-reception device - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital systems and networks. The invention improves noise immunity compared to devices using the HDLC communication procedure. On the transmitting side of the device, a 16-bit frame sync group 0010101011C 10101 is formed with a root portion including the first 13 bits and a suffix comprising the last three bits. The transmitted data is formed by the source in frames of N bits each, and the frame-group distinguishes between the beginning and end of each frame. The data sequence may include any bit configuration. To prevent erroneous identification by the frame sync group on the receiving side, the transmitting side analyzes their contents and inserts additional bits if the data sequence completely coincides with the root part of the frame sync group or differs from it by one or two bits. The receiver side removes the extra bits and recovers the transmitted data. The device contains on the transmitting side an information source. (Latsii, delay unit, comparison unit, comparison result analyzer, bitstaffing clock, synchronizer, OR element, sync group generator and register, communication channel and receiving side - sync group analyzer, delay unit, memory block, comparison unit, result analyzer Comparison, Bitstaffing Chroniser, Synchronizer and Information Receiver. 3 Cp f-crystals, 10 ill.

Description

The invention relates to telecommunications and can be used in digital systems and networks.

The purpose of the invention is to improve the noise immunity of the device.

Figure 1 shows the block diagram of the device; in fig. 2 is a diagram of the process of forging personnel dressing; FIG. 3 shows a functional circuit of the delay unit, the comparator unit and the memory unit; 4 is a functional diagram of the comparison result analyzer; FIG. 3 shows timing diagrams explaining the operation of the comparison result anapizator} in FIG. 6 is a functional diagram of a pulse generator, a frequency divider and a bitstaffing chroniser; FIG. 7 shows timing charts that explain the funktion of the chronization of a bitstaffing; FIG. 8 shows a functional diagram of a register, an OR element, and a synchro generator; figure 9 is a functional diagram of the analyzer sync; Fig. 10 is a diagram of the process of forming a frame burst in the base object.

The device for transmitting and receiving information (Fig. 1) contains on the transmitter side 1 an information source 2, a delay unit 3, a memory unit 4, a comparison unit 5, a result analyzer 6, a comparison, a beatstaffing clock 7, a synchronizer 8 executed on the generator 9 pulses and frequency divider 10, element OR 11, sync group generator 12 and register 13, communication channel 14 and on receiving side 15 - synchrogram analyzer 16, delay block 17, memory block 18, comparison block 19, comparison result analyzer 20, chroniser 21 bitstaffing, synchronizer 22, run The generator has 23 pulses and a frequency divider 24, and information receiver 25.

Delay unit 3 (FIG. 3) contains an OR element 26 and a register 27. Memory unit 4 contains two-input elements AND 28. Comparison unit 5 contains adders 29 modulo two.

The analyzer 6 of the comparison result (FIG. 4) contains a register 30, an AND 31 element, a counter 32 and a decoder 32.

The generator 9 pulses (fig.b) contains the elements AND-NOT 34-37 i capacitor 38. The frequency divider 10 contains the counter 39 and the element 40. The hro-sizer 7 of bitstafing contains the counters 41 - 43 pulses, triggers 4446, the elements And 47 - 51 and the element OR 52. The synchro generator 12 (FIG. 8) contains an AND 53 element and a register 54.

The synchro-analyzer 16 (FIG. 9 contains the register 55, the element NOT 56, the elements AND 57-60 and the element OR 61,

The operation of the device is explained by the scheme (Fig.2). On the transmitting side 1, a 16-bit frame sync group 0010101011010101 is formed with a root part including the first 13 bits 0010101011010 and a suffix that includes the last three bits 101 (fig.2Q). Data transmitted from source 2 to receiver 25 over communication channel 14 is generated by source 2 into frames of N bits each (FIG. 2 S), the frame sync group delimits the beginning and end of each frame (FIG. 2 g),

The data sequence may include any bit configuration and in order to prevent erroneous identification of the frame sync group on the receiving side 15, the following rules apply to all contents of the data bursts: the transmitting side 1 analyzes the contents of the data and inserts three bits before transmitting the data. 010 (inverse to the frame sync pattern suffix) directly after each series of 13 bits, completely coinciding with the root part of the frame sync group, or inserts two bits 01 directly After each series of 13 bits that differ only in one position from the root part of the frame sync group, or inserts one bit O immediately after each series of 13 bits, differing only in two positions from the root part of the frame sync group (Fig. 2)); the receiving side 15 analyzes the contents of the received parcels (FIG. 20) and removes three bits 010 that immediately follow a series of 13 bits completely coinciding with the root 4acTbKf frame sync group, or removes two bits 01 that immediately follow the series from 13 bits, differing only in one position from the root part of the frame sync. groups, or beats; 1, one bit O, which immediately follows a series that differs only in two positions

days x from the root of the Ka; ipo5iO i synchro group (F1P.2e).

The device works as follows.

On the transmitting side 1, the source 2 generates data in frames of N bits in each and the sign of the frame (second output), which starts the generator 12 of the sync group. The generator 12 of the sync group is transmitted through the element OR 11 into the channel 14 of the communication sequence 0010101011010101 with a speed determined by the clock frequency F, produced by the frequency divider 10. Then, source 2 turns off the sign of the beginning of the frame, and data from source 2 (first output) with a speed, also determined by the clock F, which is controlled by the beatstaffing synchronizer 7, is simultaneously received at the input of the delay unit 3 by 13 bits and through the OR 11 - to communication channel 14. The contents of block 3 delays with each clock of frequency Ff is shifted by one bit: the oldest bit itself arrives at the 13th bit, and the new bit from source 2 is written to the first bit. Then the contents of block 3 of delay are compared bit by bit in the block 5 comparisons with the contents of memory block 4, which stores the constant 0010101011010, which is the root part of the frame sync group. The analyzer 6 of the comparison result produces one of three signs:

the contents of the delay block 3 coincide in all positions with the contents of the memory block 4 (the first output) and instead of the next three data bits it is necessary to send three bits of the insert 010 to the communication channel 1–4;

the contents of delay unit 3 are different in one position from the contents of memory unit 4 (second output) and instead of the next two data bits, two insert 01 bits must be sent to communication channel 14;

the contents of delay unit 3 are different in two positions from the contents of memory unit 4 (third output) and instead of the next data bit, one insert bit 0 should be sent to communication channel 14.

The absence of signs on all three outputs of the analyzer 6 of the comparison result signals that the contents of the delay block 3 differs from the root of the frame sync group in more than two nosHiyi x, and the operative of the blocking is prohibited. The speed of the analyzer 6 of the comparison result is determined by the frequency K 16P generator 9 pulses, so that during the period of the clock frequency, the analyzer 6 has time to fully process the result of a bitwise comparison of the current data block with the root part of the frame sync group.

Depending on the result of the comparison, the clock generator 7 bitstaffing (first output) prohibits the arrival at the source 2 of three, two or one impulses. The contact frequency P, which prohibits the occurrence at the output of the source 2 of the next three, two or one data bits. At the same time, according to the result of the same comparison, the chronizator 7 of bitstaffing (the second output) permits receipt of three, two or one shifting pulses synchronous with the clock frequency P. to the insert register 13. This ensures synchronization in time of the operation of the bitstaffing with the operation of the source 2.

From the output of the register 13, the insertion bits 010,01.0 arrive through the OR element 11 into the communication channel 14 and simultaneously to the second input of the delay unit 3, since for - proper execution of the beatstaffing operation it is necessary that the insertion bits also participate in the analysis along with the bits data. Since the data from the output of source 2 is not received during the bitstaffing operation, the insertion bits 010, 01, O unhindered shift the series of data contained in block 3 of the delay, respectively three, two or one bit and take part in further analysis on coincidence with the root part of the frame sync group.

To restore the initial state 010 of register 13 after each bitstaffing operation, the bitstaffing synchronizer 7 outputs the write signal (third output), which goes to register 13 before shifting three bits when inserting bits 010, or before shifting two bits when inserting bits 01 , or before shifting one bit when inserting bit 0.

Thus, all data generated by source 2 into a frame, successively, bit by bit, is analyzed on the transmitting side 1 of the device for the presence of series matching the root part of the Frame Synchronization Group or different from it in one or two positions; and x, and then encoded by inserting bits O, 01 or 010 TdK, which in the data frame coming into channel 14 cannot find a single series of 16 bits that would differ from the frame sync in less than three positions. At the end of the data frame transmission, source 2 generates a sign of the end of the frame, similar to the beginning of the frame (second output), which also starts the synchronization generator 12, and the syncro closing data frame 0010101011010101 enters through the OR element 11 into the communication channel 14. From communication channel 14, the frame message, framed by sync groups 0010101011010101, arrives at the receiving side 15 of the device at the input of the analyzer 16 of the synchronization group, where it is delayed by three bits, and then at the input of the delay block 17. Blocks 3-10 of the receiving side operate similarly to blocks 17-24 of the transmitting side 1 of the device. With the arrival of the 16th bit from channel 14, the last three bits are in the sync group 16 analyzer, and the first 13 bits are in the delay block 17, and if they completely coincide with the root part of the frame sync group or differ from it in no more than two positions, then a comparison result appears at one of the outputs of the analyzer 20. At the same time, the synchronization group va / lizator 16 analyzes the last three bits for their corresponding suffix 101 syn. hrogruppy. If the result of such an analysis is positive, and one of the three outputs of the analyzer 20 compares the result to the sync group analyzer 16 sign of comparison, then the sync group analyzer 16 detects the start of frame signal, which is fed to the input of the receiver 25 and serves as a resolution for data reception. Similarly, the analysis of the sync group closing data frame is performed, and the sync group analyzer 16 generates a frame termination signal. which arrives at the same entrance. receiver 25 and serves as a prohibition for receiving data. After 16 clock cycles of frequency F after the start of the receive-frame sync group, nick 25 begins to receive data that is received at its input from communication channel 14 through the synchro-group analyzer 16 and delay unit 17. The bitstaffing timer 21 controls the clock frequency F supplied to the input of the delay unit 17 and the input of the receiver 25. The operation of deleting the bits inserted during transmission is as follows. If after comparing in block 19 a regular data series of 13 bits located in delay block 17 with the root part of the frame sync group stored in memory block 18, the comparison result analyzer 20 produces a sign on one of its three outputs, then chronizator 21 bitstafing excludes three, two or one pulse of the clock frequency FT, which prohibits the reception of three, two or one data bits respectively by the receiver 25 and simultaneously prohibits the promotion of the data series in the delay block 17, therefore coming from link 14 on one delay unit three, two or one insertion bits are lost. The delay unit 3 (Fig. 3) is implemented on a 13-bit universal register 27. In a sequential mode of operation (shift mode) information is fed to the input, U1, synchronization is performed on the input C1 . positive polarity pulses; the inputs V2, C2 - levels of logical O (ie, the potential of Zempi). Memory unit 4 (FIG. 3) is implemented on 13 two-input elements AND 28. The combined inputs of the elements are continuously supplied with either the ground potential (level, logical O) or the positive potential of the power source (logic level 1). At the outputs of the And 28 elements, a permanent code is established corresponding to the core part of the frame sync group. The comparison block 5 (FIG. 3) is implemented on 13 adders 29 modulo 2. At the first input of each adder 29, the data bit d is applied (c, and the second

Its input is the corresponding bit of the CK constant. With d c at the output of the adder 29, the logic level is O, with d f Cj, is the logic level 1. Thus, with each frequency F, the number of units at the thirteen outputs of block 5 determines the number of mismatched positions in the next data series.

The analyzer 6 of the comparison result (FIG. 4) is implemented on universal register 30, element 31, counter 32 modulo 4 and decoder 33 2 X 4. Logical 1 from those adders 29 modulo 2 blocks arrive at information inputs D1-D13 of register 30 3, where the corresponding bits of data and constants do not match. In para- cel operation mode (Number Record mode) of register 30 VI O, C1 0; V2 1, C2 1, i.e. synchronization is performed at input C2 and with each clock of frequency F. Information on D1-D13 is recorded in register 30 and appears at its corresponding parallel outputs 1-13. The information is then shifted by the frequency Fpy 16-F (synchronization C2) and for thirteen clock cycles Fp is received already in a sequential code from the output of the 13th digit of the register 30 through the element 31 to the counting input T of the counter 32. The counted number of units N is decoded by the decoder 33 , so if N O, then 1 appears at the first output, if N 1, then at the second output, if N 2, then at the third output, if, then at the fourth output there appears 1, which blocks the input of the counter 32 Each clock of frequency F is set to O of counter 32. In FIG. 5, time diagrams are shown. Ranma the analyzer 6, the comparison result for the case where the logic levels present on input D2 and D3 of register 30. Diagram A, 5 show the ratio of the clock generator 9 and the pulse frequency. Diagrams B, 2 show the recording of units in register 30, and - the promotion of these signals in register 30. Diagram e shows the signals at the inputs of counter 32, and from, at its outputs. The diagrams of and, k, l, mn do explain the operation of the decoder 33 for this case.

Timer 7 bitstaffing (6) is implemented on three counters: 41

1748

(divider chatota by 2), 42 (divider by 3) and 43 (divider by 4), three RS-flip-flops 44-46, elements AND 4751 and element OR 52. Counter 41 trigger 44 and element 47 form a temporary Window, including a single frequency pulse F, if input 1 receives a sign (logical 1) from analyzer 6 of the result of comparing full match d; сj..The counter 42, the trigger 45 and the element And 48 form a temporary Window that includes two pulses of frequency F, if n input 2 receives a sign of difference d ,, i J, 13 from cj, i 1,1J in one position. The counter 43, the trigger 46 and the element And 49 form a time window comprising three FT-frequency pulses, if input 3 receives a sign that the difference is djV, i 1.13 from, i 1.13 in two positions. These signals, combined by the OR element 52, are used as sync signals shifting the register of 13 bitstaffing.

Element And 50 forms the Record signal for register 13, and Element 51 forms a temporary Window to prohibit the passage of one, two or three pulses of frequency F, which is used on the transmitting side 1 of the device to prohibit transmission for the time of a bitstaffing operation, and on the receiving side 15 - to remove the inserted bits and prohibit reception at this time. Fig. 7 shows timing diagrams for explaining the operation of the bit-stamping clock 7 for the case when; logical 1 is present at input 2.

Register 13 insert bits (Fig.8) is implemented on a three-bit single universal register. At the inputs D1-D3, the constant 010 is always present and it is written into the register 13 before each shift operation on the inputs C2, V 2 by the signal from the synchronizer 7 of beatstaffing. Reading the bits of the 010 or 01, or O from the output of the third bit of the register 13 is carried out by pulses supplied to the input C1 also from the synchronizer 7 bitstaffing.

Claims (4)

The sync group generator 12 (FIG. 8) is implemented on universal register 54. The frame sync group code is written to the V2, C2 inputs with the Start-end frame signal of the polarity from the information source 2. The information is read out (and in a sequential code from the 1bgo discharge code is carried out by pulses of the clock frequency E, through the terminal 53, which prohibits the passage of the FT frequency in the absence of a frame start or end signal. To evaluate the technical and economic efficiency of the proposed device as a basic Consider the transmission of data in the HDLC communication protocol, in which (FIG. 10) data transmitted from the information source to the information receiver over the communication channel is generated by a source of N frames in N bits in a cache (32 and 2000); a frame sync group is formed on the transmitting side, which is an 8-bit series (01111110), which delimits the beginning and end of each data frame; the data sequence can include any bit configuration. To prevent erroneous recognition of the frame sync group on the receiving side , the following rules apply to all contents of the data bursts: the transmitting side analyzes their contents and inserts the O bit immediately after each series of five consecutive bits 1; The receiving side analyzes the contents of the received packages and the O bit O, which follows five consecutive bits 1. Figure 10 presents a graphical interpretation of the operations of the formation in the basic object of the frame structure, including an arbitrary data sequence framed by 8-bit sync groups 01111110 ( B), and direct and inverse bitstaffing procedures on the transmitting (a,) and receiving (l, j) sides, respectively. In the synchro-group structure, the prefix - the first bit O, the root part - the first five bits 11111 and the suffix - 10 are selected. On the transmission side and the receiving side, a continuous sequence sequence analysis is performed: the presence of a series matching the root part of the synchro group, and the right and inverse of bitstaffing operations. 74 When using a communication channel with the probability of an error P 10, the probability of distortion of the frame sync group in the basic object (provided that the errors in the communication channel are statistically independent and equally probable) is: (1-P) 1- (1- 10) .8.10 -, where m is the number of bits in a sync group, i.e.:. On average, every 12th data frame sent to the communication channel will be retransmitted due to a distortion of the frame sync group. In the proposed device, for families, the data is used for families (STV permissible sync groups: T (to 1 + s, + cf, +.. 92 2 (13-2) where Cn is the number of combinations of n different elements of m; n 13 - the number of bits in the root of the sync group;, 2 - allowable differences from the reference sync group. Then for the proposed device: Р Ы11РЕ.) Idliioi o 09-10 Грк92aujuy 1U. Thus, the proposed device has greater noise immunity. Invention formula 1. Device for transmission and receiving information, containing on the transmitting side a block tam ti, outputs which are tor It is connected to the corresponding first inputs of the comparison unit, the information source and the synchronizer, on the receiving side the memory block, the information receiver and the synchronizer, the communication channel, characterized in that, in order to improve the noise immunity of the device, blocks are inserted into it on the transmitting side delays, comparison result analyzer, bit-stamping time register, OR element and sync group generator, the first output of the information source is connected to the first input of the OR element and the first information input II1269 the delay unit, the outputs of the delay unit are connected to the corresponding second inputs of the comparison unit, the outputs of which are connected to the information input of the result analyzer compared to 5, the outputs of which are connected to the corresponding information inputs of the bitstaffing synchronizer, the first output of which is connected to the information source input, the second and third outputs About connected respectively with the first and second inputs of the register output register is connected to the second input of the OR element and the second information input of the delay unit, the second the output of the information source is connected to the information input of the sync group generator, the output of which is connected to the third input of the OR element, the first, second outputs of the synchronizer are connected to the 20 first control inputs, respectively, of the comparison result analyzer and the bitstaffing synchronizer, the third output of the synchronizer is connected to the control the inputs of the delay unit, the 2S generator of the sync group and the second control inputs of the bitstaffing synchronizer and the comparison result analyzer, the output of the OR element of the transmitting side One is connected to the communication channel input 30, a delay block, a comparison block, a comparison result analyzer, a bittaphing clock and a synchrogram analyzer, the first information j, are entered on the receiving side. The input side of the sync group analyzer of the receiving side is connected to the output of the communication channel, the first output of the sync group analyzer is connected to the first information input of the delay unit, the first output of which and the second output of the sync group analyzer are connected respectively to the first and second inputs of the information receiver, the second outputs of the delay unit and outputs 45 of the memory unit are connected respectively to the first, second inputs of the comparison unit, the outputs of which are connected to the corresponding information inputs of the analyzer - Comparison JQ, the outputs of which are connected to the corresponding second information inputs of the sync group analyzer and information bitstrapping chroniters, the output js of the bitstaffing chroniser is connected to the third input of the information receiver and the BTopbiM information input of the block 17412 delays, the first, second, outputs of the synchronizer are connected to the first control inputs of the comparison result analyzer and the bitstaphing clock, respectively; the third output of the synchronizer is connected to the control inputs of the delay unit, the sync group analyzer and the second control inputs of the comparison result analyzer and the bit stopping driver. 2. The device according to claim 1, that is, that the analyzer of the comparison result contains a register, an element AND, a counter and a decoder, the output of the register is connected to the first, direct input of the element AND whose output is connected to the counting input of the counter , the counter outputs are connected to the corresponding inputs of the decoder, the first output of the decoder is connected to the inverse input of the element I, the information inputs of the register, the combined first clock input of the register and the second direct input of the element And and the combined second clock input of the register and the installation In the counter, O are respectively the informational, first and second control inputs of the comparison result analyzer, the second outputs of the decoder are the outputs of the comparison result analyzer. 3. The POP.1 device, distinguished by the fact that the bitstaffing clock contains counters, triggers, AND elements and OR element, the outputs of the first, second and third counters are connected to the installation inputs O, respectively, of the first, second, and third flip-flops, the forward outputs of which are connected to the first inputs of the first, second, and third elements, respectively, whose outputs are connected to the first, second, and third inputs of the OR element, the inverse outputs of the first, second, and third, respectively the triggers are connected respectively to the combined first inputs, the combined second inputs and the combined third inputs of the fourth and fifth elements I., the installation inputs in 1 of the first, second and third triggers are infor the bycation inputs of the bitstaffing clock, the combined clock inputs of the triggers and the fourth input of the fourth element I, 1312 the combined counting inputs of the first, second, third counters and the second inputs of the first, second, third AND elements are respectively the first and second control inputs of the bitstaffing clock, the outputs of the fifth AND element, the fourth AND element and the OR element are the first, second and second respectively. the third output chronizatbra bitstaffing, 4. The device according to claim 1, characterized in that the sync pattern analyzer contains a register, an AND element, an NOT element and an OR element, the first, second register outputs are connected respectively to the first, second input7414 The first element of the AND, the third output of the register is connected through the element NOT to the third input of the first element AND whose output is connected to the combined first inputs of the second AND elements whose outputs are connected to the corresponding inputs of the OR element, the information input of the register and the second inputs of the second And elements and the clock the register inputs are the first and second information and control inputs of the sync group analyzer, the second register output and the OR element output, respectively. are, respectively, the first and second outputs of the sync pattern analyzer. 2, r, ..: No. Kaifelat cuHtpotpynira t t} f t f 10 If 1 tin ftn aa 1 a f 0 t a t f 0 r a f o n r XOfHfiat P, f I S f in t in} ten tin t t ff a in f a f f I a t1 in f оi i t a 11000010 Pat cattraftHut ". in a f o I 1 t o I 1 0 t o t (10 o 0 t f o ft o 1  The difference I t-aa position t Omrukut t t-t pvtetsi. , go t about t 1 I O.I 1 a / 71 (ittooieitottei OmiipuSafeiifa Kchvr Shiro Group . /, i) Lfffui taH / fUf with SumcirapiLHton (Hfum) I Shisch --i f fottotaetttfOe tettatfafaaaa ) U f a a Of a f a t a 11 o, o j t i a t t a in e Jetiptfit itfui nputnt HfU. -t  r fttarrata. . ftfaet "fterf9 fa - Ctf ftniuxc % lofpiilajoina mff ctanfetfi / a / i : x. 9u.t TttSnuna truth dsuiu.Vfamai a E7 () H Tevntshch / ftHUtmff iw-v loftfiaeua fu.l Phi 7 Fp in f-u position. U) Qmnufue S 1-k positions And on / ru for the sync group torus Susrd X sync group K ffioKy 17 delays To receiver 25 uftgiofnatsii (beginning-end of frame)