SU1295403A1 - Device for exchanging data between serial and parallel interfaces - Google Patents

Abstract

The invention relates to computing and digital automation. Its purpose is to expand the functionality by organizing the exchange of words of variable format and speeding up; B, a device containing a number of nodes traditional for this type of device, an adapter position register with a position decoder, a transmission format expansion block, a format expansion block parcel reception. The proposed device can be used as a universal programmable element for performing serial-parallel and parallel-serial data transformations of any size in computing and digital automation devices oriented to a serial communication interface. To build up the word format, it is possible to combine several exchange devices into a single complex. 4 hp f-ly, 10 ill. I (L N5 SO ate 4 o bo

Description

The invention relates to computing and digital automation and can be used in data transmission systems to adapt a peripheral communication interface with a bi-directional parallel interface and perform serial-parallel and parallel-serial data conversion.

The purpose of the invention is the expansion of functional capabilities through the organization of the exchange of words of variable format and an increase in speed (exchange rate).

Figure 1 presents the block diagram of the device; FIG. 2 shows a block of the transfer format; FIG. 3 shows a block for increasing the reception format; Fig 4 - transmission control block; in FIG. 3, a reception control unit; figure 6 - block control transmission; 7 - block control reception; on Fig-block transceivers; Figures 9 and 10 are two examples of connecting three devices.

The device 1 (Fig. 1) contains a block 2 of transceivers, a decoder 3, a transfer register 4, a first shift (transmission) register 5, a transmission control block b, a second control (transmission control) block 7, a control register 8, a status register 9, reception control unit 10, first control (reception) unit 11, reception register 12, second shift (reception) register 13, position register 14 (with position decoder), transfer format extension unit 15, format expansion block 16.

ema

Block 15 of the recalculation format additionally, the device (Fig. 1) contains the input 1-23 of the sign of expanding the transmission format, the control inputs 124 (chip select, register selection, system read / write and synchronization), the synchronous input 125 (transfer) data bus 126, sync data (FIG. 2) contains the fourth, input 127 (reception), input 128 recognizes, the second, third elements OR 17 are extensions of the reception format, input 20, first, five, fourth, second start receiving, exit 130 end

transfer, data output 131, transfer start output 132, control outputs 133 (transfer request, request

swarm, seventh, shchetoy, third elements And 21-27, second and first triggers 28 and 29, second and first elements 30 and 31 of the addition modulo two.

The building block 16 of the receiving format (FIGURES) contains the third, first, 0 fourth, five, second elements OR 32-36, the first, sixth, seventh, second, quarter, five, third elements AND 37-43, the element NOT 44, the second and first triggers 45 and 46, the second and first elements 47 and 48 modulo two

The transmission control unit 6 (Fig. 4) contains the first, the nine.

breaks, failure, reception request), data input 134, end output 135

. reception. I

Device 1 is intended for

adapting a serial peripheral interface with a bidirectional parallel interface; and performing serial-parallel and parallel-serial data transformations transmitted between these interfaces. Parallel interface data arrives to / from device 1 through eight.

Sh

0

thirty

35

the second, the eighth, the fifteenth, the third, the fourth, the fifth, the sixth, the seventh, the twelve, the ten, the thirteenth, the eleventh, the fourteenth elements AND 49 - 63, the elements NOT 64 - 66, the first, the second, the fifth, the fourth - Thy, third, sixth triggers 67 - 72, element OR 73, counter 74, elements 75 - 77 modulo two.

The acquisition unit 10 (figure 5) contains the first, third, seventh, second, dvena, tsaty, sixth, fourth, eighth, eleven, nine, ten, five, thirteen elements And 78 - 90, the second, the first, the third elements are NOT 91 - 93, the first, the second, the quarter, the third, the sixth, the five triggers 94 - 99, the elements OR 100 and 101, the 1P2 counter, the elements 103 - 105, modulo two.

The second block 7 of the control (transmission) (6) contains elements 106 and

107 modulo two, trigger

108 and element 109.

The first unit 11 of the control (reception) (Fig.7) contains elements 110 and 111 modulo two, trigger 112, and element 113.

Unit 2 transceivers (Fig.8) contains amplifiers, transmitters 114 - 116, amplifiers, receivers 117 - 119, elements OR 120 - 122.

In addition, the device (Fig. 1) contains an input 1-23 of the sign of expanding the transmission format, control inputs 124 (chip select, register selection, system read / write and synchronization), synchronous input 125 (transfer), data bus 126, sync O input 127 (reception), input 128 sign of expansion of the reception format, input 129 start of reception, output 130 of the end

breaks, failure, reception request), data input 134, end output 135

. reception. I

Device 1 is intended for

adapting a serial peripheral interface with a bidirectional parallel interface; and performing serial-parallel and parallel-serial transformations of data transmitted between these interfaces. The parallel interface data is transmitted to / from device 1 via an eight-bit bidirectional bus 12.6 of block 2. Output serial data is transmitted from the output 131 of the transfer shift register 5, and is received at the input 134 of the receive shift register 13. Sending and receiving serial data is synchronized by the transmit and receive synchronization signals, respectively, arriving at the inputs 125 of the transmission control unit 6 and the input 127 of the reception control unit 10. The moments of the beginning and end of the transmission of serial data are determined by the signals at the outputs 132 and 130 of device 1, respectively, and the moments of the beginning and end of reception of the serial data, respectively, by signals at input 128 and output 135 of device 1.

The exchange of data to the method by parallel and serial interfaces is carried out by transferring and receiving scattering.

Device 1 contains five software-accessible registers: transfer register 4 (8-bit), reception register 12 (8-bit), register 8

control (5-bit dny), register 14 positions (2-bit dns) with the output decoder and state register 9 (5-bit). The status registers 9 and reception 12 are read-only, and the transfer registers 4, control 8, and adapter positions 14 are write-only. Reading register 9 causes a reset of its bits. The outputs of the respective state register triggers 9 are the outputs 133 of the device 1.

The access to the registers is controlled by the chip sampling, register sampling, read / write, and synchronization signals at the input 124 of device 1.

The corresponding combination of these signals causes the appearance of a corresponding access signal to the register at the output of decipheror 3. At the same time, the signal from the second output of the decoder 3 causes the transfer of transmitter amplifiers 114-116 or receiver amplifiers 117-119 of block 2, depending on access by reading or records that should be executed, from the third high impedance state to the working state. As a result, information from the bus 126 enters the selected register or from the selected

0

five

register through the elements OR 120 - 122 block 2 - on the bus 126.

After turning on the power, the resetting circuit of the device (not shown) causes the reset of the registers and blocks of the device. As a result, signals are output at outputs 133, indicating respectively a receive request, a transfer request and an interrupt request.

These signals are perceived by a software control device (for example, a microprocessor) of the system in which the device operates. The software control device responds to these signals by programming device 1 to operate, consisting in writing the corresponding control information to the control register 8 and the position register 14, and in the case of data transmission also in the recording, the transmission parcel data is sent to the transmission register 4.

Control register 8 contains two functional fields: the word format field of the data to be converted and the role of the data control type. The word format field of control register 8 consists of three bits, the value of which indicates one of eight possible word formats (1-8 bits of data). The data control type field contains two bits, the value of which indicates one of three possible control types: no control, even parity, oddness control. The outputs of the word format field bits form the first control register 8 of the control register, and the outputs of the control type field bits form the second output of the control register 8.

The position register 14 with an output position codec decoder contains two bits, the four decoded values of which form four lines of the output lines of the register decoder register 14, the first, second and fourth positions of which indicate the last, first and middle positions of the device 1 when expanding the format transform words0

five

0

five

0

third is for work without increasing the word format of the data to be converted.

Synchronization of transmission actions is carried out by synchronization signals.

transfer, enter Tsimi at the input 125 of the transfer control unit 6. Writing data to the data transfer register 4 causes a reset of the request to trigger a transfer request register. In transmission control block 6, this causes the NOT 65 element AND 53 to simultaneously reset the counter 74, set the trigger 69 Transmission shift register is full and appears on the second output of the data entry signal from the transfer register 4 to the shift register 5. This signal causes the request-to-transfer trigger to be set in the state register 9, and in block 15, a reset via AND 23 (if the transmission is made without increasing the word format) of trigger 28 and the output of the transmission trigger signal at the output of AND 24. The occurrence of this signal in transmission control block 6 causes, via element 58, a reset of the trigger 70 of the word format count.

2Q through the elements And 63 and And 56 leads to the installation of the trigger 70 of the transfer format account. Setting this trigger triggers actions that result in the appearance of a trigger that is in its initial state. The reset of the trigger 70 is caused by the 25 dB element OR 73 of the signal terminating through the AND 57 element the setting of the trng transmission. Moreover, the transfer sequence is 71, this permits the appearance at the outputs of the AND 60 and 62 elements of the transmission clock signals, the post action depends on the information in the position register 14 and in the control type field of the control register 8 only

those who go to the third entrances of these elements are “in a nice way.

The end of the signal at the output of the element And 62 leads to the installation of the trigger 72 of the start of transmission and blocking the appearance of the following clock signals at the output of the element And 62.

The signal to start the transmission from the output of the element And 62 enters at the output 132, informing the external environment about the beginning of the transmission of the word and the appearance of the TRANSFER device 1 operates without monitoring the transmission and reception parcels, regardless of the position of the device 1 and therefore at the entrance

element 64 of transmission control block 6 is missing. In this case, the installation of a format counting trigger 70 results in an AND 52 to the second-time bit at the output 131. At the same time, at the output of the OR element 73, a signal to start the transfer caused the transfer to end. In the control unit 7, the setting through the trigger 70 causes the reset element AND 61 to reset the start of the trigger 108 through the control element 109 and, in block 15, sets the transmission, and through the control element 59 to the trigger 28 and memorizes in trigger 45 reset transfer trigger 71, moment

29 information on his other entry. The installation of the trigger 28 blocks the generation element And 24 signal start transmission. The first signal at the output of the element 60 of the transmission control unit 6, which appears simultaneously with the signal of the beginning of the transfer at the output of the element 62 and 62, is entered into the 3-digit counter of the format account 74, which was previously reset by the signal from the output of the element 53 At the same time, this signal arrives as a counting signal in the control unit 7, where, through the element 106, it calls

modulo two, the discharge of a single value of the discharge coming from the first output of the shift register 5 into the trigger 108. The position code from the outputs of the counter 74 controls the shift of the first (minor) bit of the transmitted word to the outputs of the shift register 5. Each subsequent signal at the output of the element And 60 causes a repetition

described actions to transfer the word bit. This continues until the value of the format counter 74 matches the value of the format of the word specified in the format field.

the words of the control register 8 and the input to the inputs of the elements 75 - 77 modulo two. When these values coincide, signals appear on the outputs of the latter.

through the elements of And 63 and And 56 lead to the installation of the trigger 70 account transfer format. The installation of this trigger causes the execution of actions leading to the output at the output of the OR element 73 of the transmission termination signal. And the sequence

DB element OR 73 signal end transmission. And the sequence

these actions depend on the information in the register 14 position and in the field of control type of the register 8 control only

If the device 1 operates without control of the transmission and reception parcels, regardless of the position of the device 1, the signal at the output of the element 21 of block 15 and, therefore, at the input

element 64 of transmission control block 6 is missing. In this case, the installation of a format counting trigger 70 results through an AND 52 element, for whose release it determines the falling edge of the transmission termination signal at the output of the OR element 73.

If device 1 operates with control of transmitted and received data (regardless of whether parity or oddness is monitored) and the position register 14 indicates the first or middle position of device 1 when expanding the word format, the transmission termination signal at the output of the element OR 73 formed in a manner similar to the one described.

If ycTpoHCTfo 1 works as in the previous case with data control, but the 14th position register indicates operation without increasing the word format or the last position of device 1 when expanding the format, the signal at the output of the And 21 element of block 15 and, therefore, at the input of the And element 50 of the transmission control unit 6 is present. In this case, after setting the trigger 70 of the format account at the moment of resetting the transfer trigger 71, the falling edge of the signal from the output of the AND 50 element causes the setting of the control switch transfer trigger 67. The installation of the trigger 67 through the element AND 51 leads to the appearance at the output of the element OR 73 of a transmission end signal, the falling edge of which is formed at the time of the end of the clock signal at the input of the I-51 element. The installation of the trigger 67 of the control bit transmission causes the transfer to the output of the AND element 49 and further through the shift register 5 - to the output 131 of the check bit information generated in block 15,

In all three cases described, the falling edge of the transmission termination signal causes a reset of the trigger 67 of the transmission of the pilot bit and the installation of the trigger 68 of the transmission termination. Setting trigger 68 triggers reset element 69 through AND 55. The shift register is full. If by this moment the data of the next transmission send is recorded in the transfer register 4 (as evidenced by the reset transfer request trigger of state register 9), then the output of the element 53 appears to transfer data from the transfer register 4 to the shift register 5 and all are repeated described data transfer actions. If transfer register 4 is empty, reset trigger 69 causes the trigger state in register 9 to be set. The transfer path is empty.

The data is monitored during transmission in block 7 of the control. It consists in calculating modulo two the number of unitary values of the data bits of the send and the formation of the value of the control bit corresponding to the type of control specified in register 8 of the control. The value of the trigger 108 of the control unit 7, as well as the value folded modulo two with the bit value of the control type of the control register 8, are received respectively via the first and second lines of the Output Line Group of the control block 7 to the block 15.

The synchronization of data reception actions is carried out by signals input to the input 127 of the reception control unit 10. The initiation of the data reception operation in the device 1 occurs at the reception start signal, which enters the input 129 of the block 16. The appearance of this signal means that the first (minor) bit of the data word enters the input of the shift register 13 and the first input of the control unit 11. The reception start signal via the element 36 of the block 16 enters the reception control block 10. If device 1 operates without increasing the word format, the output of element And 40 of block 16 has a reception start signal, since the trigger 45 is reset in the initial state, and the third input of the OR element 34 has a work signal without increasing the format, coming from the third output one time - th register decoder 14 position. The start and receive start signals cause the signal at the output of the AND 82 element of the control and reception unit 10 and the reception, since the trigger 97 of the counting format account in the initial state is reset. The signal from the output of the AND 82 element sets the trigger 96 of reception, causes the unit to be entered into the counter 102 of the format and enters as a reset signal to the input of the AND 113 element of block 11, resetting the reset state 112. Resetting the trigger 96 causes the elements OR 101 and AND 85, the receipt of the reception clock signals in block 11 of the control. At the same time, the position code from the outputs of the counter 102 controls the transmission of the data of the reception desk to the shift register 13.

The installation of the reception trigger 96 also leads to the installation through the AND element 89 of the trigger 99 The reception shift register is full, which indicates that the first bit of the received word is received in the shift register 13. The installation of the trigger 99 leads to blocking of the signal at the output of the element And 88, which caused in block 16 a reset of the trigger 45 through the element And 39.

The arrival of each receive clock causes an increase of +1

3-bit cyclic counter value 102 of the format account. When the coincidence of the bits of the counter. The values of the word bits of the format of the word register 8 of the control at the outputs from the elements 103 - 105 of the modulo two add signals that, through the element 90 and 83, cause the installation of the triggers of the 97 format account and the end of reception 95. Setting the trigger fO pa 97 results in resetting through reception element 84 and 84 of reception trigger 96, which, in the absence of a reception request signal at the output of register 9, is set to install via HE elements 93 t5 and And 86 of trigger trigger 98 to the reception register 12. This leads to the entry of information from the receive shift register 13 to the receive register 12, to setting the trigger request state 20 in the register 9, and the receive request and the trigger request, which in turn through the And 87 element resets the trigger 98. Setting the trigger 25

Hera 98 leads to resetting the trigger 99 The receive shift register is full and therefore the appearance at the output of the And 88 element of the reset signal of the trigger 45 of block 16. Resetting the trigger 45

A signal appears at the output of the element 40 of the reception trigger that causes the reset 97 of the reception format count to be reset and prepares the reception control unit 10 to initiate the reception of the next word.

Setting the trigger end 95 of the reception of the reception control unit 10 calls the sequence of actions for processing the reception end signal at the first output of the block 16. This sequence depends on the information in the position register 14 and the information in the control register type field of the control control B as follows.

If the device 1 operates without monitoring the received data, regardless of the position of the device 1, there is no signal at the output of the element 37 of the block 16 and, therefore, at the input of the element HE.91 of the reception control block 10. In this case, the installation of the trigger 95 of the reception end is signaled through the element AND 79 and the appearance at the output of the element OR 100 of the signal of the end of reception.

If device 1 is working with the control of received data (regardless of whether it is even or even odd O 5 0

five

About 5

0

five

there is a control) and the position register 14 indicates the first or middle position when building up the word format, the reception end signal at the output of the OR element 100 is generated in the same way as in the described case.

If device 1 works as in the previous case with monitoring yes; nn, but register position 14 indicates operation without increasing the format or the last position of device 1 when expanding the format, the signal at the output of the And 37 element of block 16 and, therefore, the input element And 80 block 10 control reception is. In this case, after the reception end trigger 95 is set, but before the reception trigger 96 is reset, check trigger trigger 96 is set through AND 80. The installation of the trigger 95 of the reception end, through the element OR 101, causes the appearance of the signal AND 85 at the input of the element, which leads to the reception of the value of the check bit by the control unit 11. The setting of the trigger 94 causes, through the AND 91 element, the appearance of the output of the OR element 100 of the reception termination signal. The installation of trigger 94 results in the appearance at the output of the And 78 signal of a control failure if there is a mismatch between the received check bit and the check bit generated in block 16.

In all three cases described, the falling edge of the reception end signal causes a reset of the reception end trigger 95, the reset of which causes the reset of the control reception trigger 94. At the same time, the reception end signal through the element OR 33 of the block 16 enters output 135, informing the environment about the end of word reception.

The data is monitored at reception in block 11 of the control. It consists in calculating modulo two quantities, single values of word bits of the received data, generating a check bit value of the received data corresponding to the type of control specified in control register 8 and comparing this value with the value of the received check bit of the word received. The trigger value 112 of the control block 11, as well as its value, folded modulo two per

1112

modulo two addition element 111, with a bit value. The control type of the control register 8 is fed through the first and second lines of the output lines group of the control unit 11 to the receiving form extension unit 16.

Device 1 provides the exchange of shipments with a maximum format of 8 data bits. In order to exchange shipments above 8 bits, several devices must be connected. The number of adapters is related to the length of the patch m as follows

nie n 1 about 1 where I-

em is the largest integer part of the number -Q-.

about

The connection of the required number of devices 1 is performed in such a way that at outputs 130 and 135, the previous ones are connected respectively to inputs 123 and 128 of the subsequent one. Moreover, the inputs 123 and 128 of the first device are connected respectively to the outputs 130 and 135 of the last device. Thus, there is a chain connection of devices, in which all devices 1 located between the first and the last are called averages. When programming chain devices for operation, the position register 14 of each device is entered with the code of the corresponding device position in the chain (first, middle, last).

The connection of the remaining inputs and outputs of the devices 1 in the chain depends on the size of the parallel bidirectional data bus 126.

Figure 9 shows an example of the connection of three devices 1 for the case of an 8-bit bidirectional parallel data bus and a 24-bit word format. In this case, the inputs 124 of all devices 1 (except for the Select Crystal input), respectively, are connected so that the choice of one or another device for programming

or the exchange of parallel data, the Q-ID of the IDN 20 of block 15 is fed to

determined by the input information. The selection of the crystal, the inputs 134, 127 and 125 of all devices, respectively, are connected. Outputs 133 are used independently, as they carry information about the state of devices 1. Outputs 132 of middle and last devices 1 are not used in the same way as inputs 129.

the second input of element 22, the remaining inputs of which receive, respectively, signals from the first output of the flip-flop 28, which was installed at the moment of the start of the transfer, from the second output of the flip-flop 71 of the transmission control unit and from the presence of the control of the control-control-8 control field. As a result on

12

0

Q

Figure 10 shows an example of connecting three devices 1 for a case of a 24-bit parallel data bus and a 24-bit word format. Since in this case, the programming of all devices and the exchange of data with them takes place simultaneously, respectively, the inputs 124 of all devices are connected. The outputs 131, a; and the inputs 134, 127, and 125 of the adapters are connected in the same way as in the previous case.

Line The failure of the output 133 of the first device 1 and the transmission request 5 line, the reception request and the interrupt request of the output 133 of the last device 1 informs the system about the state of the devices.

Consider the work in the transfer mode of the device 1 when increasing the format of the word. If in register 14 position it is indicated that it is the first in the chain, similarly to when the device is working alone, a transmission start signal appears at the output of the element AND 24 of block 15, since

the triggering state, the trigger 28 is reset, and the position signal is the first at the second input of the OR element 19. The occurrence of a transmission trigger causes actions similar to those described for when the device operates without increasing the word format, until the appearance at the output of the element OR 18 of the transmission termination signal. Then, after the transmission end signal is issued, which initiates the transmission in the next (middle or last) device 1 of the chain, the output 130 of the first device 1 receives a counting signal modulo two transmitted words, which is taken into account by the next chain device 1 when generating its counting output signal module two. This signal is generated as follows. The value of the trigger 108 of the control unit 7 through the element 26 and the second input of the element 22, the remaining inputs of which receive signals from the first output of the trigger 28, which was set at the moment the transfer began, from the second output of the transmission trigger 71 of the transmission control block 6, and Yes, the presence of the control field control register 8 control. As a result on

13

The output of the element And 22, and then at the output of the element OR 18, a modulo two data signal appears, transmitted by the device.

After all the devices in the chain have transmitted the first input of the trigger 29 of the block 15, the first device receives a signal from the output 130 of the last device, which resets the trigger 28, thereby allowing the element 24 to produce a transmission start signal. If at this point new data has been loaded into transfer register 4, the data transfer process is resumed.

If in the position register 14 it is indicated that the device is average in the chain, in this case, the transmission termination signal from the previous (first or middle) device enters the first trigger input 28 of block 15, causing it to be reset. This leads to the appearance at the output of the element 24 of the transmission trigger signal, which enters the transmission control unit 6, initiating the described data transmission actions. The transmission start signal from transmission control block 6 causes the trigger 28 of block 15 to be set and the information written to the trigger 29 at the first input of this trigger is set to write. This information in the case of increasing the word format when monitoring the transmitted information is the modulo counting signal of two unit words of the previous device, which through the addition element 30 modulo two, the AND 25 element, the OR 20 element, the AND 22 element and the OR 18 element comes after the end of the transmission signal of this device to the output 130 End of transmission,

If in register 14 position it is indicated that the device is the last in the chain, in this case the signal is terminated12

The transmissions from the first output of the previous (first or middle) device 1 are fed to the input 123 of the block 15 of the last device of the chain and trigger actions to start data transmission, which are similar to the described case. After the end of the transfer of data from the shift register 5, the signal of the end of the transfer of data from the output 130 of the last device to the input 123 of the first device of the chain causes the transfer of the data of the new word. In the

50

- 55

9540314

In addition to the word control, when transmitting, the last device outputs to the second output of the shift register 5 information of the check bit, which is formed in block 15 with the help of trigger 29, element 27 and addition element 31 modulo two.

The operation of the device 1 in the reception mode when expanding the format of the word.

JO If in the position register 14 it is indicated that the device is first in the chain, similar to when device 1 is working alone, the output of element 40 of block 16 has a start signal at j5, since trigger 45 is reset in the initial state, and at the second input element 34, there is a signal of the first position of the device. The appearance of the reception start signal at block 123

20, 16 causes actions similar to those described for the case of operation without building up the word format until the end signal is output through the element OR-33 of the block 16. After

25 by issuing a reception termination signal, which initiates the reception of the reception in the next (middle or last) device 1 of the chain, to the output 135 of the device 1, if the reception is carried out

30 seconds, the control signal receives the modulo signal of two received data, which is taken into account by the next device 1 of the chain when forming its output signal of the modulo 35 ly two. The modulo count signal of the two data received by the first device 1 is generated as follows. The value of the trigger 112 of the account modulo two of the control block 11 through the elements of AND 42 and OR 35, And 38 and OR 33 of block 16 enters the output 135 of the adapter.

After receiving all the devices in the chain, the reception end signal from the output 135 of the last device in the chain, which resets the trigger 45, is received at the first input of the trigger 45 of block 16 of the first device 1, thereby allowing the element 40 to generate the receive trigger signal. If, next to this, a start signal appears at the input of device 1, the process of receiving a trace;

If in register 14 of the position of device 1 it is indicated that it is average in the chain, the reception end signal from the previous (first or middle) device enters the second

15

trigger input 46 of block 16, causing it to reset. This leads to the appearance at the output of the element And 40 of the reception trigger signal, which in the reception control unit 10 causes the described sequence of actions for receiving data. If the reception is carried out with control, after the end of the reception of data by the average device and the signal of the end of reception in the trigger

46 of block 16, information is input from input 13A, which is modulo information of the account modulo two unit values of data bits received by the previous device. This information is added to the item.

47 modulo two with trigger count value modulo an average device and through elements

And 41, or 35, and 38 and or 33 are fed to the input 134 of the next (middle or last) device of the chain.

If the adapter position register 14 indicates that it is the last one in the chain, in this case the reception end signal from the previous adapter (first or middle) of the chain adapter is fed to the input 134 of the last device, causing actions to start the reception, similar to the previous case. If the data is received with control, in block 16, the device on elements And 43 and element 48 of the modulo-two addition controls the data of the received word received by all devices. In the event of a violation of the control type, the signal from the output of the addition element 48 modulo two is fed to the And 78 element of the receive control block 10 and then to the state register 9, where it causes a trigger to fail.

Claims (5)

1. A device for data exchange between parallel and serial interfaces, comprising a transceiver unit, a decoder, a transmission register, two shift registers, a control register, a reception register, two control units, a status register, a transmission control unit, a reception control unit, and the decoder inputs are the inputs of the device to connect to the control buses O five 0 five The parallel interface NIN, the first to fifth outputs of the decoder are connected respectively to the synchronous inputs of the transmission register, the control register, the status register, the reception register and the control input of the transceiver unit whose input-output is the input-output of the device parallel interface buses, the information output of the transceiver unit is connected to the information inputs of the control register and the transmission register, the output of which is connected to the information input of the first the shift register, the output of which is the output of the device for connecting the serial interface to the data bus, the information input of the receive register is connected to the output of the second shift register, whose information input is the input of the device for connecting to the serial interface information bus, first to fourth outputs the status registers are the outputs of the device for connection to the control bus of the parallel interface; the fifth output of the status register is connected to the first information input ode transceiver unit, the second information input of which is connected to the output of the receive register, the first, second, third and fourth outputs of the reception control unit are connected respectively to the synchronous input of the second shift register, the first information input, the parity input of the first control unit and the first installation input of the state register , information and second installation inputs of which are connected respectively to the first and second outputs of the transmission control unit, also connected to the recording input ne Vågå shift register, a control bit input and the shift input of which is connected respectively with the third and fourth outputs of the transmission control block 0, the five output of which is connected to the counting input of the second control unit, the first information input of which is connected to the output of the control shift register, the first and fourth outputs of the state register are connected respectively to the inputs of the transmission control block and the block reception control, fifth output which five 0 five five 17, connected to the third setup input of the status register, and the write input of the receive register, the first output of the control register is connected to the input settings of the word format of the transmission control unit and the reception control unit, the synchronous inputs of which are respectively the transmission and reception sync inputs of the device, the second output of the control register - JO yen with the inputs of the control type setting of the first and second control blocks, the second information input of the first control block is connected to the device input for connecting to the information f5 The serial interface bus is characterized in that, in order to enhance functional possibilities due to the organization of the exchange of words of variable format 20 and speeding up, it contains a position register, a transfer format extension unit and a transmission block; the reception format, where the information and sync inputs of the position register 25 are connected respectively to the output of the transceiver unit and the second output of the decoder, the output of the position register is connected to the inputs of the position attributes of the building block 30 the transmission and the receive extension block whose control inputs are connected to the second output of the control register, and the inputs of the format expansion attribute are 5 identical inputs of the device, the output of the transmission end of the transmission extension module is the output of the transmission end of the device, and the gate outputs, start of transmission and 40 control bits of the block are connected to the same inputs of the transmission control block, the sixth and seventh outputs of which are connected to the inputs of the end of the transmission and the sign of the transmission of the block by increasing The transmission format, the eighth output of the transmission control unit is connected to the transmission start inputs of the transmission format incrementing unit, the second control unit and 50 is the device Start transfer code, the second output of the transmission control unit is connected to the recording input of the transmission format extension unit, control bit input 5 which is connected to the output of the second control unit, the input of the start of reception and the exit end of the reception of the building block of the receiving format are 129540318 The device's input and output, gate outputs, reception start, check bit, reception start and reception end inputs, reception feature, unit reset, reception format definition are connected to the sixth, seventh, eighth outputs of the reception control unit, the output of the first block The control unit is connected to the input of the control bit of the block for increasing the reception format. 2. Device POP.1, characterized in that the increment block of the transmission format contains the first, second, third and fourth elements OR, first, second, third, fourth, fifth, sixth and seventh elements AND, first and second triggers, first and the second addition module modulo two, the outputs of the transmission end, strobe, transmission start and check bit are connected respectively to the outputs of the first OR element, the first and second And elements, and the first addition element modulo two, the first and second inputs of which are connected with pen the output bit of the input of the control bit of the block and the output of the third element I, the first and second inputs of which are connected respectively to the first bit of the input of the block position indicator and the output of the first trigger, the first and second inputs of which are connected respectively to the inputs of the format extension attribute and the start of the transfer of the block a, the input of the characteristic of the format of the block co. the first and second inputs of the second element OR and the second trigger, the second and third inputs of which are connected respectively to the outputs of the fourth element AND and the input of the beginning of the block transfer, the first and second outputs of the second trigger are connected respectively to the first input of the fifth element AND and the first input of the second element And, the second input of which is connected with the output of the second element of the IPD, the second and third inputs of which are connected respectively to the second and third bits of the input of the block position feature, the second bit of the position sign input unit is connected to the first input of the sixth element And, the second input of which is connected to the first input of the second addition element modulo two and the second discharge of the input of the check bit of the block, v129595403 the second element of the second two is connected to the output of the rigger; the outputs of the second arc modulo two and the sheeta are connected by the corresponding j-first inputs of the seventh AND and the third OR element, whose ods are connected to the fourth bit of the Vokok position of the block and the output of the JO element AND, the output The third OR is connected to the second inlet of the AND element, the third and the inputs of which are connected to the inputs of the sign 15 and the block transfer, the output of the AND terminal is connected to the first of the OR element, which is connected to the input The first of the two is not the same as the second half of the second half of the first half of the second half of the second half of the first half of the second half of the second half of the second half of the second half of the second half of the second year. tgo me the end of the block transfer, the first and second inputs of the first element I are connected respectively to the input of the control sign and in the output of the fourth element OR, the first and second inputs of which are connected respectively to the first and third bits of the input of the sign of the position of the block And, the second input of which is connected to the input of the recording block. 3. The device according to Claim 1, characterized in that the block of building up the reception format contains the first, second, third, fourth and second elements OR, the first, second, third, fourth, fifth, sixth and seventh elements AND, the element NOT , the first and second triggers, the first and second elements of the modulo two addition, the outputs of the receiving end, strobe, reception start, the check bit and the start of reception are connected respectively to the outputs of the first OR element, the first and second And elements, and the first addition modulo two and second elements of IL inen with the first bit of the input of the block position indicator, the first input of the third element OR and the first input of the third element AND, the second input of the second element OR is connected to the second discharge of the input of the block position indicator and the first input of the fourth element AND, the third input of the second element OR is connected with the input of the beginning of the reception of the block, the second input of the fourth element I is connected to the output of the second element of the addition modulo two. 20 - five five 0 0 5 0 5 0 5 whose first input is connected to the first bit of the control block input and the first input of the fifth element And, the second input of the second addition element modulo two is connected to the output of the first trigger, the first input of which is connected to the input end of the block and the first input of the first element OR , the second input of the first trigger is connected to the input of the sign of the expansion of the block format, the first inputs of the fourth IL element and the second trigger and the second input of the third And element, the output of which is connected to the first input of the first layer element Modulo two, the second input of which is connected to the second discharge of the control block input, the second input of the fifth element AND is connected to the third discharge of the input of the block position and the second input of the fourth element OR, the output of the fifth element AND is connected to the first input the fifth OR element, the second input of which is connected to the output of the fourth AND element, the output of the fifth OR element is connected to the first input of the sixth AND element, the second input of which is connected to the first output of the second trigger, the third input of the sixth AND element n with the input of the block and. the input element is NOT, the fourth input of the sixth element is AND is connected to the input of the control sign of the block and the first input of the first element is AND, the output of the sixth element is AND is connected to the second input of the first element OR, the second input of the first element is AND is connected to the output of the third element OR, the second input of which is connected to the fourth bit of the input of the sign of the block position, the third input of the fourth ILI element and the first input of the seventh element I, the second input of which is connected to the reset input of the block, the output of the seventh element I, is connected to the second input of the second trigger, the third input of which is connected to the output of the NOT element, the second output of the second trigger is connected to the first input of the second element AND, the second input of which is connected to the output of the fourth element OR. 4. The device according to claim 1, which means that the transmission control block contains AND, OR, NOT, triggers, a counter, an element. You add modulo two, with the output of the first element I being the third output of the block, the first input of the first element I connected to the input of the control bit of the block, the second input of the first element I connecting to the output of the first trigger and the first input of the second element I, the second input of which connected to the first inputs from the third to the seventh AND elements and the output of the first element NOT, the output of the second element AND connected to the first input of the first OR element, the second input of which is connected to the output of the eighth element AND, the output of the first IL element And connected to the first inputs of the first and second triggers and the sixth output of the block, the second input of the first trigger is connected to the output of the ninth And element, the second output of the first trigger is connected to the second input of the seventh And element, the first input of the ninth And element is connected to the first output of the third trigger , the first inputs of the eighth, tenth and eleventh And elements and the second input of the fifth element And, the second input of the ninth element And connected to the input of the gate of the block and the input of the first element NOT, the output of which is connected to the second input of the eighth And, the third input of which is connected to the first output of the fourth trigger and the first inputs of the twelfth and thirteenth elements And, the third input of the fifth element And is connected to the output of the fourteenth element And, the output of the fifth element And is connected to the first input of the fourth t5 the second trigger whose second input is connected to the output of the seventh element And, the second output of the fourth trigger is connected to the second inputs of the tenth and eleventh elements And and the second input of the sixth element And, the third input and output of which are connected respectively to the first output of the fifth trigger and the first the input of the third trigger, the second input of which is connected to the output of the twelfth element I, the second output of the third trigger is connected to the sixth output of the block and the third input of the seventh element I, the fourth input of which is connected to the start of the transfer of the block, the second input and the output of the second trigger are connected (Accordingly, with the output of the third element AND and the second input of the fourth eleventh4040322 And the second input of the third element And is connected to the second output of the fifth trigger., the first output of the block and the first input of the fifteenth element And, the first input of the fifth trigger (. connected to the output of the fourth element And, the second input of the fifth trigger is connected to the input reset the counter, the second output of the block and the output of the fifteenth element I, the second input of which is connected to the output of the second element NOT, the third input of the fifteenth element AND is connected to the synchronous input block, the input of the third element NOT, the second inputs of the twelfth and thirteenth elements And the third inputs of the tenth and eleventh And elements, the input of the second element is NOT connected to the input of the block transfer request, the output of the thirteenth element And is connected to the first input of the sixth trigger, the second input of which is connected to the output of the eleventh And element and the eighth output of the block, output of the sixth the trigger is connected to the fourth input of the eleventh element I, the output of the tenth element I is connected to the fifth output of the block and the counting input of the counter, the first, second and third outputs of which form the fourth output of the block and connected with the first inputs of the first, second and third elements of addition modulo two, the second inputs of which form the input of setting the block word format, the outputs of the first, second and third elements of addition modulo two are connected respectively to the first, second and third inputs of the fourteenth element AND . 20 25 thirty 35 40 45 /ABOUT 55 5. The device according to claim 1, wherein the reception control unit contains AND elements, NOT elements, triggers, OR elements, a counter, addition elements modulo two, the output of the first AND element is the fourth output of the block, The first input of the first element I is the input of the control bit of the block, the second input of the first element I is connected to the output of the first triggers, and the first input of the second element I, the second input of which is connected to the synchronous input of the block, the first inputs of the third, fourth and fifth elements And the input of the first element NOT output of the second AND element is connected to a first input of the first five ABOUT five 5. The device according to claim 1, wherein the reception control unit contains AND elements, NOT elements, triggers, OR elements, a counter, addition elements modulo two, the output of the first AND element is the fourth output of the block, The first input of the first element I is the input of the control bit of the block, the second input of the first element I is connected to the output of the first triggers, and the first input of the second element I, the second input of which is connected to the synchronous input of the block, the first inputs of the third, fourth and fifth elements And the input of the first element NOT output of the second AND element is connected to a first input of the first 231 the OR element, the second input of which is connected to the output of the third element AND, the output of the first element IL is connected to the sixth output of the block and the first input of the second trigger, the second input of which is connected to the output of the sixth element And and the first input of the third trigger, the first output of the second trigger the input of the first trigger, the second output of the second trigger is connected to the first inputs of the seventh element AND and the second element OR, and the second input of the third element AND, the third input of which is connected to the output of the second element NOT whose input o is connected to the gate input of the block and the second input of the seventh element I, the third input of which is connected to the output of the first element NOT and the first inputs of the sixth, eighth, ninth and tenth elements And, the fourth input of the seventh element And connected to the first input of the eleventh element And, the seventh output of the block and the second output of the fourth trigger, the output of the seventh element And is connected to the second input of the first trigger, the second input of the third trigger is connected to the input of the block start reception and the first input of the twelfth element And, the first output of the third This trigger is connected to the second input of the fourth element I, the second output of the third trigger is connected to the second input of the fifth element I and the second input of the twelfth element I, the third input of which is connected to the input of the beginning of the block reception, the output of the twelfth element I is connected to the third output of the block, input reset counter and the first quarter entrance (o five 403 0 five 0 five 0 24 trigger, the second input of which is connected to the output of the fourth element AND, the first output of the fourth trigger is connected to the third input of the fifth element AND, the second input of the second element OR and the second input of the sixth element And, the third input of which is connected to the output of the thirteenth element AND, the output of the second element OR is connected to the second input of the eighth element AND, the output of which is connected to the second output of the block, the input request request of which is connected to the second input of the ninth element Neither the input of the third element NOT, the output of which is connected to the third input and the output of which are connected respectively to the first output of the fifth trigger and the first input of the sixth trigger, the second input of which is connected to the output of the ninth element I, the output of the sixth trigger is connected to the fifth output of the block and the first input of the fifth trigger, the second input of which is connected to the output of the fifth element AND and the counting input of the counter, the second output of the fifth trigger is connected to the second input of the tenth element And, the output of which is connected to the eighth output of the block, first, second and third the outputs of the counter form the first output of the block and are connected to the first inputs of the first, second and third elements of the addition modulo two, the second inputs of which form the input setting the format of the block word, the outputs of the first, second and third elements of the modulo two are connected respectively to the first, second and second the third inputs of the thirteenth element I. FIG. ten.f - {I J FIG. g from to from 8 to t0t 1 129 I (i ± iz:  I., i. (rig 7 fJ5 Klo from IS 6 / J / j out of 10 of you of 8 figl 5 fig