SU1099321A1 - Device for transmitting and receiving digital information - Google Patents

Abstract

1. DEVICE FOR TRANSMITTING AND RECEIVING DISCRETE INFORMATION containing a data loss detector, the output of which is connected to the first register input, the first decoder, generator, output encoder, control unit, the second input of the register is connected to the first input of the device, the output - with the first input of the output encoder The input of the first decoder is combined with the first input of the information loss detector, characterized in that, in order to increase the information transfer rate, a second decoder, a memory block, a modulator, a set unit phase, the first and second amplifiers, the first input and output of the first amplifier are connected respectively to the second input and the first output of the device, the second input and the second output respectively to the modulator output and the first inputs of the loss of information detector and the first decoder, the first and second inputs of which connected respectively to the first inputs of the memory unit and the phase setting unit, the first and second outputs of which are connected respectively to the second and third inputs of the memory unit, the output of which is connected to the second input output encoder, the fourth input of the memory unit, the first input of the second decoder, the first input of the control unit, the second input of the phase setting unit are connected to the generator output, the output of the second decoder is connected to the second input of the control unit and the fifth input of the S memory block, the sixth input which is connected to the first output of the control unit, the second output of which is connected to the second input of the information loss detector, the third output to the input of the modulator, the fourth output to the third input of the register, to the first and third inputs of which n control unit, the first output of which is connected to the second input of the second decryption: o rator, the third input of which is connected: o with the output of the second amplifier, the first N5 input of which is connected to the output of the output coder, the first output and the second input, respectively the output and the third input of the device. 2. The device according to claim 1, characterized in that the memory block contains triggers, registers, groups of AND elements and the OR element, the first input of the memory block is connected to the first input of the first register, the second input of which is connected to the first input of the second register and zero way out

Description

the first trigger, the unit input of which is connected to the second input of the memory unit, the third input of which is connected to the third input of the first register, the second input of the second register and the counting input of the second trigger, the single input of which is connected to the sixth input of the memory unit, the fifth input connected to the zero inputs of the first and second triggers, the first input of the third register and the zero input of the third trigger, the counting input of which is connected to the fourth input of the memory unit, the output of which is connected to the single output of the third a trigger whose unit input is connected to the output of the OR element, whose inputs are connected to the outputs of the first group of elements AND, the first inputs of which are connected respectively to the outputs of the third register, the second input of which is connected to the output of the element And, the first and second inputs of which are connected to the single outputs of ne - first and second triggers, respectively, the third input of the second register is connected to the output of the first register, the first input of the corresponding element AND of the first group, the first group of outputs of the second register is connected with the first inputs of the corresponding elements of the second group and with the second inputs of the corresponding first. elements of the first group, the second output with the second input of the corresponding element AND of the second group, with the third input of the third register and with the second input of the corresponding first element AND of the first group of elements And, the fourth inputs of the third register-a are connected to the corresponding outputs-and the corresponding second inputs of the corresponding elements AND the second group of elements.

3  Device pop 1, otli-  chyu. This is because the phase setting block contains the first and second registers, the reversible counter, the decoder, the first, second and third delay elements, the first second and third pulse shapers, the OR-NOT element, the trigger, the keys, the first and second KPI elements, the first, the second and third elements And, nepBbtfi the input of the phase setting unit is connected to the first input of the first register, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the first output of the phase setting unit, the first input of which is also connected to the soda of the first form l pulses and the first delay element, the output of which is connected to the first inputs of the first AND elements, the outputs of which are connected to the first inputs of the second register, the outputs of which are connected to the outputs of the OR-NOT element, to the first inputs of the keys and to the second inputs of the first And elements, respectively, the third inputs of which are connected to the output of an OR-NOT element, the first inputs of the second elements AND and the first element OR, the second and third inputs of which are connected respectively to the second and third inputs of the second register and the outputs of the third el And respectively, the inputs of which are connected respectively to the outputs of the reversible counter, the first and second inputs of which are connected to the outputs of the second elements AND, respectively, the third input with the output of the first element OR, the output of the first pulse shaper is connected to the second inputs of the second elements And, the third inputs of which are connected to zero output of the trigger, the unit output of which is connected to the second input of the first register and the second output of the phase setting unit, the unit input of the trigger is connected to the output of the second form The pulse generator, whose input is connected via the third delay element to the output of the second OR element and via the third pulse shaper — to the zero input of a trigger; the second input of the phase setting unit is connected to the input of the second delay element, the outputs of which are connected to the second inputs of the keys, respectively, whose outputs are connected with the inputs of the second element OR.  The invention relates to discrete information transmission systems used in seismic exploration.  In this case, it is envisaged to connect the device with each other and with the central station to which information is transmitted for further recording and processing.  Known digital receiving device containing the first, second, third and fourth regenerators, the delay element, analog-to-digital Converter, counter-register, driver shift with logic control, depth sensor and analog seismometer, the outputs of which are connected to the inputs of analog-to-digital converters, the first and the second outputs of which are connected respectively with the first inputs of the counter-register and the shift driver, the second one of which is connected to the output of the first regenerator and the delay element, output cat The first is connected to the input of the second regenerator and another input of the analog-digital converter, the output of the shifter is connected to the second input of the counter-register, the output of which is connected to the single input of the OR element, the second input of which is connected to the output of the third regenerator, and the output to the fourth input regenerator, the outputs of the second and fourth generators are respectively the first and second outputs of the digital receiving device as a whole, the inputs of the first and third regenerator are the first and second inputs A device riemnogo.  The known device has the disadvantage of low potential noise immunity, since it can only work on special cable oil-filled communication lines, and it does not work on real communication lines (for example, a pair of wires). maybe due to the lack of the necessary linear nodes.  Known switching device.  designed to control and record the central data post coming from the data collection posts, containing a transmission line connecting the central post with each data collection post, a device designed to input a series of command pulses into the transmission line, a receiver located at each collection post .  Device for data entry collection points in the transmission line 2j.  The disadvantages of this device are low functional reliability, lack of functional control capabilities due to the adopted method of transmitting seismic signals, the need for two communication lines.  The closest in technical essence to the present invention is a device for transmitting and receiving information, comprising an output encoder, a control unit, first, second, third and fourth registers, a divider, a first and second delay element, a counter, a switch, a reset command driver, a decoder, generator, data loss detector, the input of which is connected to the input of the device and to the input of the decoder, the first and second outputs of which are connected respectively to the first input of the first register, divider, the first input of the first ele The delay and shaper of the reset command, the output of which is connected to the first input of the counter, the second input of which is connected to the generator output, the first output to the second and first inputs of the first and second delay elements, respectively, and the first input of the second register, respectively, the second input to which the second output of the counter, and the first inputs are connected to the outputs of the third register, the first input of which is connected to the output of the divider, and the second inputs to the outputs of the first register, the output of the data loss detector is connected the third input of the first delay element, a first output connected to the first input of the fourth register, the second input of which is connected to the bus. digital data, and the output is connected to the first input of the switch, the second input is connected to the output of the second register, the third input is connected to the output of the control unit, the input of which is connected to the second output of the first delay element, the output of the device is connected to the output of the output encoder, the first and second inputs connected respectively with the output of the switch and the output of the second delay element sj.  The disadvantages of the known device are in the information redundancy of the transmitted message words, which reduces the real message transfer rate in the transmitted pulse series.  It is necessary to have a synchronized sequence in the information word, which reduces the transmission rate.  In addition, if one of the devices connected in series with each other fails, it is impossible to determine the location of the failure and to check the correctness of information recording in the central device due to the continuous transmission of information and the absence of two-way communication with devices located nearby.  The purpose of the invention is to increase the speed of information transfer.  . This goal is achieved by the fact that a first decoder, a generator, an output encoder, a control information block, a generator, an output encoder, a control information block, a second input the register is connected to the first input of the device, the output to the first input of the output encoder, the input of the first decoder is combined with the first input of the information loss detector, the second decoder is additionally added, m ti, modulator, the phase setting unit, the first and. the second amplifiers, the first input and output of the first amplifier dual connection being connected to the second input and the first output of the device, the second input and the second output corresponding to the modulator output and the first inputs of the information loss detector and the first decoder, the first and second inputs which are connected respectively to the first inputs of the memory unit and the phase setting unit, the first and second outputs of which are connected respectively to the second and third inputs of the memory unit, the output of which is connected to the second input output The fourth encoder, the fourth input of the memory unit, the second input of the phase installation unit, the first input of the control unit and the first input of the second decoder are connected to the generator output, the output of the second decoder is connected to the second input of the control unit and the fifth input of the memory unit, the sixth input which is connected to the fifth output by the control unit, the second output of which is connected to the second input of the information loss detector, the third output to the modulator input, the fourth output to the third input of the register, the first input to which is connected to the third input Control, the first output of which is connected to the second input of the second decoder, the third input of which is connected to the output of the second amplifier, the first input of which is connected to the output of the output encoder, the first output and the second input respectively of the second output and the third input of the device.  The memory block contains the first, second and third triggers, the first, second and third registers, the AND element, the first and second group of AND elements, the OR element, the first input of the memory block is connected to the first input of the first register, the second input of which is connected to the first input the second register and the zero output of the first trigger, the single input of which is connected to the second input of the memory unit, the third input of which is connected to the third input of the first register, the second input of the second register, and the counting input of the second trigger, whose single input It is connected to the sixth input of the memory block, whose fifth input is connected to the zero inputs of the first and second flip-flops, the first input of the third register and the zero input of the third flip-flop, the counting input of which is connected to the fourth input of the memory block whose output is connected to the single output of the third flip-flop whose single input is connected to the output. an OR element whose inputs are connected to an OR element output, the inputs of which are connected to the outputs of the first group of elements AND whose first inputs are connected respectively to the outputs of the third register, the second input of which is connected to the output of the AND element, the first and second inputs of which are connected to the single outputs of the first and the second trigger, respectively, the third input of the second register is connected to the output of the first regis. tra, the first input of the corresponding element And the second group of elements And and the second input of the Corresponding element And the first group, the first group of outputs of the second register connected to the first inputs of the corresponding elements And the second group and the second inputs of the corresponding first elements of the IC of the first group, the second output with the second the inputs of the corresponding element And the second group, with the third input of the third register and the second input of the corresponding first element And the first group of elements And, the fourth inputs of the third register th dineny to the respective outputs and respective second inputs of the corresponding element and the second element of the group.  The phase setting block contains the first and second registers, the reversible counter, the decoder, the first, second and third delay elements, the first, the second. and the third pulse formers, the element OR NOT, the trigger, the keys, the first and second elements OR, the first second and third elements AND, the first input of the phase setting unit connected to the first input of the first register whose outputs are connected to the inputs of the encoder, the output of which is connected to the first output of the phase setting unit, the first input of which is also connected to the inputs of the first pulse shaper and the first delay element, the output of which is connected to the first inputs of the first And elements, the outputs of which are connected to the first inputs of the second register, the outputs of which are connected to the outputs of the element IPI-NOT with the first inputs of keys and with the second inputs of the first elements AND, respectively, the third inputs of which are connected to the output of the element OR-NOT, the first inputs of the second elements AND and the first element OR, the second and the third the inputs of which are connected respectively to the second and third inputs of the second register and the codes of the third elements AND respectively, whose inputs are connected respectively to the outputs of the reversible counter, the first and.  the second inputs of which are connected to the outputs of the second And elements, respectively, the third input is with the output of the first OR element, the output of the first pulse shaper is connected to the second inputs of the second And elements, the third inputs of which are connected to zero. trigger output, a single output of which.  connected to c. the second input of the first register and the second output of the phase setting unit; the single trigger input is connected to the output of the second pulse driver, the input of which is connected through the third delay element to the output of the second OR element and through the third pulse driver to the zero trigger input connected to the input of the second delay element, the outputs of which are connected to the second inputs of the keys, respectively, the outputs of which are connected to the inputs of the second element OR.  FIG.  t shows a block diagram of the device; in fig.  2 - a functional block diagram of the memory; in fig.  3 — functional implementation of a phase setting unit; in fig.  4 functional implementation of the control unit; in fig.  5 - time diagram of the exchange of signals.  The device contains the first input 1 of the device, the amplifier 2, the first output 3 of the device, the modulator 4, the information loss detector 5, the first decoder 6, the memory block 7, the phase setting unit 8, the generator 9, the control unit 10, the second decoder 11, output coder 12, register 13, amplifier 14, second output of device 15, inputs 16 and 17 of device, first input of memory block 18, first and second registers 19 and 20 of memory block, trigger 21, second and third inputs 22 and 23 memory blocks, trigger 24, fourth and fifth inputs 25-26 of the memory block, third register 27, trigger 28, synchronize input 29, output 30 of the memory block, element OR 31, the second group of elements AND 32, element AND 33, the first group of elements AND 34, input 35 of the phase setting block, the first register 36 of the phase setting block, the decoder 37, output 38, the driver 39 pulses, delay element 40, elements AND 41, second register 42, element OR NOT 43, delay element 44 of register 13 with seismic sources, keys 45, elements AND 46, element OR 47, element AND 48, reversible counter 49, trigger 50 , the output of block 51, the generator of 52 pulses, the element 53 of the delay, the element OR 54, the driver of the 55 pulses, the input 56 block the dose settings, the first 57, the second 58 and the third 59 inputs of the control maintenance unit, the AND 60 element, the first and second flip-flops 61 and 62, the counter 63, the decoder 64, the first and second elements OR 65 and 66, the first and second, third-fourth and fifth outputs 67-71 of the control unit.  The timing diagram of the signal exchange for the case of sequential connection to the central station of the six transceiver-transmitting devices displays: 72, 73, 74, 75, 76, 77 - respectively, the exchange of messages in communication channels between the central station and the first transceiver transmitting device between the first and second devices, the second and third, third and fourth, fourth and fifth, fifth sixth devices; RFP - signal designations Start, CT - signal designation Start, P - signal designation Information separator, ID - and the formational part of the message.  FIG.  Figure 5 shows the time diagram of the operation of the device, where 78 — the formation of the transfer at the register output at the remaining positions is given a mapping of the occurrence of signals in time at the corresponding inputs or output according to the position number.  The device works as follows.  All devices for transmission and reception are connected in series with the central station, which is supplied for recording and processing information from seismic sensors. cove  The information system works afterwards. blowing way.  From the central station, it is transmitted to the first receiving and transmitting device, the Start signal, which passes through the second amplifier 14 and enters the second decoder 11, into which it is demodulated and decrypted.  At the end of the moment of receiving the signal. Starting from the output of the second decoder 1, a signal is taken, which is fed to the fifth input of memory block 7, resetting all elements of memory block 7 to the initial state and to the second input of control block 10, switching trigger 61 into the zero state and allowing the passage of the pulses of the generator 9 through the element 60 to the input of the binary counter 63, the signals from the first outputs of which are fed to the inputs of the decoder 64.  Through the second element OR 66 a pulse code sequence is formed, which is fed to the circuit of the modulating device 4.  Through the first amplifier 2, the generated signal is triggered.  Upon completion of the formation of the signal, the Start starts from the second output 68 from the element OR 65 to (Third input register 13 sequence of units, thereby pushing the contents of the register successively to the second input of the output encoder 12, and the Start sync sequence is stored in the register and information from the seismic sources supplied the third input 17 ycTpoiicTva, and at the same time at the time of the formation of the signal the Start flips the flip-flop 62 and the detector 5 is simultaneously inputted from the fourth output 70 on the second input to the loss data.  The word register 13 in the output coder 12 is converted into the form required for transmission over the communication channel and transmitted through the second amplifier 14 to the central station.  When the flip-flop 61 is triggered, the first output 67 of the control unit 10 and the third input of the second decoder 11 are given a signal that prohibits reception of the trigger signal during the transmission of information from register 13.  After a predetermined time has passed, the circuit of the data loss detector 5 sets the triggers 61 and 62 of the control unit 10 to the initial state. and writes to the register 13 Start signal.  The trigger 61, which is thrown to the single state, removes the prohibition from the third input of the second decoder 11.  The message from the subsequent device enters the input 17 through the first amplifier 2 to the input of the first decoder 6.  The decoder 6 demodulates the message and separates it into the Start signal and the information part of the message, which is fed to the first input of the memory block 7.  The start signal in the form of a synchro sequence arrives at the first input 35 of the phase setting unit 8, in which the incoming pulse of the synchro sequence of the first delay element 40 is delayed by half of its duration and the first pulse generator 39 separates the sync pulse.  The sync-frequency pulses from the generator 9 are continuously fed through the second input 52 of the phase setting unit 8 to the input of the second delay element 44, which delays each pulse for its duration.  Through one of the first elements AND 41, on the first and second inputs of which the pulses coincide, the output from the first delay element 40 and one of the outputs of the second delay element 4 is written to the corresponding bit of the second register 42.  The number of outputs of the second delay element 44, the first And elements and the size of the register 42 are determined by the accuracy of the phase adjustment, namely, if, for example, the accuracy of the adjustment is 10%, then the required number of outputs of the delay element 44 is 10. .  After the unit is recorded in the register 42, a potential appears at the corresponding output, which opens the corresponding key 45, and through the element OR-NOT 43 prohibits the passage of pulses from the first delay element 40 to the second register 42 via the third inputs through AND 41 elements .  The trigger 50 by the pulses formed by the second and third formers 52 and 55, switches to a new state after a time equal to half the duration of the synchrohclock frequency, t. e.  the third delay element 53 delays the pulse by this, time.  From the single output of the trigger 50, the clock pulses are shifted for gating to half the period relative to the pulses of the message layer from the previous device, fed to the second input of the first register, into which the Start sequence is written, and through the second output 51 to the third input of memory block 7 .  The elements 46 and 48, the reversible counter 49, control the phase departure and its adjustment.  The first driver generates a signal and if it coincides with one of the pulses from the outputs of the trigger 50, then the corresponding input to the counter 49 records-; or one is read.  The accuracy of the error in the phase discrepancy is made by the connections of the outputs of the counter 49 with the inputs of the third elements AND A8.  When an error code accumulates in the counter, the unit in register 42 shifts: to the left, if one occurs in phase; to the right - if the phase synchronization of the synchro-frequency from the syncro sequence.  At the same time over the element OR 47, the counter 49 is reset to the zero state.  In memory block 7, in-phase clock pulses are supplied to the third input 23, to the second input 22 of which a pulse is transmitted from the decoder 37 to the first input. 18 is the informational part of the word. messages, the sixth input 25 is allowed from the control unit 10, the transfer of messages, to the fourth input 29, the clock pulses are applied.  The information part of the message word enters input 18 into the first register 19, in which the information separator code is stored, and from its output, successively into the second register 20.  The first and second registers are filled, and at the outputs of elements AND 34 of the first group, potentials appear successively, respectively, at the outputs of those elements 34 that correspond to the most significant bit of register 20, filled with information.  After some time, the first and second triggers 21 and 24, with the arrival of the enabling signals from the phase setting unit 8 and the control unit 10, are transferred to the single states and through the And 38 element.  the second synchronization of the third register 27 is allowed to write the unit from the output of the corresponding element AND 34 to the corresponding bit of the third register 27.  The signal from the corresponding output of the third register 27 is fed to the first input of the element AND 32 associated with the output.  Thus, a chain of transmission of the information word is established with information separator from the corresponding output of the second register 20 through element 32, to the first input of which an enabling signal was fed from register 27 through the element OR to the single input of the third trigger 28, from output 30 of which the relayed word is removed with its own synchronization frequency of the generator 9 and is fed to the first input of the encoder 12 via the input 20 and 27 to the initial state, and the information separator code is written to the register 19.  The code signals in the output coder are modulated and fed through the second amplifier 14 to the communication channel for reception by the central station.  Similarly, the process of reception and transmission occurs in other devices of reception and transmission in the circuit Their serial connection with the central station.  The effectiveness of the proposed device may be as follows.

in a way. If, in a known device, is transmitted from each transceiver device, n clock pulses and n) information pulses (binary units), then the efficiency of the scrolling speed is defined as

n + m

m

where k is the number of serially connected receiving-transmitting devices.

Counting the information separator messages at the central station allows determining the failed receiving and transmitting device, since in this case the k-1 message Separator of information is not available when the k-ro device leaves.

57 J9

5B 67

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71 70

Fy

59

5

Claims (3)

1. A device for transmitting and receiving discrete information, containing a loss of information detector, the output of which is connected to the first input of the register, the first decoder, generator, output encoder, control unit, the second input of the register connected to the first input of the device, the output to the first input of the output encoder , the input of the first decoder is combined with the first input of the information loss detector, characterized in that, in order to increase the speed of information transfer, a second decoder, a memory unit, a modulator, and a setup block are introduced into it s, the first and second amplifiers, the first input and output of the first amplifier are connected respectively to the second input and the first output of the device, the second input and second output, respectively, to the output of the modulator and the first inputs of the information loss detector and the first decoder, the first and second inputs of which are connected respectively, with the first inputs of the memory unit and the phase setting unit, the first and second outputs of which are connected to the second and third, respectively, the inputs of the memory unit, the output of which is connected to the second input of the output encoder , the fourth input of the memory unit, the first input of the second decoder, the first input of the control unit, the second input of the phase setting unit are connected to the output of the generator, the output of the second decoder is connected to the second input of the control unit and the fifth input of the memory unit g, the sixth input of which is connected to the first output of the unit control, the second output of which is connected to the second input of the information loss detector, the third output - with the input of the module, the fourth output - with the third input of the register, with the first and third inputs of which the control unit is connected, vy output of which is coupled to a second input of the second decoder, a third input coupled to an output of the second amplifier, a first input coupled to an output of the encoder output, the first output and the second input - respectively to the second output and the third input device. h · ^ ·: © YU 2. The device according to claim 1, characterized in that the memory unit contains triggers, registers, groups of AND elements and an OR element, the first input of the memory unit is connected to the first input of the first register, the second input of which is connected to the first input of the second register and the zero output of the first trigger, the single input of which is connected to the second input of the memory block, the third input of which is connected to the third input of the first register, the second input of the second register and the counting input of the second trigger, the single input of which is connected to the sixth input of the memory block the input of which is connected to the zero inputs of the first and second triggers, the first input of the third register and the zero input of the third trigger, the counting input of which is connected to the fourth input of the memory block, the output of which is connected to the single output of the third trigger, the single input of which is connected to the output of the OR element, whose inputs are connected to the outputs of the first group of AND elements, the first inputs of which are connected respectively to the outputs of the third register, the second input of which is connected to the output of the And element, the first and second input They are connected to the unit outputs of the first and second triggers, respectively, the third input of the second register is connected to the output of the first register, the first input of the corresponding element AND of the first group, the first group of outputs of the second register is connected to the first inputs of the corresponding elements AND of the second group and with the second inputs the corresponding first elements AND of the first group, the second output - with the second input of the corresponding element AND of the second group, with the third input of the third register and with the second input of the corresponding first electronic ment and the first group element and fourth inputs of the third register are connected to respective outputs and respective second inputs of the corresponding AND gates of the second group elements. 3. The device according to claim 1, wherein the phase setting unit comprises first and second registers, a reversible counter, a decoder, first, second and third delay elements, first second and third pulse shapers, an OR-HE element , trigger, keys, first and second elements OR, first, second and third elements AND, the first input of the phase setting unit is connected to the first input of the first register, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the first output of the phase setting unit, the first input which is also connected to the strokes of the first pulse former and the first delay element, the output of which is connected to the first inputs of the first AND elements, the outputs of which are connected to the first inputs of the second register, the outputs of which are connected to the outputs of the OR-HE element, with the first inputs of the keys and with the second inputs of the first AND elements, respectively , the third inputs of which are connected to the output of the OR-HE element, the first inputs of the second AND elements and the first OR element, the second and third inputs of which are connected respectively to the second and third inputs of the second register and the outputs of the third elements AND, respectively, the inputs of which are connected respectively to the outputs of the reversible counter, the first and second inputs of which are connected to the outputs of the second elements AND, respectively, the third input with the output of the first element OR, the output of the first pulse shaper is connected to the second inputs of the second elements AND, third inputs which are connected to the zero output of the trigger, the single output of which is connected to the second input of the first register and to the second output of the phase setting unit, the single input of the trigger is connected to the output the house of the second pulse shaper, the input of which is connected through the third delay element to the output of the second OR element and through the third pulse shaper - with the zero input of the trigger, the second input of the phase setting unit is connected to the input of the second delay element, the outputs of which are connected to the second key inputs, respectively, the outputs which are connected to the inputs of the second OR element.