SU1413655A1 - Device for transmitting information via fibre-optic communication line - Google Patents

Abstract

The invention relates to fiber optic information transmission systems and can be used in control systems for automated equipment and robotic complexes. The purpose of the invention is to expand the field of application by providing interfacing with digital computers and increasing speed. The device contains on the transmitting side an analog I multiplexer, digital 2 multiplexer, analog-digital converter 3, 4 clock frequency generator, frequency divider 5, transmitter 6, including serial code H converter 7 optoelectronic module 8, shift register 9, fiber optical communication line 10, EXCLUSIVE OR AND element, NOT element 12, AND element 13, first switch 14, second switch 15, third switch 16, OR-NOT element 17, address counter 18, on the receiving side receiver 19, including opto Electronic module 20 and linear code converter 21 shift register 22, buffer register 23, address decoder 24, digital-to-analog converters 25 | -25 ″, register 26, shaper 27 of img record, including the element EXCLUSIVE OR 28, divisor 55 ( L

Description

i Li

with

O5 ate

ate

29 frequencies, element 30 and register 31. The device ensures the operation of the control system of a robotic complex or other technological equipment in two modes: in the copying mode, when analog and discrete sensors are directly used as the target devices, and automatically, when the algorithm and parameters control signals are set by a digital computer, and in the second case, the information transfer rate is practically unlimited. 1 h; item f-ly, 1 ill.

The invention is related to communication technology, namely to fiber-optic information transmission systems, and can be used to transmit and receive information in automation control systems using OiHHbiM equipment and robotic complexes.

The aim of the invention is to expand the scope of application of interface with the computer and increase the speed of the device.

The drawing shows a structural block diagram of the device.

The information transmission device over the fiber-optic communication line contains on the transmitting side analog multiplexer 1, digital multiplexer 2, analog-digital converter 3, generator 4 clock frequency, frequency divider 5, shredder 6, including serial code converter 7 and the optoelectronic module 8, the Esdvig register fiber-optic communication line 10, the element EXCLUSIVE OR 11, the element NOT 12, the element AND 13, the first switch 14, the second switch 5, the third switch 16, the element OR - NOT 17, the address counter 18, on the face one receiver 19, which includes an optoelectronic module 20 and a linear code converter 21, a shift register 22, a buffer register 23, an address 24 converter, digital-to-analog converters 25i-25, a register 26, a write pulse driver 27, which includes an EXCLUSIVE element OR 28, the frequency divider 29, the element And 30 and the register 31.

The device works as follows.

A clock frequency generator 4 generates pulses with a fixed frequency, which are fed to a clock input of a controlled frequency divider 5. From the first output of divider 5, pulses of frequency 2f arrive at the clock input of converter 7 of the code, from the third output pulses of frequency f arrive at the clock input of shift register 9 from the fourth output pulses of frequency f (N -) - l) arrive at the second input of the EXCLUSIVE element

0

the second input element And 13, the output pulses of the frequency f-Mui to the clock input of the analog-converter 3, and

so that time

OR AND and with the second do digital

is chosen

the conversion of block 3 was less than or equal to the cycle time of the shift register 9. If there is a logical “About at the input of the setting of the register 9 shift

It works in sequential input mode. From the output of the shift register 9, the sequential code goes to the first input of the EXCLUSIVE OR 11 element, and from the output of this element to the research input of the same register. When a EXCLUSIVE OR 11 pulse arrives at the second input at a frequency F (NH) from the fourth output of controlled divider 5 at frequency 5, the corresponding bit of the serial code is inverted. When the same pulse arrives at the second input of the element I 13 simultaneously with the presence of a logical "1" at the output of the shift register 9, the output of the element I 13 forms a pulse that converts the shift register 9 to the parallel input mode, when the last bit of the block 9 records the logical “O, which arrives at the last parallel input of the register 23. In accordance with the address code Thus, the cycle of operation of the parallel-serial register 9 shift contains 2 (N + 1) information bits, in the first and second half of the cycle rvye N bits are identical, and the latter, which acts as the synchronous clock is inverted - the first half of the cycle sync is transmitted as a logical "O, and the second - a logic" 1. In accordance with the foregoing, pulses with a frequency of f / 2 (N + 1) are formed at the output of the element And 13, which translate block 9 into the parallelo mode. ie,; ibHoro input, as well as run analog-to-digital converter 3 and is fed to the input of the counter 18 addresses. On the falling edge of these pulses, the code combination at the output of the counter 18 is changed.

addresses, in accordance with which in the operation mode without a digital computer, a cyclic interrogation is made of an analogue of OVExx and discrete sensors. From the output of the address counter 18, the code combination of the address is fed through the third switch 16 to the m.h sixth input of register 9, as well as to the address inputs of digital 2 and analog I multiplexers. The multiplexed analog signals from the output of the analog multiplexer 1 are fed to the analog input of block 3 and, after being converted into a digital code, through the second switch 15 are fed to the fifth input of the shift register 9. The multiplexed signals from discrete sensors from the output of qi (}) of level multiplexer 2 through the first switch .14 are fed to the fourth input of register 9. In the mode of operation of the device with a computer, when a signal arrives at the control input of the third switch 16, the address code combination with the digital computer through the third the switch 16 is fed to the sixth input of register 9 and to the address inputs of digital 2 and analog 1 multiplexers — discrete and analog sensors are polled in accordance with the algorithm specified by the computational by car. When control signals arrive at the control inputs of the second and first switches 15 and-14, analog information in digital form and digital information, respectively, through switches 15 and 14 is supplied from the computer to. parallel inputs of the shift register 9. At the same time, the necessary information transfer rate is set by the control action from the computer to the control input of the frequency divider 5. To ensure synchronous operation from a computer, an OR-NOT 17 element generates a pulse of the beginning of the sensor polling cycle (personnel pulse) when the output of the counter 18 of the address of the first code combination is present, and the pulses from the output of the I 13 element are also sent to the digital computer. that the information has been read and the device is ready to receive new information. From the output of the shift register 9, the serial code is fed to the information input of the converter 7 of the code, to the clock input of which pulses of frequency 2f are fed from the first output of the controlled body 5 frequency. The encoder 7 transforms the sequential code without returning to the well: п into linear self-synchronization code. which is fed to the input of the optoelectronic transmitter module 8, which converts electrical signals into optical signals. Opti; a cue signal from the output of the transmitting optoelectronic module 8 through the fiber; PTC link 10 enters NC; Optoelectron receiver module;

Most importantly, reverse formation. From the output of the receiving optoelectronic module 20 linear self-synchronization code is fed to the input of the Converter 21 code

d which converts it to a serial code without returning to July and allocating the clock frequency. The serial code and clock pulses from the outputs of the converter 21 of the code are accessed on the corresponding inputs of the shift register 22, which has - | 2 parallel outputs, and thus, at its first and last outputs, the code send bits with the same sequence number 5 will be simultaneously found. .In the e-element EXCLUSIVE OR 28 of block 27 of the write pulse shaper, a bitwise comparison of the corresponding bits of the code message from the first and second parts of the transmission cycle occurs. In their non-identity, at the output of the EXCLUSIVE OR 28 element, the logical "Uac" is the arrival of the next clock pulse at the first output of the register 31 also appears logical "1 and divider 29

converges to zero. The output divider 29

logical frequencies are only 1 in the case where the N bits in the first and second half of the transmission cycle will be identical. With the arrival of a sync pulse, which is constantly inverted, the outputs of element 30 EXCLUSIVE OR 28 and frequency divider 29 at the same time appear logical "1 and, thus, at output of element And 30 - too. With the arrival of the next clock pulse, a write pulse 35 is formed at the output of the buffer register 23, the information from the first outputs of the shift register 22 is written into the buffer register 23. If the code message contains an error from the first and second parts of the transmission cycle, the format of their 1 bits does not match - the record in the buffer register 23 does not occur. From the second output of the buffer register 23, the address code is fed to the input of address decoder 24, which distributes the write pulses into the d cell of the register 26 of digital signals and digital-to-analogue converters 25i-25 ". The information input of the register 26 is connected to the third output of the buffer register 23. In accordance with the address code information from this, the output of the buffer register hp 23 is recorded in certain cells of the register 26 and stored at its outputs during the cycle of changing the address code. From the first output of the buffer register, 23 information is fed to the information inputs of the digital-analog converters 25i-25. In accordance with the address code, the information is written into the register of a specific digital-to-analog converter 25i-25 ", converted into an analog signal and stored at the output of the digital-: analog converters 25" -25p during the address code change cycle.

Thus, the device provides the operation of the control system with a robotic complex or other technical equipment in two modes: copying, when the AMIOG and discrete sensors are directly used as master signals, and in the automated mode, when the algorithm and parameters "Control keys are set by the computer, and in the second case the information transfer rate is practically:

ten

Claims (2)

1. A device for transmitting information via a fiber-optic communication line, which contains sensors, an analog-digital converter, switches, a transmitter, the output of which is connected via a fiber-optic communication line; on the receiver side with the receiver input, the shift register, the second output is a digital-to-analogue converter, is: connected to the second input so that, in order to expand the P, the first input of the application area  The shear master is connected to the second pulse burner, the first output of the shear master is connected to the second input of the write pulse former, the group interface with the computer and the following: to extract the speed of the device, they are entered into it on the transmitting side of the analog 30; the shift register registers are connected to a multiplexer and a digital multiplexer corresponding to the group of inputs of the buffer circuit; , 1.гп1гм1Л1г-1: register, the last output of the output group  shift, elements EXCLUDE-:; The shift and the shift is connected to the third input of NECH OR, NOT and AND, clock generator, recording pulse generator frequency, frequency divider, address counter, trip ic, / in P1PIULI, and zniei, the first element OR NOT, the generator output of the buffer register is connected to the volume frequency connected to the first input 35 The information inputs of the TFAN analogue converters, the second and the third outputs of the buffer register are connected respectively to the information inputs of the address decoder and register, the group of address inputs of which and the address inputs of digital-to-analog converters are connected to the corresponding outputs of the address decoder, the outputs qi The analogue converters and register outputs are third and fourth, respectively. the frequency divider, the second input of which is the first control input of the device, the first output of the frequency divider is connected to the transmitter's clock input, the information inputs of the transmitter, AND elements, NOT, and the EXCLUSIVE OR link with the output of the shift register, the second and third outputs of the frequency divider are connected corresponding to the first entrances; analog-to-digital converter and shift register, the fourth output of the divider is 45 outputs of the device, the tots are connected to the clock inputs of the elements EXCLUSIVE OR and AND, the outputs of the elements EXCLUSIVE OR; and are NOT connected respectively to the second 2. The device according to claim 1, characterized in that the recording pulse shaper contains an EXCLUSIVE OR element, a frequency divider, the AND element and the register, and the third inputs of the shift register, the fourth, first inputs of the frequency divider and the fifth and fifth inputs of which are connected ; The hirs are the first input of the first and second write pulse inputs respectively, the second input of the switch, the output of the third switch of the frequency switch is connected to the first connected to the sixth input of the register shift-output register, the second output of which and the combined address inputs anapo-o is the output of the former. the tax and digital multiplexers, - jg pulse recording, the first and second inputs EXCLUSIVE OR elements are respectively the second and third inputs of the write pulse former, the outputs informational inputs of which are connected to the outputs of the respective sensors, the output of the element I is connected to the seventh input 0 the shift register, to the second input of the analog-digital converter, to the input of the address counter, and is the first output of the device; the outputs of the analog and digital multiplexers are connected respectively to the third input of the analog-digital converter and the first input of the first switch, the second input of the first commutator, and The first inputs of the second and third switches are respectively the second, third and fourth control: device inputs, the third input of the first; the switch and the second inputs of the second and third switch They are the first, second and third information inputs of the device, the third input of the second switch is connected to the output of the analog-digital converter,. the output of the address counter is connected to the third input of the third switch and to the input; an OR-NOT element whose output is 0 with the second output of the device, on the receiving side, a shift register, a buffer register, an address decoder, a write pulse driver and a register are entered into it, the first output of the receiver is connected to the first    the first input of the shift shear is connected to the second input pulse recorder, the first output of the shift shear is connected to the second input of the write pulse former, the group ; the outputs of the register shift are connected to the corresponding group of inputs of the buffer: register, the last output of the group of outputs 71413655g an EXCLUSIVE OR element and a deliberately output of an EXCLUSIVE frequency signal element through the AND element connected OR connected to the third input of the rivers to the second input of the register and the non-direct histor.