SU1674385A1 - Communication system tandem office remote control unit - Google Patents

Abstract

The invention relates to telecommunications technology. The purpose of the invention is to increase the reliability of telecontrol. The set of input units at the transmitting station 1, at all intermediate stations 14 and at the receiving station 36 allows, as part of the intermediate station 14, a receiving part consisting of the receiving register 26, the decoder 18 and the decoder 19, the generator 25 clock pulses, trigger 20 and the buffer register 24, as well as having a transmitting part consisting of the shift register 21, the clock pulse generator 17, the address register 22, the stop signal registers 29 and 31, to form a digital sequence for transmission regardless of the presence of syncro catch the last intermediate station or the time of the occurrence. This does not require transferring the intermediate station 1 to the end mode and vice versa. The device according to claim 2 of the invention is characterized by the execution of a gate signal generator. 1 hp f-ly, 1 ill.

Description

one

(21) 4750777 / 24-09

(22) 10/16/89

(46) 08/30/91. Bul M; 32

(72) L.I.Bragovka and A.YULAPIN

(53) 621.396.664 (088.8)

(56) USSR Author's Certificate N 1467766, cl. H 04 B 3/46, 1987.

(54) DEVICE FOR TELECONTROL OF INTERMEDIATE STATIONS OF THE COMMUNICATION SYSTEM

(57) The invention relates to telecommunication engineering. The purpose of the invention is to increase the reliability of telecontrol. The set of input units at the transmitting station 1, at all intermediate stations 14 and at receiving station 36 allows, as part of an intermediate station 14, a receiving part consisting of a receiving register 26. a decoder 18 and a decoder 19, a generator of 25 clock pulses, trigger 20 and buffer register 24, as well as having a transmitting part consisting of a shift register 21, a generator of 17 clock pulses, an address register 22, registers 29 and 31 of the sgop signal, form a digital sequence for transmission regardless of the presence of sync signals of the previous intermediate station or the time of their occurrence. This does not require transferring the intermediate station 1 to the end mode and vice versa. The device according to claim 2 of the invention is characterized by the construction of a building signal generator. 1 ep f-ly, 1 ill.

cl

WITH

The invention relates to a technique of telecommunications and can be used during telecontrol of a communication line with intermediate stations installed on it. The purpose of the invention is to increase the reliability of telecontrol Figure 1 shows the structural scheme of the proposed device; Fig. 2 shows an embodiment of a building signal generator.

The device for telecontrol of the intermediate stations of the communication system contains (FIG. 1) at the transmitting station 1 a sync signal register 2, a data register 3, a stop signal register 4, a delay line 5, an address register 6, an And 7 element, a clock pulse generator 8, a detector 9 alarm signals, address shaper 10, counter 11, gate signal shaper 12, shift register 13, at each intermediate station 14 element I 15, delay line 16, first generator 17 clock pulses, decoder 18 sync signals, decoder 19 stop signals, trigger 20, registr 21, shift register 22, address generator 23, address generator 24, a strobe signal generator of the second

25-cycle pulses receiving register

26 shift, buffer register 27, data register 28, first stop signal register 29, stop signal generator 30, second stop signal register 31, HE element 32. alarm signal detector 33, clock register 34, counter 35, at receiving station 36 receiving shift register 37, data register 38, clock generator 39, trigger 40, sync decoder 41, brake light decoder 42.

ABOUT

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1SL

Shaper 24 of the strobe signal at each intermediate station contains the element NOT 43, the first block 44 of the And elements, the shaper 45 of the code, the second block 46 of the And elements, the counter47, the trigger 48.

The device works as follows.

In registers 2, 3, 4 transmitting stations

I and all intermediate stations 14 permanently recorded the synchronization code, and in registers 6 and 22 the address code formed (for example, dialed and recorded manually using switching elements of the switches) by the driver 10.

In the data registers 38, 3 and 28, the information coming from the detectors 9, 33 of the alarm signals is recorded (Fig. 1).

In driver unit 30, a stop signal code is recorded, which at transmitter station 1 is recorded in register 4, at intermediate station 14 in registers 29 or 31.

Information is transmitted from transmitting station 1 as follows.

From the output of the first generator 8, the clock pulses arrive at the input of the counter

II with the recalculation coefficient

Мз n - - (m + k) N + I, where N is the total number of stations.

With the arrival of the Mz clock at the output of the counter 11, an impulse appears, which, entering the input of the record of the shift register 13, allows the recording of information from its information inputs. In this case, the recording is made:

clock signal to bits D0-Dn

addresses in the Dn + i-Da bits, where a n + m.

state data in bits, where b n + m + k

stop signal in bits, where with n + m + k-H.

After the time At required to record information in the shift register 13, a high potential pulse will be sent from the output of the delay line 5 to the input of the gate signal generator 12, allowing the formation of a high potential gate signal, TL duration This duration, as mentioned above, is determined by the amount of information transmitted by the device in terminal station mode and is

 + (rn + k) +. From the output of the imaging unit 12, a pulse with a duration of Ti is fed to the second input of the element I 7, thereby allowing the passage of clock pulses to the clock input of the register 13, thus promoting a digital information signal to the communication line,

After Mi cycles at the output of the driver 12, the potential is low and the reading of information into the line stops.

After the counter has counted 11, the new number of clocks in register 13 will be

recorded updated data and transfer again.

The intermediate station operates as follows.

With the appearance at the output of the communication line

(input of the device installed at the intermediate station) of the digital information signal during the time regardless of the state of the generator 12 and the counter 11 the decoder 18 extracts the synchronization signal and generates a start signal of the second clock generator 25, from the output of which the clock pulses arrive at the second clock input of the receiver shift register 26, which ensures that digital information with a duration W of cycles W (m + k) (L-1) is written into it, which is input to the input.

Dedicated decoder 19 stop signal flips trigger 20 in a single

a high potential appears at its output, which, arriving at the first input of the buffer register 27, where a difcep can be additionally installed, permits the recording of information arriving at its second inputs from the outputs of the receiving register 26. The same signal sets the zero state the first register 29 and, having passed through the element NOT 32, prohibits the recording of information in it, a,

arriving at the first input of the second register 31, permits the recording of information from the driver 30 of the stop signal into it. At the same time, the second clock pulse generator 25 is stopped.

At the same time, a high potential from the output of the trigger 20 goes to the fourth input of the driver 24, which, in accordance with this signal and the station address, coming from the driver 23, will provide

the formation at its output signal duration TI.

Ti1 n + (m + k) L + I t IN / Tsg. The recording signal received from the output of the counter 35 to the input of the record of the register 21,

provides recording of information from its information inputs into it. In this case, the recording is made:

the clock signal in bits D0-Dn addresses in bits Dn + i-Da, where a n + m

state data in bits Da + i OH. where b n + m + k

addresses and data from previous stations to bits DbH-Dd, where d git + k + W - n + m + k-Km + k) (L-1)

stop signal in bits Dd + 1-Dg. where g n + rrMk (-W-H-n "(m + k) LH

After the time At required to record information into the register 21, from the output of the delay line 16, a high potential pulse will be sent to the third input of the driver 24, which allows the formation of a high potential gate signal of duration T | .

From the output of the gate signal generator 24, a high potential is transmitted to the second input of the element 15, thereby allowing the passage of the clock clock Mi from the output of the first generator 17 to the clock input of the register 21, thus promoting the digital information signal to the input of the communication line.

Through the Mi ticks at the output of the gate signal generator 24, a low potential prohibits the transmission of information to the communication line.

In this case, a high potential pulse from the output of the delay line 16 arrives at the first input of the trigger 20 and transfers it to the zero state. At the output of the trigger 20 a low potential appears and the whole device is reset.

If, during operation, the intermediate or transmitting station fails (or the link is broken), the digital sequence nearest to it will not be received at the intermediate station 14. After writing to register 21 and transmitting data on the status of previous stations received last time before the accident, trigger 20 will remain in zero state.

Scientific research institute

The low potential from the trigger output 20 prohibits the recording of information in the register 31 and the buffer register 27. At the same time, this element NOT 32 generates a signal to set the buffer register 27 and the first register 31 to the zero state and allows writing the STPP signal to the second register 29

Therefore, a low potential will be present at the third input of the imaging unit 24, and when a signal arrives at its input from delay line 16, a gate signal with duration Ti will be formed

Ti n-fm + k} that is, as at transmitting station 1.

Intermediate station 14 will begin to transmit this data only about the state of its funds and will essentially work as terminated.

Reception at receiving station 36 is as follows.

When the stop signal is received by the decoder 41, rpnirep 40 is triggered and starts generator 39, clock pulses from the output

which provide reception of the signal on the line and its entry into the receiving register 37 After receiving the sgop-sishala with the decoder 42, the generator 39 stops and the data from the receiving register 37 is rewritten

in the data register 38

From the output of the register 38, information may be transmitted to a display device or a device for further processing of information.

At the transmitting station 1 signals g

detector 9). The register 3 arrives at the sixth input of the register 13 of the shift register and generates a stop signal and transmits through the register 13 to the communication line the generator 8 controls the operation of the register 3. elements 7 and counter 11 The signal from the output of the generator 10 through the register In enters the second input of the register 13

At the intermediate station 14, the synchronization signal is recorded in register 34 and is fed to the sixth input of the register 21 Cm from the output of the former 23 enters the globalization 24 and through the register 22 to the second input regis 2 2 to the clock input of which

the signal comes from the output of the element 15

The main purpose of shaper 24 (fit 2 | is the formation of a control signal (a variable pulse momentarily (.ti) whose duration depends on

from the sequence number (intermediate route addresses 14 in the communication line and the presence in the buffer register 27 of the received digital sequence from the previous intermediate channel) This signal is interworking; test for the clock input of the register 2 1 of the specified number of pulses from the first re-measure mpa 17

The duration of the control pulse (signal 1 and and about which potential) of the output

the parent 24 and therefore the number of f / b clock pulses passing through the bandwidth is determined by the expression

r-.-Mi t n (t V) I l where i is the period of the following clock pulses

n Sync signal.

m is the address width,

k data size.

1 - stop signal width:

L is the sequence number of the intermediate station (determined by the station address).

Moreover, the value of L is determined by the signal arriving at the fourth input of the former 24. At a high potential at this input, L is equal to the sequence number of the intermediate station, and at low, regardless of the address of the intermediate station, L 1.

The duration of the strobe signal in this case

Ti r n-t (m + kH,

This is the number of clock pulses designed to transmit only the information that is generated at this intermediate station 14.

When a low potential arrives at the fourth input of the imaging unit 24, a high potential signal (control signal) will be present at the output of the HE element 43. This signal provides connection (via the first block 44 I elements) of the imaging unit 45 of the address code 1 to the installation inputs of the counter 47. Thus when the signal arrives at the third input, the formers 24 and the control input of the counter 47 will write the coefficient of the count to it.

Ki1 n + (m + k) -M.

At the same time, the signal from the third input of the imaging unit 24 transfers the trigger 48 to a single state and at its output a high potential signal is obtained. After counting the K pulses arriving at the counting input of the counter 47 from the output of the first generator 17. A signal is output at the output of the counter 47, which transfers the trigger 48 to its initial state and a low potential is established at its output. Thus, at the output of the imaging unit 24, a strobe signal with a duration of Ti will be formed, corresponding to Ki t ktgtum mmpULSEM.

When a high potential input arrives at the fourth input, the address generator 23 will be connected to the installation inputs of the counter 47 (via the second block 45 of the I elements) and when the recording signal arrives, the ESS1E coefficient will be written to the counter 47

Ki - n-i (rmk) L-H

and subsequently formed a strobe signal with duration Tb

Thus, shaper 24 provides the formation of a signal permitting the transmission of a digital sequence from the shift register 21 to the communication line (the passage of the clock pulses to the register 21, and the number of these pulses is determined by the number of the intermediate station in the communication line and the presence or absence of the received information in the buffer register 27).

Claims (2)

1. Device for telecontrol of intermediate stations of the communication system, containing a clock pulse generator and an address generator at the transmitting station, at each intermediate station an alarm signal detector, the first generator 0 clock pulses, shift register, address driver and clock decoder, and at the receiving station are serially connected receiving shift register, whose input is the output of the communication system, data register, characterized in that, in order to increase the reliability of the telecontrol, at the transmitting station A sync signal register, a stop signal register, and therefore a connected counter, whose input is connected to the output of a clock generator, a delay line, a strobe signal shaper, an And element, are entered. the second input is connected to 5 output clock generator and the shift register, the output of which is the input of the communication system, the address register, the input and output of which are connected respectively to the output of the address generator and the second input of the shift register, the third, fourth and fifth inputs of which are connected respectively to the outputs the counter, the clock register and the stop signal register are connected in series with the alarm signal detector and the data register, the recording input and output of which are connected respectively to the output of the clock generator and estym input shift register at each intermediate 0 stations are entered in the clock register, the second clock generator, the first input is connected to the output of the clock decoder, the data register is information, the recording input and the output are connected respectively to the output of the alarm signal detector, the output of the first clock generator, and the first input of the shift register, register addr oa informational 0 input, recording input and output of which are connected respectively with the output of the address generator, the output of the first clock generator and the second input of the shift register connected in series 5 receiving p of his shift, the clock input of which is connected to the output of the second clock generator, pulses, and the buffer register whose output is connected to the third input of the shift register, connected in series with the counter of the input of which is connected to the output of the first clock pulse generator, delay line, gate driver the signal, the clock input of which is connected to the output of the first clock pulse generator, and element I. the second input and output of which are connected respectively to the output of the first clock generator pulses and clock input of the shift register, stoplight shaper, serially connected brake decoder, the input of which is connected to the inputs of the sync signal decoder and the receiving shift register and is the output of the communication system, trigger, the second input of which is connected to the output of the delay line, element NOT and the first register of the stop signal, the input of the zero setting and the output of which are connected respectively with the trigger output and the fourth input of the shift register, the second register of the brake signal, the input of the zero setting, the first input and output which are connected respectively to the output of the element NOT, to the trigger output and the fifth input of the shift register, the sixth and seventh inputs of which are connected respectively to the output of the clock signal register and the counter output, the output of the stop signal generator is connected to the second inputs of the first and second stop signal registers, the output of the element is NOT connected to the setup input of the zero buffer register, the trigger output is connected to the second input of the buffer register, the second input of the gate signal generator and the setup input of the second g generator of clock pulses output the address driver is connected to the third gate driver input, the shift register output is the communication system input, and at the receiving station entered the stop signal decoder, serially connected clock decoder, the input of which is connected to the input of the brake signal decoder and to the input of the receiving shift register, trigger and generator clock pulses, the output of which is connected to the clock input of the receiving shift register, the output of the brake signal decoder is connected to the second inputs of the data register and the trigger. 2. The device according to claim 1, that is, so that the gate signal generator at each intermediate station contains a code generator, the series-connected element NOT and the first block of elements I, the second input of which is connected to the output shaper code, serially connected second block of elements And, a counter, the input of which is also connected to the output of the first block of elements And, and the trigger, the output of which is the output of the strobe signal generator, the first input of which is the combined first input of the first block The AND elements and the input of the NOT element, the second counter input is connected to the second trigger input and is the second input of the gate signal generator, the third and clock inputs of which are respectively the second input of the second block of AND elements and the counter input of the counter. Editor N. Call yes Compiled by E. Golub Techred M. Morgental FIG. Z Proofreader V. Girn to