SU1334151A1 - Device for information exchange - Google Patents

Abstract

The invention relates to computing technology and can be used for the exchange of information between computers in the presence of an annular communication channel. The aim of the invention is to expand the field of application of the device by providing access to a common ring communication channel. The device comprises a computer communication unit 1, a control signal decoder 2, a mode register 3, a control unit 4, a communication unit 5 with a line, a switch 6, a frequency divider 7, a pulse generator 8, a transceiver unit 9. 13 il. W (L with 00 4 f2 01 - Fig. 1

Description

The invention relates to computing and can be used to exchange information between a computer group in the presence of a circular communication channel.

The purpose of the invention is to expand the field of application of the device by providing access to a common ring communication channel.

FIG. 1 shows the block diagram of the device proposed; Fig. 2 is a functional diagram of a computer communication unit; figure 3 is a functional diagram of the node receivers; 4 is a functional diagram of an interrupt node; figure 5 is a functional diagram of the node transmitters; in fig. 6 is a diagram of a control signal decoder j in FIG. Functional diagram of a mode register; 2o radios, reset line 44, connected

Fig. 8 is a functional block diagram of the control unit; Fig. 9 is a functional block diagram of a communication unit with a line; in fig. 10- functional diagram of the transceiver unit; FIG. 11 shows the timing diagram of the operation of the communication unit with the line; FIG 12 is an information message format; on Fig - the structure of the ring network using the proposed device,

. The device contains a computer unit 1, a control decoder 2, a mode register 3, a laziness unit 4, a communication unit 5 with a line, a tator 6, a frequency divider 7.

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torus 8 pulses and transceiver block 9. In Fig. 1, the first group of inputs-outputs 10 of the computer communication unit 1 is indicated, the input-output 11 and 12 of the device for connection to the communication line, the Computer Communication Unit 1 (Fig 2) contains a receiver node 13, node 14 interrupts and node 15 transmitters. In FIG. 2, data lines and addresses 16 are indicated, the interrupt provision input line 17 (R1), the line 18 is numbered. , the initial installation (NUC), the line of 19 byte operations (KBIT), the line 20 of input operations (CWERT), the line 21 of output operations (CWITCH), the active device synchronization line 22 (XIA), the line 23 of access to external devices (HLC), output interruption provision line 24 (CGSR1), interruption request line 25 (CTPR), passive device synchronization line 26, second group of inputs / outputs 27 of block 10, data bus 27 j associated with a group

35

with the first output of a communication unit with a computer, a transmission flag line 45, a switching flag line 46 and a status flag input 47.

Receiver node 13 (FIG. 3) contains receivers 48-63, decoder (LH) 64, trigger 65-67, HE element 68, FIG. 3 shows the output line 69,

Interrupt node 14 (FIG. 4) contains triggers 70-75, elements 76-81, and E-NOT elements 82-85, elements OR 86-88, transmitters 89-93, delay element 94. In FIG. 4, the output lines 95-98 of the interrupt node 99 of the interrupt node 14 are connected to the address and data bus 16.

Node 15 transmitters (figure 5) contains the transmitters 100-i11, multiplexer (M) 112, the element AND NOT 113.

The decoder 2 control signals (Fig, 6) contains the elements NOT 114-120 element AND 121, the elements OR 122 and 123, the element OR-NOT 124, the element AND-NOT 125, the decoder 126, Fig, 6g marked the first output line 12 first output 128 of the decoder 2 control signals, second output line 129, second output 130 of the control decoder, third, quarter and fifth and output lines 131-134, respectively.

The mode register 3 (FIG. 7) contains the trap diggers 135-138, the AND-HE element 139. In FIG. 7, an input 140 of a mode register marker 140, a second output 141 and a third output 142 are indicated,

Control unit 4 contains shift registers 143 and 144, decoders 145 and 146, the first trigger 147 ficks

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information inputs / outputs of a computer communication unit, operation readiness input 28, receiver readiness line 29, transmitter readiness line 30, second state identification and data input 31, data reading line 32, receiver status reading line 33, state reading line 34 neither the transmitter, the line 35 of the receiver status record, the line 36 of the transmitter state record, the first input 37 of the state identification and data, the device selection line 38 (FBG), the line 39 of the operation indication (Enter), the second bit line 40 of the address devices line 4 first bit adr ESA device, the second output 42 of the communication unit with a computer, line 43 sign of byte operation

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with the first output of a communication unit with a computer, a transmission flag line 45, a switching flag line 46 and a status flag input 47.

Receiver node 13 (FIG. 3) contains receivers 48-63, decoder (LH) 64, trigger 65-67, HE element 68, FIG. 3 shows the output line 69,

Interrupt node 14 (FIG. 4) contains triggers 70-75, elements 76-81, and E-NOT elements 82-85, elements OR 86-88, transmitters 89-93, delay element 94. In FIG. 4, the output lines 95-98 of the interrupt node, the output 99 of the interrupt node 14 are connected to the address and data bus 16.

Node 15 transmitters (figure 5) contains the transmitters 100-i11, multiplexer (M) 112, the element AND NOT 113.

The decoder 2 control signals (Fig, 6) contains the elements NOT 114-120, the element AND 121, the elements OR 122 and 123, the element OR-NOT 124, the element AND-NOT 125, the decoder 126, FIG. 6 g is the first output. line 127, first output 128 of the decoder 2 control signals, second output line 129, second output 130 of the control decoder, third, fourth and fifth output lines 131-134, respectively.

The mode register 3 (FIG. 7) contains the trap diggers 135-138, the AND-HE element 139. In FIG. 7, an input 140 of a mode register marker 140, a second output 141 and a third output 142 are indicated,

Control unit 4 contains shift registers 143 and 144, decoders 145 and 146, the first trigger 147 fic0

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tions zero, synchronization trigger 148, flag trigger 149, address trigger 150, marker trigger 151, second zero fixation trigger 152, multiplexer 153, counter 154, first element And 155, fourth element And 156, sixth element And 157, second element And 158, the third element AND 159, the element OR 160, the element OR-NOT 161, the elements NOT 162 and 163, the elements 164-166 of the delay and the fifth element AND 167.

8, the second information input 168, the sync input 169, the third output 170, the fourth output 171, the second output 172, the first information input 173 and the fifth output 174 are indicated.

The 5-link-to-line unit contains receivers 175 and 176, trigger 177 ,. the element OR 178, the element NOT 179, the elements And 180 and 181 and the transmitters 182 and 183.

In Fig.9 marked outputs 184 and

185 transmitters 182 and 183, connected to a second output for connecting to a communication line, a third output

186 devices, outputs 187 and 188 of receivers 175 and 176 for connection to a channel input. Transceiver unit 9 contains: it node. 189 local control, control register node 190, data buffer 191, transmission unit 192, and reception unit 193. Transceiver unit 9 may be performed, for example, on an IC51 IC51 chip K580. The device performs data exchange between the parallel input-output of the computer through the device inputs-outputs 10 and the serial communication line of the ring structure, obtained by connecting the output 12 of the previous device to the input 11. of the subsequent device. In such a system, the generator 8 of one of the devices is used as a common clock signal generator of the entire system, and the frequency divider 7 determines the common frequency of the clock signals. In this case, the switching control of the sync signals is performed from the computer and is accomplished by inputting 1 computer to a certain bit of phase switching (trigger 135) of the register 3 of the device mode — the clock source through input 27. Register 3 of the mode, computer connection unit 1 and inputs - outputs 10 devices. The signal arriving in this case from the output 46 of the register 3 of the mode to the control input of the switch

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51. 6, switches the clock signals from the output of the generator 8 through its divider 7 to its output. In the other devices, the phase switching bit of the register of the 3 modes is set to O by a signal, arriving at its input 44 Reset. At the same time, from the third output of the communication unit 5, through the switch 6, to the gate input of the unit 5 receives the allocated clock signals.

The communication unit 5 with the line encodes the informational and synchronizing signals arriving in the line as a self-synchronizing ternary tandem through the two-wire communication lines 184 and 185, (see the time diagram in FIG. 11).

Serial messaging can be divided into 7 fields (Fig. 12). The first field, located at the beginning of the list, is used to place the code. a flag (01111110) indicating the beginning of the message. The second and third fields are respectively used to place the address codes of the receiving and transmitting devices between which information is exchanged. The fourth field is used to place the control code and indicates the type of message (informational or control), as well as the Acknowledgment Symptom received or rejected by the recipient information message sent to him. The fifth field contains the message length code in bytes. The sixth field contains the information part of the package. The seventh field contains the marker code, upon receipt of which the device can break the ring, stop relaying data, and send its message to it. The device provides code independence of data by bitstaffing, the mechanism of which is implemented in block 4 of the exchange control. The device can operate in the following four modes: priority output, output by marker, input and retransmission.

The priority output mode is used to send a successive ring line to the marker code, as well as, if necessary, a control message — an acknowledgment (erroneous or error-free) of an information message. This mode is triggered by the write 1 command to the transmit flag (trigger

138) register 3 modes. In this case, the mode register 3 switches the device from the retransmission mode to the information output mode from the device to the serial ring communication line. The signal from the output 141 of the register 3 is fed to the input of the control unit 4 which in this case disconnects from its output 172 the data sent to its input 168 and connects the data to the input 173 of the block. Thus, the input of the communication unit 5 with the line will receive data from the output

173 transceiver unit 9 via unit g control unit 4 at its output 140

4. The marker code is entered from the computer in block 9 through the device inputs-outputs 10, the computer-connected unit 1 via the input-outputs 27. When each transmitter strobe clock signal arrives at the input 174 of block 9, the marker is sequentially outputted. output 173 of block 9 to line 12. Similarly to the output of the marker, the output of the control message, which contains only the first four fields of the package, is also performed. After issuing the entire message from the second output of communication unit 9 via control unit 4 and communication unit 5 to the line 12 (or after issuing the marker), the computer enters O into the bit of the transmission indication (trigger 138) of register 3 modes similarly to that considered. The device switches from transmission mode. Efe retransmission mode,

In this mode, the serial code received at the device input 11 is decoded in the communication unit 5 with the line. When this occurs, the separation of information and sync signals. The information signal from the first output of block 5 passes through the shift register 143 of block 4 and enters the information input of block 5. The synchronization signal from the third output of block 5 enters the gate input of block 5, where these signals are encoded again into a serial code and output to 12 devices. In this mode, all the ringing information passes through the shift register 143 of the exchange control block 4, which with the help of its decoder 145 analyzes this formation to identify control sequences such as marker, flag, address, and others.

Output mode by marker is used to output from a computer

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A signal appears that enters the register 3 modes and, by conjunction with a single output bit of the transmission resolution of the register 3 modes, sets the 1 bit of the transmission sign (trigger 138) of the mode 3 register, thus switching the device from the retransmission mode to the output mode . The occurrence of a low level signal at the input block readiness (141) of the block allows the delivery of a flag from the second output of block 9 through the control block 4 to the link block 5 with the line 12. The output speed is determined by the clock frequency of the transmitter strobe at the fourth input (174) block 9. When generating a single signal level of the transmitter readiness via line 30 at the first output 28 of block 9, which is fed through block 1 of communication with a computer to the inputs-outputs 10 of the device ,. The computer loads in block 9 the next symbol of the information message. The operation of the device in this mode is similar to the work in the priority output mode. The difference between these two modes consists only in the difference in the methods of their initiation, which provide access to the serial communication line. After issuing the entire information message to the output I2 of the computer, O enters into the bit with the sign of the transfer of the register 3 modes similarly considered, thereby prohibiting. Go to serial data from the second output of block 9 and switch the device to retransmission mode.

In the input mode, information is received addressed to the device and a computer connected to it, coming from the device input 11 via the device inputs-outputs 10 to the computer. Addressing the receiver can be individual, group and broadcast.

an informative message line (see Fig. 12). In this case, the computer enters 1 in the resolution of the transfer (trigger 136) register 3 modes. Under the control of the control signal decoder 2, the first character of the information parcel, the flag, is sent to the communication block 9 via the second group of inputs and outputs 27. The device then waits for the receipt of the marker code from the serial line while still in the relay mode. Upon receipt of a marker code in

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A signal appears that enters register 3 of the mode and, by conjunction with a single output of the resolution of transfer of the register of mode 3, sets the transfer indication (trigger 138) of register 3 of the mode to 1, switching the device from the retransmission mode to the output mode The occurrence of a low signal level at the input, readiness of reception (141) of block 9 allows the delivery of a flag from the second output of block 9 through block 4 of control, block 5 of communication with the line to line 12. The output speed is determined by the frequency of the clock signals of the transmitter on the fourth The mouth of the input (174) of the unit 9. When generating a single signal level of the transmitter readiness via line 30 at the first output 28 of the block 9, which is fed through the computer connection unit 1 to the device inputs-outputs 10 ,. The computer loads in block 9 the next symbol of the information message. The operation of the device in this mode is similar to the work in the priority output mode. The difference between these modes consists only in the difference in the methods of their initiation, which provide access to the serial communication line. After issuing the entire information message to the output I2 of the computer device, O enters into the bit the sign of the transfer of the register 3 modes similarly to that considered, thereby prohibiting. Go to serial data from the second output of block 9 and switch the device to retransmission mode.

In the input mode, information is received addressed to the device and a computer connected to it, coming from the device input 11 via the device inputs-outputs 10 to the computer. Addressing the receiver can be individual, group and broadcast

7

Noah. The broadcast address belongs to all devices connected to the ring., And all these devices simultaneously receive the transmitted message with the broadcast address code in the address field of the receiver. When passing the flag code, which is the sign of the beginning of the message, through the control unit 4, a single signal level is generated at its fourth output (171), which arrives at the third synchronous input of block 9 (171), allowing the last reception of data arriving at the information input of unit 9. But data reception begins only when unit 4 recognizes its individual, group or broadcast address. In this case, block 4 permits the passage of sync signals from its sync input to the third output and then to the second synch input of block 9. After accumulating the first character of the received data in block 9, the latter generates at its first output 28 via line 29 a receiver readiness signal in the computer through the unit 1 of communication with the computer and the inputs-outputs 10 of the device. Having received this signal, the computer enters the parallel code of the received symbol in block 9 via bi-directional inputs / outputs 27. The number of received symbols is determined by the fifth field (see Fig. 12) of the consecutive sending. Having received the number of characters specified in this field, the computer rewrites one of the control registers of block 9. The input mode is terminated and the device continues to operate in the relay mode. The input mode can be performed both simultaneously with the retransmission mode and simultaneously with one of the output modes.

Consider the work of individual units of the device.

The unit of communication with the computer interacts with the device with the computer.

In this case, the receiver unit 13 performs reception of control, address and information signals from the device inputs-outputs 10 using receivers 48-63. Using the address decoder 64 in the receiver node I3, the address code received from the computer is compared with the receivers 54-63 in the address part of the communication cycle with the address assigned to the device and the memory

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comparison result per trigger 65 Selection on the leading edge of the CI-IA signal coming from the output of receiver 53. On triggers 66 and 67, two lower bits A2 and AI address addresses, which determine the choice of one of the device's internal registers, are stored. Receivers 56-63 are gated with a signal Read receiver data (CSP).

Interrupt unit 14 generates control signals for the exchange of information between the device and the computer. Thus, when inputting or outputting information and selecting this device at the output of the element AND 81, a signal is transmitted which, through the delay element 94 and the element OR 88, enters the input of the transmitter 91. As a result, a synchronization signal is generated at the output of the transmitter 91 and the output 26 of the interrupt unit 14 the passive CSIT device; the interrupt node 14 outputting an interrupt request signal. The computer enables the device to operate in the interrupt mode by inputting I to the resolution for interrupting a transmitter. Trigger I triggering 70 or 71 is performed when a single signal is received from a certain bit — bus 27. I triggering in triggers 70 and 71 is gated with unit levels of control signals, respectively, at inputs 36 and 35 of interrupt unit 14. The occurrence of a single signal of readiness of the transmitter from the input 30 of the node 14 of the interruption through the element 76 on the gate input of the trigger 72 will cause the latter to be set to one. In doing so, the trigger 74 blocks the further spreading of the interruption grants. At the same time, a single signal from the inverted output of the trigger 74 causes a signal to be generated to terminate the TPR using the element OR 97, and the transmitter 93 at the output 25 of the interrupt unit 14.

Similarly, the same sequence of operations is carried out when the interrupt is processed by the receiver readiness signal, which is inputted to input 29 of interrupt unit 14.

The decoder 2 control signals generates the control signals of the device. When accessing the device, the Select, Input, Output, A2, and Al signals are received correspondingly

Zeno via lines 38, 39, 69, AO p 41 to the input of the decoder 2 control signals, determine the internal registers of the device, the type of operation to be performed and the control signals of the transceiver unit 9.

In register 3 modes, when a single signal is received from the first record entry (36) of the register 3 mode, the latter are set to the gate inputs of the flip-flops 135, 13 and 138 from the corresponding bits of the bus 27 arriving at the information inputs of these triggers. The trigger 137 enables the operation of the code-independent mechanism in control unit 4. This mechanism is required so that the information message does not come across control character codes, in particular, flag code 01111110 and marker code 11111110. To enable the code independence mechanism, information message symbols are written to the computer-controlled byte commands, during which the trigger 137 is set in 1. Writing the flag and marker symbols is performed by word-processing commands, at which the trigger 137 is set

in O ,, prohibiting m. code-dependent mechanism for the output of these characters.

The control unit 4 controls the exchange of information with the ring line, the hardware realizes the discovery of the code-dependent data at the expense of the bit rate, the transmission control by the recognition of the control marker and the subsequent reading of the message, the control of the recognition neither its address and reception permission, retransmission of received messages. In the absence of their messages

dp transmissions block 4 completes retransmission transmissions of going further, five unit

SLUTS10 messages, 1 access 1, to its input 168 under the control of the clock signals received from its input 69. The data recorded in register 143 through multiplexer 153, arrive at output 172 of the block. If the decoder 145 decrypts the flag codes 01.111110, then the triggers 148 and 149 will go into one state. The trigger 149 enables the operation of the counter 154 by permitting the passage of pulses from the output of the element 165 through the element AND 155. And to the counting input of the counter 154. After counting by the counter

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of the bits in the information field, the transmitting device generates a zero bit, and the receiving device, when receiving five consecutive units, removes the next zero. The case of the need to insert a zero is recognized by the decoder 146. If the code-independent mechanism is enabled, the signal from the output of the decoder 146 And 157 enters the information input of the trigger 152. When the output signal of the 164 delay element rpjjirrep 152 is set to 1. The zero signal from in

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154 eight bits to the gate input of the address trigger 150 receives a signal. If the decoder 145 has decrypted in the address field of the receiver the code of its in-. individual, group or broadcast address, then a single signal from the third output of the decoder through the element And 156 sets the trigger 150 in a single state. The signal from the output of the trigger 150 enters the second input of the AND 159 element, allowing the clock signals from input 169 of block 4 to pass through the elements 164, 165 and 159 to the third 170 output of block 4, which is the beginning of data reception by block 9. If the decoder does not recognize the address code The message device of the communication line does not accept. After counting by the counter 154 eight bits, following 1x behind (|) lag, the signal from the output of counter 154 through the delay element i66 also goes to the gate input of the trigger 149 of the flag and through the OR 160 element to the input to the installation of the counter 154. With this signal the trigger 149 of the flag and the counter 154 is set to O. When the code of the marker decoder 145 recognizes the zero signal from its fourth output sets to 1 the trigger 151 of the marker. Thus, the shift register 143 and the decoder 145 operate as data is entered and retransmitted. The shift register 144 and the decoder 146 operate in the output. In the output, multiplexer 153 switches to the second output U72) of block 4, the output of the shift register 144, to the information input of which serial data are received for output from the first information input 173 of block 4.

In block 4 of the control, the code independence mechanism is implemented: after

transfers going further, fi single

of the bits in the information field, the transmitting device generates a zero bit, and the receiving device, when receiving five consecutive units, removes the next zero. The case of the need to insert a zero is recognized by the decoder 146. If the code-independent mechanism is enabled, the signal from the output of the decoder 146 And 157 enters the information input of the trigger 152. When the output signal of the 164 delay element rpjjirrep 152 is set to 1. The zero signal from in111

In this case, the trigger output 152 enters the input of the elements 158 and 167, blocking the sequential information input on the shift register 144, as a result of which the low bit of the shift register 144 is entered into the zero bit. At the same time, the transmitter strobe at the fifth output (174) of the block is also prohibited from moving the next bit of data from block 9 for one clock cycle. In the next cycle, the signal from the output of the decoder 146 through the element 157 sets the trigger 152 to O and the output will continue normally by the way ..

When receiving, the need to skip the zero bit is recognized by the decoder 145. In this case, the signal from its first. The bdro output enters the information input of the trigger 147. When the clock signal arrives at the gate input of the trigger 147, the latter is set to 1 and the zero signal from its inverse output blocks the clock signal passing through the third output unit 4 for one clock cycle. the clock strobe of the receiver of block 9 is forbidden; and the reception of the zero bit inserted during the transmission of the bit. In the next stroke, the trigger 147 is set to O and the input continues as usual.

The unit 5 of communication with the line when outputting provides the encoding of information and synchronizing signals into a serial code, and upon inputting - decoding a serial code into

informational and synchronizing

signals. The information and synchronization signals are combined with the help of HE elements 179, AND 180 and 181 for simultaneous transmission via transmitters 182 and 183 via communication lines 184 and 185 (Fig. 11). Lines 184, 187 and 185, 188 are pairwise connected and receivers 175 and 176 receive and invert the transmitted signals. At the same time

trigger 177 is allocated information

signal, and on the element OR 178 a sync signal. Transceiver unit 9, when outputting, converts an eight-bit parallel code to its bi-directional inputs-outputs 27 into a serial code issued to its second output (173) through data buffer 191 and transmission unit 192. Consistent

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the issuance of this code occurs when each sync signal of the transmitter arrives at the fourth synchronization input (174) of the block. When entering, block 9 receives a serial code arriving at its information input (168) under control of the receiver clock signals arriving at the second synchronous input (170), forming a parallel code in the block

 193 reception and sends it through the bus 194 and the buffer 191 data to its bidirectional input-output) I 27.

The control register black 190 is intended to store the mode control word, the sync symbols, the instruction instructions. The local control unit 189 ensures the operation of unit 9 in accordance with the instructions received.

Transmission block 192 receives a parallel eight-bit code from data buffer 191, converts it into a serial code, and outputs it to the second output of the block. After the next eight bits, a block 192 of transmission over line 30 produces a single transmitter readiness signal. Block 193

The reception transforms the serial code arriving at its information input under the control of the receiver clock signal and results in the generated parallel code.

Implemented in the proposed device, the possibility of not only individual, but also multicast and broadcast addressing, which allows many subscribers to simultaneously receive the transmitted message, significantly increases the capacity of the exchange.

Form ula invention

A device for information exchange, comprising a transceiver unit, a decoder of control signals, a communication unit with a line, a pulser generator I1, a frequency divider and a computer communication unit, the group of information and control inputs-outputs of which are connection to data buses and computer control, a group of information inputs-outputs of a computer communication unit is connected to a group of information outputs-inputs of a transceiver unit, the reset input of which is connected to the first output

a computer communication unit whose operation readiness input is connected to the first output of the transceiver unit, the mode input and the recording input of which are connected to the first and second outputs of the decoder control signals, the third and fourth outputs of which are connected respectively to the first and second inputs of the identification No other communication with the computer, the second output of which is connected to the input of the decoder of control signals, the output of the pulse generator. connected to the input of the frequency divider and the first synchronization input of the transceiver unit; the first output of the communication unit with the line is connected to the information input of the transceiver unit; the second output and the channel input of the communication unit with the line are the channel output and the input for the connection to the communication line. , characterized in that, in order to expand the field of application, by providing access to a common ring communication channel, a control unit, a mode register and a switch are inserted into the device, with the information group the ion inputs of the outputs of the computer communication unit are connected to a group of information inputs of the mode register, the first and third outputs of the computer communication unit are connected with the reset inputs and the bit input of the mode byte register, the first output of which is connected to the input of the state neither a computer communication unit, the first and second inputs of the register of the mode register are connected respectively to the third and second outputs of the decoder of control signals, the second output of the mode register is connected to the Ready inputs of the receiver of the transceiver units the control, the first output and the input of the byte of the control unit are connected respectively to the marker input and the third output of the mode register whose fourth output is connected to the control input of the switch, the first and second information inputs of which are connected respectively to the output of the frequency divider and the third output of the unit the connection with the line, the strobe and informational inputs of which are connected respectively with the outputs of the switch and the second output of the control unit; the third, fourth

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and the fifth outputs of which are connected respectively to the second, third and fourth synchronization inputs of the transceiver unit 9 whose second output is connected to the first information input of the control unit, the inputs of the Broker and the recording of which are connected respectively to the first output of the communication unit with the computer and the second output of the control signal decoder The second information input and the synchronization input of the control unit are connected respectively to the first and third outputs of the communication unit with a line, and the control unit contains two shift registers Stra two decoder, two trigger locking zero, the synchronization triggers flag addresses, marker, the multiplexer, the counter, the six elements. And, the element OR, the element OR-NOT, two elements NOT, three delay elements, and the information input of the first shift register is connected to the second information input of the control unit and to the first input of the first decoder, the remaining seven inputs of which are connected to the seven lower outputs the first shift register, the eighth most significant output of which is connected to the first information input of the multiplexer, the first output of the first decoder is connected to the information input of the first zero fixing trigger, the output of the first delay element and connected to the input of the second delay element and with the synchronous inputs of the first and second zero-firing triggers, the input of the first delay element is connected to the input of the first delay element and connected to the synchronization input of the control unit, the output of the first element is NOT connected to the gate inputs of the first and second shift registers and the output of the second delay element is connected to the first inputs of the first, second and third elements And, the second output of the first decoder is connected to the single inputs of the trigger trigger and flag, the output The synchronization trigger is connected to the quarter output of the control unit, and the flag trigger output is connected to the second input of the first element And and the first input of the fourth element And whose output is connected to the information input of the address trigger, the output of which is connected to the second input of the third element And, tre 1

The third input is connected to the output of the first zero fixing trigger, and the output of the third element I is connected to the third output of the control unit, the readiness input of the receiver is connected to the control input of the multiplexer, the output of which is connected to the information output of the control unit whose recording input is connected to the first input of the IL-NOT element, the output of which is connected to the zero inputs of the synchronization triggers, flag, marker, address and the first input of the OR element, whose output is connected to the counter installation input, the input of which is connected to the output of the first element AND, the output of the counter soy; inn with the input of the third delay element, the output of which is connected to the synchronous inputs of the address and flag triggers and with the second input of the first OR element, the third and fourth outputs of the first decoder are connected respectively to the second input of the fourth element AND and the single input of the marker triggers, the transceiver of which is connected to the first output of the control unit, the reset input of which

one with the second input of the element OR NOT and the input of the second element NOT whose output is connected to the zero inputs of the first and second zero-firing triggers and to the installation inputs of the first and second shift registers, the first information input of the control unit is connected to the first input of the fifth element And, the output of which is connected to the information input of the second shift register and the first input of the second decoder, the remaining seven inputs of which are connected - € seven junior outputs of the second shift register, the eighth most senior you which is connected to the second information input of the multiplexer, the output of the second decoder is connected to the first input of the sixth element I, the output of which is connected to the information input of the second zero fixation trigger, the output of which is connected to the second inputs of the second and fifth elements AND to the second input of the sixth element I, and the output of the second element I to the fifth output of the control unit.

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FIG. 12

Claims (1)

Claim 45 Information exchange device comprising a transceiver unit, a control signal decoder, a communication unit with a line, a pulse generator, a frequency divider and a computer communication unit, 50 which information-control input-output group is a group of input-output devices for connecting to data buses and computer control, the group of information inputs of the outputs of the communication unit with the computer is connected to the group of information outputs and inputs of the transceiver unit, the reset input of which is connected to the first output 13341 computer communication unit, the operation readiness input of which is connected to the first output of the transceiver unit, the mode input and recording input of which are connected respectively to the first and second outputs of the control signal decoder, the third and fourth outputs of which are connected respectively to the first and second inputs of state and data identification there was a connection with a computer, the second output of which is connected to the input of the decoder of the control signals, the output of the pulse generator. connected to the input of the frequency divider and _{15 to the} first synchronization input of the transceiver unit, the first output of the communication unit with the line is connected to the information input of the transceiver unit, the second output and the channel input of the communication unit with the line are respectively the channel output and input of the device for connecting to the communication line, characterized in that, in order to expand the scope of application by providing access to a common ring communication channel, a control unit, a control unit, a mode register and a switch are introduced into the device, and the information group the input inputs of the outputs of the communication unit with the computer is connected to a group of information inputs of the mode register, the first and third outputs of the communication unit with the computer are connected sag responsibly to the reset inputs and the discharge input of the sign of the mode byte-register, the first output of which is connected to the status sign of the communication unit with the computer , the first and second inputs of the mode register record are connected respectively to the third and second outputs of the control signal decoder, the second output of the mode register is connected to the Readiness inputs of the receiver of the transceiver and control units Lines, the first output and the byte sign indication of the control unit are connected respectively to the marker discharge input and the third output of the mode register, the fourth output of which is connected to the control input of the switch, the first and second information inputs of which are connected respectively to the output of the frequency divider and the third output of the communication unit with the line the gate and information inputs of which are connected respectively to the outputs of the switch and the second output of the control unit, the third, fourth 51 .14 and the fifth outputs of which are connected respectively to the second, third and fourth synchronization inputs of the transceiver unit, the second output of which is connected to the first information input of the control unit, whose reset and write inputs are connected respectively to the first output of the communication unit with the computer and the second output of the control decoder signals, the second information input and the synchronization input of the control unit are connected respectively to the first and third outputs of the communication unit with the line, and the control unit contains two shift reg Istra, two decoders, two zero-fixing triggers, synchronization, flag, address, marker, multiplexer, counter, six elements triggers. AND, an OR element, an OR-NOT element, two NOT elements, three delay elements, the information input of the first shift register connected to the second information input of the control unit and to the first input of the first decoder, the remaining seven inputs of which are connected to the seven junior outputs of the first shift register ', the 30th eighth senior output of which is connected to the first information input of the multiplexer, the first output of the first decoder is connected to the information input of the first fix trigger. zero, the output of the first delay element 35 is connected to the input of the second delay element and to the sync inputs of the first and second triggers of zero fixing, the input of the first delay element is connected to the input of the first delay element and connected to the synchronization input of the control unit, the output of the first element is NOT connected to the gate inputs first and second. _ shift registers, and the output of the second 45 delay element is connected to the first inputs of the first, second and third elements AND, the second output of the first decoder is connected to the unit ₅ θ inputs of the synchronization triggers and flag, the output of the synchronization trigger is connected to the fourth output of the control unit, and the output of the trigger flag is connected to the second input of the first element And and the first input of the fourth 55 ,, of the And element, the output of which is connected to the information input of the address trigger, the output of which is connected to the second input of the third And element, 1334151 The 16th input of which is connected to the OUTPUT 'of the first zero-fixing trigger, and the output -1 of the third AND element is connected to the third output of the control unit, the receiver readiness input of which is connected to the control input of the multiplexer, the output of which is connected to the information output of the control unit, input records of which are connected to the first input of the OR-NOT element, the output of which is connected With the zero inputs of triggers for synchronization, flag, marker, address and the first input of the OR element, the output of which is connected to the installation input of the counter, whose input is connected to the output of the first AND element, the output of the counter is connected to the input of the third delay element, the output of which is connected to the clock inputs of the address and flag triggers and to the second input of the first OR element, the third and fourth outputs of the first decoder are connected single to the second input of the OR element and NOT NOT input of the second element, the output of which is connected to zero inputs of the first and second flip-flops ⁵ and fixation zero with adjusting inputs of said first and second shift registers, first information input unit councils eniya ₁₀ connected to the first input of the fifth AND gate, whose output is connected to the data input of the second shift register and the first input of the second decoder, the remaining seven inputs of which soedi15 yen -c younger family outputs the second shift register, the eighth oldest whose output is connected to second data input of the multiplexer , the output of the second decoder 2Q is connected to the first input of the sixth element And, the output of which is connected to the information input of the second zero-fixing trigger, the output of which is connected to the second inputs the odes of the second and, accordingly, with the second input of the fourth AND element and a single input of trigger markers, the output of which is connected to the first output of the control unit, the reset input of which FIG. 2 of the fifth element AND, the input attribute of the byte of the control unit is connected _ by the second input of the sixth element And the fifth output of the second element And is connected by the output of the control unit. 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