SU1693611A1 - Computer interface with communication line - Google Patents

Abstract

The invention relates to computer technology and can be used to exchange information between a PC and a local network and between a PC and an EC type computer. The purpose of the invention is to increase the reliability of receiving information of the device. A second main transmitter and receiver, a galvanic isolation unit, a fifth trigger, a controllable frequency divider and three elements OR NOT. The invention provides the implementation of the functions of the physical layer for the local network of a PC, and for the communication channel with the EC terminal station, as well as protection against low-frequency pickups and impulse noise in the communication line. The serial interface unit exchanges commands and data of the PC through the system bus, bit-by-bit enters and outputs the decoded data, issues a signal with the transmission reception permission, transmits to the PC a sign of the occurrence of a conflict in the communication channel. 3 il. Yo

Description

The invention relates to computing and can be used in the construction of local area networks of computers.

The purpose of the invention is to increase the reliability of receiving information.

Figure 1 shows the functional diagram of the device; 2 and 3 are timing diagrams of the device operation in the transmission and reception modes. The device (figure 1) contains a block 1 of the serial interface, the element EXCLUSIVE OR 2, the second element AND-NO 3, the counter 4, the first trigger 5, the elements OR-NOT 6 and 7, the first element AND-NO 8, main transmitters 9 and 10, galvanic isolation unit 11, trunk receivers 12 and 13, fifth trigger 14, second 15 and third 16 triggers, EXCLUSIVE OR 1.7 element, fourth trigger 18, third OR-NOT 19 element, controllable frequency divider 20 and setting chik 21 codes.

The galvanic isolation unit 11 is a pulse transformer consisting of three isolated windings. The first and second have a grounded midpoint winding and are connected to main transmitters and receivers, and a third is connected to the communication line. The code settingter 21 determines the data reception and transmission rate and is a set of jumpers or switches that issue a code in accordance with their installation. It is possible to use as a reference a parallel register code, the output code of which is set by software. Block sequential in

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The interface 1 exchanges information with a PC, converts data from a serial code to a parallel one in receive mode and back in transmit mode.

The device operates under the control of a PC. The network software of the PC consists of programs for implementing the functions of the local area network protocols and the program (driver) directly serving the operation of the device. The driver program sets the transmission or reception modes, sets the length of the transmitted or received words and the synchronization mode, issues words to block 1 for subsequent transmission to the communication line, analyzes the contents of the state register of block 1. At the same time, the availability of block 1 to receiving a word for subsequent transmission in the communication line, the presence of a signal or a conflict in the communication line, a sign of the end of reception of the word from the communication line and the presence of an error in reception. The software can be built on various algorithms depending on the specific applications of the device,

The device can operate both in the communication mode with the local PC network and in the communication mode with the EC 7920 terminal station, while ensuring the physical parameters of the PC information exchange signals corresponding to each mode. Before the transfer of information to the communication line begins, unit 1 issues a single potential (AND-NOT 8) to the NE-8 and OR-NOT 19 elements, which opens the AND-NE 8 opening element and prohibits the passage of the reset signal of the controlled divider 20 and counter 4 through the OR-NOT 19. A controllable divider 20, the division factor of which is determined by the code generator, generates pulses from a master clock at its input with a frequency corresponding to the transmission rate. At the outputs of counter 4, pulses of clock (fig.2b) and doubled clock frequency (figv) appear, causing appearance at the outputs of block 1 of the transmitted data bit by bit synchronously with the clock frequency (fig.2g). With the help of the EXCLUSIVE OR 2 element, the absolute phase modulation of the transmitted data occurs (Fig. 2e). Trigger 5 triggers modulated data to exclude short-term emissions that may occur due to the imperfect coincidence of fronts arriving at the EXCLUSIVE OR inputs of 2 clock and information signals. Coded data in the device operation mode in the local network from the forward and inverse outputs of the trigger 5 (Fig. 2g) is inverted on the elements OR-NOT 6 and 7 and fed to the main transmitters 9 and 10 (Fig. 2i, k). The amplified signal enters the galvanic isolation unit 11, from the output of which the bi-polar signal is fed to the communication line (Fig. 2L).

0 When the device operates in communication with the terminal station EC 7920 at the inputs of the elements OR NOT B and 7 through an open potential from the output of the sensor sensor 21 of the code AND-NOT 3 element and open

5 element AND-NOT 8 receives clock pulses (fig.2e). At the outputs of the elements OR-NOT 6 and 7, signals are generated (Fig. 2k, and) amplified in transmitters 9 and 10 and fed to block 11, from the output of which a two-polar signal is fed into the communication line. The parameters of this signal correspond to the parameters of the signal exchange of display devices with the terminal station EC-7920 (Fig.2l).

5 Before receiving information from the communication line, a low potential from the output of block 1 closes the AND-HE element 8, from the output of which the potential enters the inputs of the elements OR-NOT b and 7. Low potential from their outputs puts transmitters 9 and 10 into an inactive state the In addition, the low potential from the output of unit 1 permits the passage of reset pulses to a controlled divider 20 and a counter 4 from the output

5 flip-flop 18. The signal from the communication line (Fig. 3a) enters block 11, from the outputs of which the non-inverted and inverted signals generated by the constant component are fed to the inputs of receivers 12 and 13, respectively. These receivers are configured to operate from the input signal above level zero. When working in a PC network, a conflict may occur, i.e. simultaneous operation of more than one transmitter network, while the receiver 12 gives a high potential to the block 1. The appearance of a sign of conflict causes the termination of the transfer and its repetition over time. The signal from the output of the receiver 12 enters (figb, c) at the inputs of the trigger 14, from the output of which the received coded data is fed into block 1 (fig. 3g) and causes the low level trigger signal for triggering the triggers 15 and 16

5 from the output of block 1.

In order to increase the noise immunity, the received signal is gated on the trigger 15 by the clock system of the PC bus, which specifies the clock pulses. Received coded signal from inverse output

trigger 15 (FIG. 10) is fed to the input of the EXCLUSIVE OR element 17 and to the information input of the trigger 16, from the output of which the decoded data enters block 1 and to the input of the element EXCLUSIVE OR 17 (Fig.Ze). The positive differential from the output of the EXCLUSIVE OR element 17 (FIG. 3) sets the trigger 18 to one state. To the zero state, this trigger is transferred by an overflow signal from the output of counter 4 (FIG. 3), which occurs every time after a predetermined delay after reset. controlled divider 20 and counter 4, determined by the speed of the received information. The delay time depends on the frequency of the pulses at the input of the counter 4, which is determined by the division ratio of the controlled divider 20. The division ratio is determined by the code from the output of the code setting 21.

Thus, the trigger 18 generates the clock pulses (FIG. 3K), which accompany the received data and arrive at the input of unit 1, as well as through the element IL AND-EE 19, the controlled divider 20 and the counter 4 are reset (FIG. ZH). In block 1, the received data is converted into a parallel code and transferred to the PC via the system bus. The short impulse interferences in the communication line of positive or negative polarity (shown by dashed lines) (Fig. 3a) do not affect, since at the moment of the arrival of the impulse noise, both inputs of the trigger 14 have a low potential and this trigger does not change its state (fig.Zb.v).

Claims (1)

Invention Formula A device for interfacing a computer with a communication line containing the serial interface bpok, the group of information control inputs / outputs of which is a device input-output group for connecting to computer system buses, first trunk transmitters and a receiver, four triggers, setting device code, a counter, two NAND elements, two EXCLUSIVE OR elements, the first output of the first trunk receiver connected to the readiness input of the serial interface unit, the output of the test data of which is Connected to the first input of the EXCLUSIVE OR element, the output connected to the information input of the first trigger, the synchronous input of the second trigger is connected to the input-output group of the device, and you 5 10 15 20 5 0 5 0 5 0 5 move - with the information input of the third trigger and the first input of the second element EXCLUSIVE OR, the second input and output respectively of the third trigger connected to the direct output and the installation input of the fourth trigger, the inverse output and reset input of which are connected respectively to the synchronous input of the third trigger and the counter transfer output, the direct outputs of the third and fourth triggers are connected respectively to the information input of the serial data and the clock input of the serial interface unit, you The readiness of reception is connected to the reset inputs of the second and third triggers, characterized in that, in order to increase the reliability of the reception of the device, a second main transmitter and receiver are inserted into it, the galvanic isolation unit, the input-output of which is the input-output of the device connection to the communication line, fifth trigger, controllable frequency divider and three OR-NOT elements, with the direct and inverse outputs of the first trigger connected to the first inputs of the first and second elements OR-NOT, respectively, to the outputs the first and second main transmitters with the direct and inverse inputs of the galvanic isolation unit, the direct and inverse outputs of which are connected to the inputs of the first and second main receivers, the second output of the first and the output of the second main receivers are connected respectively to the installation input and the reset input of the first flip-flop, the output connected to the information input of the second flip-flop and the input of the receive request of the serial interface unit, the output of the transmission enable and the transmission synchronous input of which is connected respectively to the first inputs of the first AND-NOT element and the third element OR NOT and to the output of the counter frequency doubled, the output of the main frequency of which is connected to the synchronous input of the first trigger, the second inputs of the first and second elements OR-NOT connected to the output of the first element NAND, the second input connected to the output of the second element NAND, the first output of which is connected to the output of the setting unit code, and the second input - to the output of double frequency and the second input of the first element EXCLUSIVE OR, groups the code master and counting outputs, the counter input is connected respectively to the group of control inputs and the output of the controlled frequency divider, the counting input connected to the device's input-output group, and the reset input - to the OR-NOT input, the second input of which is connected to the counter reset and the output of the third element by the direct output of the fourth trigger. Phie.1 a 6 6 FIG. 2 LLLP jnjTJ-LrLTLri u Fig.Z