SU1180915A1 - System for switching device and interface - Google Patents

Abstract

1. A switching system of computing devices containing a switching device, m interface devices, a group of bidirectional data trunks, a line Signal of receiving data, a line / Sign of data output, a line Data continuation, inputs / outputs of data lines of a switching device through a group bidirectional data trunk lines are connected to the outputs / inputs of the data lines of the interfacing device, the inputs / outputs of the line Signal of receiving data and lines Sign of data output of the switching device of communication through the lines The sign of data reception and the sign of data output are connected to the same outputs-inputs of the coupler, line outputs. Continuation of data that is connected via the line. Continuation of data to the same input of the switching device of communication, the group of input-output ports of the main line of the switching processor is the same input-output. system, the input-output bus of the subscriber of the i-th device of interface (, t) is the same input of the bus of the subscriber's i-ro, which is C (L in order to increase data transfer due to the introduction of a synchronous exchange mode, a clock pulse generator, ha + 1 clock shaping units, lines, a blocking of a highway, a clock pulse line, a clock pulse output through a clock pulse line are connected to the system; pulses of sync pulse shaping blocks, data synchronization inputs of the commutation device. The communication and interface devices are connected to the outputs of the corresponding synchro pulses forming blocks. Line input The trunk of the switching device of the communication is connected via the Line blocking line to the corresponding outputs of the gateways. 2. A communications switching device containing a first through third counter, registers, trigger, first through

Description

the third group of elements OR, from the first to the eighth group of elements AND, the first and second elements OR, the first element AND, the outputs of the elements AND of the first group are connected to the first inputs of the elements OR of the first group, the outputs of the elements AND the seventh and eighth groups are connected to the first and second inputs OR elements of the third group, the outputs of which are the device data bus outputs, the output of the first element OR the line output Request for data transmission of the device, the forward output of the trigger is the output of the line State transfer request, different so that, in order to extend the functionality due to the independent transmission of data from any subscriber, a memory block, first to third amplifiers, transmitters, first to fifth amplifiers receivers, first to fourth elements NOT, second to the fifth elements And, the delay element, the first and second inputs of the second element And through the first and second amplifiers, the receivers are connected to the inputs of the lines Sign of data output and Sign of receiving data of the device, respectively, the first input of the third element And through the quarter ale The ent and the third amplifier-receiver are connected to the input of the continuation line of the device, the inputs of the second register through the fourth group of elements And the fourth amplifier-receiver are connected to the inputs of the data lines of the device, the first inputs of the first and fourth elements And, the first inputs of the third group of elements And and the input the delay element is connected to the synchronization input of the device data, the output of the delay element is connected to the first input of the fifth

the AND element and the control inputs of the fourth group of elements AND, the line input Blocking the main line of the device through the fifth receiver amplifier and the second element is NOT connected to the second inputs of the fourth and fifth And elements, the outputs of which are connected to the first and second inputs of the first OR element, inputs read and write memory blocks are connected to the inputs of the lines Record and Read devices, respectively, the input line of the initial sampling device

connected to the first inputs of elements of the And p of the group and through the third element. NOT to the first inputs of elements AND of the first group, the input of the line Address, the device channel is connected by the second inputs of elements AND of the fifth group, the third inputs of which are combined with the information inputs of the First Register and connected to the inputs of the device data buses, the input of the channel information line of the device is connected to the reset input trigger and write input of the first register, the outputs of which are connected to the first inputs of the elements And the sixth group, line inputs Reading the address and subscriber information of the device are connected to the first inputs of the elements And the seventh and the eighth group, respectively, the output of the first element is connected to the input of the counter, the outputs of which are connected to the second inputs of the elements of the first and seventh groups, with the first inputs of the elements of the second group, the outputs of the elements And the second and sixth groups through the second group of elements OR are connected to the second inputs of the elements And the third group, the outputs of which are connected to the inputs of the third register, the outputs of which through the first amplifier-transmitter are connected to the outputs of the data lines of the device, the output of the second register is connected to the second inputs of the el elements And the eighth group, the output of the second element And is connected to the second inputs of the elements And the sixth group, the third inputs of the elements And the seventh and eighth groups, the third inputs of the fourth and fifth elements And the first element is NOT the second inputs of the third element And elements And the second group and with the first input of the second element OR, the output of the third element AND is connected to the input of the trigger installation, the output of the second element OR is connected to the second input of the first element AND, the direct output of the trigger is connected to the second input of the second element OR in By stating the memory block, the information inputs of which are connected to the outputs of the OR elements of the first group, the first output of the memory element is connected to the third inputs of the AND elements of the sixth group, the fourth input of the fourth AND element and the second amplifier-transmitter - with the output of the device data output line , the second output of the memory element is connected to the fourth inputs of the elements of the eighth group, the fourth input of the fifth element I and through the third amplifier-transmitter with the output of the line Sign of receiving data of the device, output elements and fifth groups are connected to second inputs of the OR elements of the first group.

3. The interface device containing the first to third amplifiers-receivers, the first to the fourth amplifiers-transmitters, the decoder subscriber number j receiving and transmitting registers, from the first to the sixth elements AND, the first element OR, the first to the third elements NOT, prrvy the trigger, the delay element, the decoder input of the subscriber number and the information inputs of the receiving register through the first amplifier-receiver are connected to the inputs of the device data lines, the outputs of the receiving register are connected to the outputs of the device data buses, information Transmitter register moves are connected to device data bus inputs, characterized in that, in order to increase reliability by preventing information loss during data exchange in synchronous mode, the seventh and eighth And elements are entered into it, and the Element group from the second to the seventh elements OR The second to fifth triggers, the first inputs of the first element AND, the seventh element OR, and the input of the third element are NOT connected through the first amplifier / receiver to the line input. Sign Display device data, the output of the third element is NOT connected. with the first input of the fifth element AND, the first input of the second element AND, the second input of the seventh element OR, and the input of the second element are NOT connected via the second amplifier-receiver to the line input Sign of receiving data of the device, the output of the second element is NOT connected to the first input of the sixth element AND the input of the record of the transmitting register, the first input of the third element And, and through the delay element the first inputs of the fourth, eighth, second inputs of the first, second, sixth elements AND are connected to

device data synchronization output, the first input of the first element OR and the third input of the first element AND are connected to the forward input of the line Sign of entering information of the device, the second input of the first element OR and the third input of the second element AND are connected to the forward input of the line Sign of the information output of the device, input reset of the third trigger through the fourth element OR connected to the inputs of the lines New data is ready and Data Received devices, reset input of the fourth trigger through the seventh element And connected to the inverse inputs of the lines The sign of the input and the sign of the information input of the device, the output of the decoder number of the absolute is connected to the quarter inputs of the first and second elements AND, the outputs of which are connected to the installation inputs of the first and second triggers respectively, the reset inputs of which through the first element are NOT connected to the output of the first element OR, etc. my output of the first trigger is connected to the second input of the fourth element I and through the first amplifier-transmitter connected to the output of the line Sign of data reception of the device, the output of the second element I connected to the first the second input of the second element OR, the direct output of the second trigger is connected to the first inputs of the AND elements of the group, from the second to the third and to the third input of the sixth AND elements and through the second amplifier-transmitter to the line input Sign of the data output of the device, the fourth element output is connected to the second and the first inputs of the second and sixth elements OR, respectively, with the second input of the fifth And element and with the recording input of the receiving register; the output of the third And element is connected to the third and second inputs of the second and sixth elements OR respectively Actually, the output of the transmitting register is connected to the second inputs of elements AND groups, the outputs of which through the third amplifier-transmitter are connected to the outputs of the data lines of the device, the output of the second element OR is connected to the input of the installation of the third trigger, the direct output of which is connected to the first input of the third element OR

and information input of the fifth trigger, the synchronization input of which is connected to the output of the sixth element OR, and the direct output through the fourth amplifier-transmitter is connected to the output of the line Blocking of the trunk and output of the line Continuation of device data, outputs of the fifth and sixth elements And through the fifth element OR connected to the installation entrance of the fourth

trigger, the direct output of which is connected to the output of the line Sign of the end of communication of the device and with the second input of the third element IL whose output is connected to the output of the line device request; the output of the seventh element OR is connected to the second input of the eighth element AND, the output of which is connected to the third input of the first element OR.

The invention relates to computing technology, in particular to geographically distributed centralized computing data collection and processing systems operating on long telephone lines, and provides for the connection of different types of electronic computing machines. . The purpose of the invention is to increase the data transfer rate by introducing a synchronous exchange mode, expanding the functionality due to independent data transmissions from any subscriber, and increasing reliability by preventing information loss during data exchange in a synchronous mode. Figure 1 shows a block diagram of the switching system computing devices; Fig. 2 is a functional diagram of a communications switching device; FIG. 3 is a functional diagram of the interface; FIG. 4 is a functional diagram of a sync pulse shaping unit; in fig. .5 is a functional diagram of the interface unit with external devices; FIG. 6 - subscriber functional scheme; FIG. 7 are time diagrams for explaining how the system works; Fig.8-1 algorithms for computing devices with a switching system. The switching system of computing devices (Fig. 1) contains a central electronic computer 1, for example, a unit 2 for interfacing with external devices, a communication switching device 3, a group of 4 bidirectional main data lines, a line 5 Signs of data reception, line 6 Sign of data output, line 7 Data continuation, m devices 8.1 conjugation (), t subscribers 9.1, generator 10 clock pulses, t + 1 clock forming blocks 11.1, line 12 Trunk blocking, line 13 clock pulses. The communication switching device 3 (Fig. 2) contains a memory block 14, a counter 15, first to third registers 16-18, trigger 19, first to fifth amplifier-receivers 20.1-20.5, first to third transmitters 21.1-21.3, from the first to the eighth group of the elements i toB And 22-29, from the first to the fourth elements And 30-34, and from the first to the third group of elements OR 35-37, the first and second elements OR 38 and 39, first to third elements are NOT 40-43, delay element 44, data bus outputs 45, line output 46 Request for data transfer, line output 47 Request state transfer, synchronization input 48 data, line input 49 Write, line 50 input Read, initial sample line input 51, channel input 52, channel address, channel 53 bus inputs, channel information line 54 input, line input 55, address read, line input 56 Reads subscriber information.

Interface device 8 (FIG. 3) contains first to third receiver amplifiers 20.1-20.3 first to quarterly transmitter amplifiers 21.1-21.4 transmitters, a subscriber number decoder 57, receiving and transmitting registers 58 and 59, first to eighth elements And 60-67, a group of elements And 68, from the first to the seventh - elements OR 69-75, first to third elements are NOT 76-78, first to fifth triggers 79-83, delay element 84, outputs 85 of data buses, data bus inputs 86, data synchronization input 87, direct 88 line input Information output flag, 89 line direct input sign in ode information input lines 90 new input data ready line 91 are received data, inverted input lines 92 Symptom information output, the inverting input 93 input 94 input information indicator line End communication request output line 95.

The sync pulse shaping unit 11 (Fig. 4) contains the element HE 96, the first and second one-shot one and the same vibrators 97 and 98, the element OR 99.

The electronic computer 1 (FIG. 5) contains a processor 100, a RAM block 101, a multiplex channel 102, a block 2 for interfacing with external devices containing a command register 103, an information register 104, an address decoder 105, an initial sampling trigger 106, groups 107 and 108 elements AND, a group of 109 elements OR, two elements AND 110 and 111, node 112 forming interface signals, input line 113 Channel control, output line 114 Subscriber operation, output line 115 Subscriber address, output line 116 Subscriber control, output bus 117 ab Onenta input lines Channel 118 operation, Channel 119 sampling, 120 resolution sampling, Channel 121 blocking, Subscriber output lines 122 and Subscriber 123 sampling.

Subscriber 9 (FIG. 6) contains a common bus 124 with processor 125 connected to it, block 126

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memory, external memory block 127, conversational I / O block 128, interface signal block 129, which contains interrupt control node 130, address sampling node 131, information input registers 132, information state blocks 133 and 134, and a bit buffer register 135, matching receiving elements 10, 136, matching transmitting elements 137, a switching control unit 138, two inverters 139 and 140.

Figure 7 shows the time t5 diagrams explaining how the system works. 7 shows diagrams: 141 — clock pulses (TI) from the generator output 10 clock pulses at the same name, SRI 13, 142 — sync pulses from the outputs of the synchro pulses forming unit 11, 143 — data reception feature (PD) signals on the same line 5, 144 —signal 25 signals (PV) on the same line 6; 145 — trunk block signals (BLM) on the same line 12; 146 — data continuation signals (PD) on the same line 7; 30 147 — signals on the bi-directional trunk group 4 data.

The principle of operation of the computing system, the communications switching device and the interface device with .JC is represented by the functional diagrams and timing diagrams and is as follows.

The whole cycle of the system starts with the fact that the central computer 1 according to a predetermined program by executing the Write and Read commands via the I / O interface and the interface 2 block with external devices in the initial sampling mode initializes the communication switching device 3. The initialization fact is recorded in the memory block 14 of the communication switching device 3 with the indication of the reception or output of data for all subscribers 9.

Next (FIG. 7) and (FIG. 1), the communication switching device 3 initializes a continuous sequential interrogation of subscribers 9 for 55 receiving or outputting information to

TsEVM1. A 10-clock pulse generator continuously generates a series of rectangular pulses with a duty cycle

two (chart 141) on the 13 clock line,

The sync pulse shaping units 11 generate sync pulses (SI) along the leading and trailing edges of the clock pulses (diagram 142). According to one of the clock pulses, the communication switching device 3 issues, for example, a data reception feature () to the same line 5 (chart 143) and simultaneously to the trunk data group 4 data code number (K address) of the 9K subscriber, chart 147, this subscriber identifies the address, via the 8K interface, responds by issuing a data output feature (Ex) to the same line 6 (diagrams 144) and starts transmitting a data block over a group of 4 data lines. Having received a response on the data output line (PD), the communication switching device 3 is prepared to receive data from the subscriber and, at the time of data arrival, forms a request to transmit them to the CEVM1 and, in accordance with 1 and with the I / O interface, organizes the data transmission cycle to CEVM1 in multiplex mode and so consistently for all subscribers.

During the operation of the system, it may appear that the subscriber, for example, 8p, did not have time to prepare the data for transmission, he generates a trunk blocking signal (BLM) to the same line 12 (chart 145) through his 8p interface device. The BLM signal on the trunk warns switching device 3 connection that it is necessary to skip a cycle or several cycles in data transfer. The BLM signal in the communication switching device 3 blocks the request for data transmission to the CEVM1. The presence of this signal eliminates the time constraints of the preparation of information during the transmission of clock pulses.

If the subscriber receiving and / or transmitting data is slow and does not have a buffer memory, then he works in the mode of byte transfer. At the same time, after transmission of a data byte, it appears on line 7, Continuation of data, a sign of continuation of data (PD) (chart 146) and

at the same time, it removes the signal from line 6 of the data output feature, diagram 144. In the switching device 3, linking the blocking signal to the transmission status of the CEBM1 is blocked, and the signal from line 5 of the data receiving sign is reset. The continuation of work in this case is carried out on a common basis,

those. when the turn comes to poll this subscriber.

During system operation, it may be that one of the subscribers 9 (for example, with address B) is

not ready for the communication session (Fig. 7), then the communication switching device 3 proceeds to polling the next subscriber 9, for example, with the address p. The principle of operation of the aircraft in data transfer mode from the CEVM1 to the subscriber is similar to the specified one, except that On the initiative of the Center for Computer Communication, the communication switching device 3 issues a sign of data output to the data output line 6 and to the same name, data line 4, the subscriber address code (for example, address p). Subscriber 9p, through its device 8p conjugation, recognizing its address, sends a sign of receiving data to the same name line 5 of the sign of receiving data, after which TsEVM1 starts transmitting data to subscriber 9p in this way. Stop Transmission

data in this case, as a rule, ends on the initiative of CEVM1 by removing the signal from line 6 of the sign of the data output.

.Program exchange support

data in the system is carried out by the monitor programs on CEVM1 and subscribers 9.

A monitor program receives requests from internal programs and an external monitor program via communication lines. It performs the ordered operations on its computer using the service routines it calls and supports the exchange with another monitor program on a group of bidirectional trunk lines 4 data and lines 5, 6, 7, 12, 13 of the control.

The initial power up of the CEVM1 and subscribers 9 and the launch of the monitor programs is carried out according to a schedule.

There are two main modes of operation of the system: setting when

I

the type of exchange operation is coordinated, and the actual exchange operation or transfer, when a coordinated operation is performed between CEVM1 and the corresponding subscriber 9. Immediately after switching on CEVM1, subscribers switch to the establishment mode.

At each time point, subscriber 9 can be either in the first or second mode, and CEVM1 with different subscribers 9 in different modes.

The exchange takes place in blocks of fixed length.

Each block contains information and service sections. In the service section there is, in particular, a checksum.

The correctness of the block transfer is performed by calculating the checksum.

Particular attention should be paid to the mechanism for transmitting messages about incorrect checksum and other information in half-duplex transmission mode.

This is achieved by the fact that the monitor of the receiving unit stops its reception in a certain place, i.e. breaks the reception block.

Depending on the number of bytes transferred, by the time the exchange is terminated, the sender understands that the receiver wanted to inform and takes appropriate measures.

For example, a break on the second byte means that the previous block was transmitted with an incorrect checksum and you need to transfer it again

A break on the 6th byte indicates that the requested transmitter in the establishment mode can be performed by the receiver, etc.

In the install mode, the CEVM1 monitor accepts a block with a request for operation from subscribers 9. It can either refuse to exchange because it is impossible to perform the operation, or have the subscriber 9 perform (despite his request) his request for an operation, or report the possibility of performing the operation and the transition to the exchange phase.

Various erroneous situations are divided into: identifiable (e.g., checksum mismatch), resulting after five times

the transmission torus and back to the establishment mode, and unrecognizable (subscriber 9 does not contact, the I / O command hangs). In this case, the exit from this situation occurs on the system timer.

The indicated algorithm of the computer system operation with the devices included in it is explained by the diagrams shown in FIG. 8-13, where, for the sake of multiplicity of presentation, TsEVM-1, unit 2 for interfacing with external devices, communication switching device 3 is designated as a central unit (CB).

f with I

. FIG. 8 and 9 are presented. the CBA algorithm diagrams in the communication establishment mode (CON) with one subscriber of reception and / or transmission of data, where certain

Actions with the following positions: 148 — set the system timer to an acceptable delay value STII-ffi, 149 — accept extension from an internal subscriber and set the 1R indicator, (1R 1 request is, 1R There is no request), 150 — set to About the counter NKS, counting the number of KS checksum discrepancies and the pointer

0 hardware errors HWER 0, 151 give a command to read a block to a specific subscriber PQ1B, 152 receive a block from subscriber 1B, 153 there is KS f О to set the pointer

5 cliffs or go to 157, 154 - analyze the request from an external subscriber and, if possible, 155

its fulfillment,

unable to execute then install

КР 10 and go to 157, 156 - if 1R 1, then КР 14 and go to 161 through 157 and 158, the request can be executed КР 6 (items marked for example 148.1, 151.1,

151.2, 152.1, 153.1, etc. indicate the transition lines of the diagram at 8-13), 157 - give a command to read the block from the RQIB subscriber, 158 start receiving and terminate 1B (CU)

block after receiving the KR - bytes,

159 - if КР 6, then the end of establishment (ENDV) to go in exchange (RUN), 160 - if КР 2, Ж8 -NKS + 1, if Ж8 5, then go to 151 or to 148, 161 - NKS ф 162 - transfer the block with the request to the subscriber (OB), 163 - transmit the terminal block OB (CR), proanalieiro

break, 164 - if CR 6, then go to exchange (RUN); 165 - if КР 10, then go to 148, 166, if КР 2, then NKS NKS + 1, and if NKS 5, then go to 162, otherwise go to 148, 167 is a hardware communication error, go to 148.

FIG. 10 and 11 are diagrams of a subscriber's algorithm for receiving and / or transmitting data in the mode of establishing a connection (CON) with a security station, where:

168- set the system timer n the allowable amount of delay STIME,

169- accept subscription from an internal subscriber and set the 1R pointer (1R 1 request is, 1R There is no request), 170 - set to About the NKS counter, counting the number of checksum mismatches KS, NKS

and the HIJER hardware error indicator 0, 171 - transfer the block to the CB (OB), 172 - transfer the end block ABOUT (CR), 173 - if CR 14, then proceed to continue setting on demand in the CB, 174 - if CR 6, then go to exchange RUN, 175 if CR 10, then go to 168, 176 - if CR 2, then NKS GH + 1 and if NKS 5, then go to 171 otherwise go to 168, 177 - hardware communication error HWER 1, go in 168, 178 - give a command to read the block from the RQC central bank, 179 - block 1B is received, 180 - if KS О set the break indicator КР 2 and go to 184, 181 - analyze the request from the RQC central bank, and the possibility of its execution RQC TRUE, 182 - if it is impossible to perform 181, then install КР 10 and go to 184, 183 - otherwise КР 6, 184 - give the command to read the RQC block, 185 - terminate in accordance with КР (1В), 186 - if КР 6, then go to the phase exchange RUN, 187 - if КР 10, then go to the beginning of the establishment of CON, 188 if КР 2, then NKS NKS + 1 and if Ж8 5, then go to 178, otherwise go to CON.

On Fig presents the algorithm of the work of the aircraft in the exchange mode (RUN) for the information transmitting subscriber or the central bank, where: 189 - set the system timer to the permissible value of the STIME track, 190 - set the counter NKS in O, counting the number of mismatches control 8091510

KS, NKS O and the HWER 0, 191 hardware error indicator, set the block counter NBL N + 1, where N is the number of information blocks, N + 1 is the control block for the N block for the transfer, 192 - transmit I block (I) (line 192.1), 193 - transmit the next (1 + 1) -and block OB (1 + 1)

o (line 193.1), 194 - analyze the number of bytes of the KR transmitted: if the RS is 524, then the block is transmitted correctly NKS eJ, NBL NБL - 1, go to 193, 195 - if KR 2,

5 then KS / O, ZhZ NK3 + 1 and if

NKS 5 should repeat the transfer of the previous block and go to 192, otherwise the fatal completion of the exchange, the transition to the establishment of CON (ER),

0 196, - if CR 6 and if NBL O, then the end of the exchange and the transition to the establishment of CON, otherwise the transition to the establishment with an error CON (ER), 197 - if the CR 2,6,524 hardware error

5 HWER 1 go to 192.

FIG. Figure 13 shows the algorithm of operation of the aircraft in the exchange mode (RUN) for the subscriber or central bank who receives information, where: 198 — set the system

0 timer for acceptable delay value ZIME, 199 - set the NKS counter to O, counting the number of KS, NKS O checksum mismatches and hardware error HWER 0, 200 - set the NBL N counter of the number of received blocks, 201 - accept the 1B block (I ), 202 - analyze the checksum KS U, 203 - if KS О, in

0 including when the block is not fully received due to an error, set the break indicator, stop receiving the next block in the 2nd byte, increase the error counter by 1 and if NKS 5

5 go to 201, otherwise go to setting with error CON (ER), 204 checksum coincided, KS counter of received blocks decrease by 1 NBL NBL - 1, reset NK3, 205 -. if NBL (KP 6, cut off the reception of the last N + 1 block on 6 bytes and go to normal CON termination, otherwise KP 524, take the next block completely and go to 202.

The principle of operation of the communication switching device 3 is explained by the functional diagram (Fig. 2) and is as follows: CEVM1 via interface 2 with external devices, by executing an I / O command Write or Read in the initial sampling mode sets the characteristics of reception or output data into certain cells (the address of the memory cell corresponds to the address of the subscriber) of memory block 14 through the fifth group of elements AND 26 and through the first group of elements OR 35 according to the signals: Shin-K (53), N.V. (51) and ADR-K (52). An operating counter 15 on the signal of the SI (48), coming from the synchro pulsation unit 11, through the second group of elements AND 23, the second group of elements OR 36, the third group of elements AND 24, the register 18 and the amplifier 21.2 outputs to SHIN-M (4) the subscriber's address code 9, for example, address K, and simultaneously through the first groups of elements AND 22 and elements OR 35 is detected by the established address code K from memory block 14. A sign, for example, Reception, which is output from the second output of memory block 14 through amplifier 21.3 on the same line 5 of the sign of data reception lcx (diagram 143 of FIG. 7). If the subscriber 9k has recognized his address through his device 8k conjugation, then in the same half-cycle of the clock series (Fig.7), he responds along line 6 of the data output flag with the HB signal (diagram 144 of Fig.7). Signals PPr and Pv of the same lines PPr5 and Pvb block the further recalculation of counter 15. Simultaneous presence of signals on lines PPr (5) and PV (6) is also a permission to upload to PC 1 via interface 2 with external devices using the signals of the SI (48) requests for data transmission according to code 46 at TsEVM1. After that, the address address is connected to the address of the subscriber 9, for example, with the address K from the counter 15, which through the seventh group of elements 28 and the third group of elements OR 37 is transmitted to the outputs 45 and transmitted through the interface 2 with external devices to the CEVM1 .

After the signal Pv on the same line 6 of the sign of withdrawal

data, the subscriber 9k through its device 8k interface transfers data to SHIN-M (4), which are recorded in register 17, from where they are transmitted to CEVM1 via the INF-A signal (56), through the eighth group of elements And 29 and the third group of elements STI 37 data is received at the outputs 45, from where through the interface 2 is transmitted to CEVM1.

The end of the exchange of data on the initiative of the central computer (1) or subscriber 9 is accomplished by withdrawing its

15 of the signal of the sign of reception of the directive or the indication of the output of PV from the corresponding lines of PRPR (5) or PV (6). The absence of one of the signals PV (6) OR App (5) causes the installation

20 trigger 19 in one state, i.e. the Request for state transfer (47) signal to the central computer 1 is generated, and at the same time it unlocks counter 15 and erases in cell 14

5 memories corresponding attribute

PPr or Pv on the signal from the output of the trigger 19, which is reset by the INF-K signal (54), coming from the central computer (1) through the block 2 of the interface and external devices, j During system operation, it may turn out that subscriber 9 to For some reason, I did not have time to prepare the transmitted information, he

5 transmits the BLM signal to the trunk line 12 of the same name (Figure 145, subscriber with address p, FIG. 7). This signal blocks the output of the signal. Transmission request

0 data 46 in ECVM1. The BLM signal is issued per clock or several cycles. and removed by subscriber 9 when information readiness for transmission / reception is resumed. After taking off

The 5 BLM signal is unlocked by the fourth element AND 33.

If subscriber 9, for example, with address S (chart 446, Fig.7)

0 is slow-acting, it can stop transmitting data by picking the PD flag on the same name as data continuation line 7 and in the PV signal (chart 144, fig. 7) from line 6

sign of data year. The occurrence of the PD sign unlocks the counter 15. This leads to the removal of the sign Ppr on the second output of block 14 of memory 13.

ti and from the same line 5 sign of data reception.

The principle of operation of the interface device is as follows. In accordance with the operation of the communication switching device 3, the timing diagram (Fig. 7) and the functional diagram of the interface device 8 (Fig. 3), the subscriber code 9 with the address K and the feature received on the TIR-M (4) 5 of the reception feature, the device 8k of the interface of the subscriber 9k identifies its address with the help of the address decoder 57 by the SI signal (87) delayed through the delay element 84 from block 1k of sync pulse generation, the reception feature signal on the same line 5 and if there is a signal Output (89) information, through the second element And 61 set is cast into 1 second trigger 80. The single state of the second trigger 80 is output as an indication of the output of the same line PV (6) and through the third element And 62 allows the passage of the information synchronization signal (87), through which the second element OR 70 is set to one the state of the third flip-flop 81, the single state of the third flip-flop 81 through the third element OR 71 is transmitted along the output request 95 to the service subscriber 9k through the interface signal block 129 (FIG. 6). At the request of the interface device 8k, the processor 125 of the subscriber 9k receiving and / or transmitting data via the node 12 of generating interface signals enters the data data bytes 86 on the data buses, which, by the data synchronization signal (87), is written to the transmitting register 59 and through the AND 68 group of elements is transmitted to a group of 4 data bus 4

The third trigger 81 is reset by the control input signal. New data is ready (90), coming from the interface signal generation section 129.

The data transfer, in this case, initiated by the subscriber 9k, is carried out by removing the input signal of the view: information (89), which zeroes through the first element OR 69 and the first element NOT 76 the second trigger 80

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those. The data output feature (Pv) signal is removed from the same name line 6 of the data output feature.

The termination of data transmission is also possible on the initiative of TsEVM1, in this case, the signal of the reception feature is removed from the same name line 5 of the data reception feature and through the second element NOT 77, the And 65 element,

0, the fifth element OR 73 is set to one state by a fourth trigger 82, the output of this trigger is connected to the output line 94 of the termination feature, which is processed by the processor 125 of the subscriber 9 for receiving and / or transmitting data as a sign of the end of the data output operation.

If data is transmitted from CEBM1

0, the operation of the interface 8 is as follows. The communication switching device 3 is connected to the TIR-M 4 subscriber code 9 with an address, for example R (FIG. 7), and a sign

5 Pv outputs (diagram 144) on the same name line 6 of the data output feature, the 8R interface of the subscriber 9R identifies its address with the help of the decoder 57 addresses,

0 by the delayed, via the delay element 84, data synchronization signal (87), the PV signal (6), and in the presence of the input signal of the input information sign (88) through

the first element And 60 sets to 1 the first trigger 7-9. A single state of it appears as a sign on the CPR line (5) and through the fourth element I 63 allows the passage of the delayed data synchronization signals (87) coming from the sync pulse shaping unit 11R. This condition is a permission to enter the data byte of data on PWM-M (4) (chart 147) into the receive register 58. At the same time, through the second element OR 70 it is set to one

the third flip-flop 81, the unit state of this flip-flop, via the third element OR 71, is transmitted via the output 95 of the service request to the subscriber 9R through the interface signal generation unit 129 (Fig. 6).

At the request of an 8R interface device, a 125 subscriber processor 9R

reads information from the receiving register 58 through the interface signal generation node 129, and then sets the signal Data is received on the input line 91 Data is received, the third trigger 81 is reset to the O signal via the fourth element OR 72, thereby preparing the 8R pairing device to receive the next byte of information.

If processor 125, for example, subscriber 8p, does not have time to respond to a request over the duration of the clock pulses (chart 141), then the data synchronization signal (87) via the third element And 62 (when outputting information) or the fourth element And 63 (when entering information ) and the sixth element OR 74 is set to the single state of the fifth trigger 83 (with the single state of the third trigger 81). The single state of the fifth trigger 83 enters the line 12 of the blocking highway. This feature blocks the trunk per clock or several cycles (diagrams 141, 145) until the processor 125 of the 8p subscriber services the incoming request.

The use of a clock generator, sync pulse shaping units, unidirectional trunk blocking lines and clock pulses, as well as bidirectional data reception feature lines and a data view feature allows the data transfer rate to be as close as possible to systems of this type.

The switching system of computing devices, the communication switching device and the interface device make it possible to combine different types of computers, which makes it possible to create a computer system for automating experimental studies of a physical experiment.

Fig4

, LZ. one

Claims (3)

1. A switching system of computing devices, comprising a communication switching device, m interface devices, a group of bi-directional data lines, a line. Sign of data reception, a line / sign of data output, a line. Continuation of data, inputs and outputs of data lines of a communication device through a group of bi-directional trunk lines. data are connected to the outputs-inputs of the data lines of the interface devices, the inputs and outputs of the line. Sign of receiving data and lines. Sign of data output of the communication switching device via lines. data reception and the Sign of data output are connected to the same outputs-inputs of the pairing devices, the line outputs Continuation of the data which is connected through the line Continuing the data to the same name input of the communication switching device, the group of input-outputs of the main line of the central processor of the switching device is the system input-output of the same name, the input- subscriber bus output _i-ro of the interface device (i = 1, t) is the input-output of the i-ro bus of the subscriber of the system of the same name, characterized in that, in order to increase the transmission speed data due to the introduction of a synchronous exchange mode into the system. a clock pulse generator, t + 1 clock generation blocks are introduced, a trunk lock line, a clock pulse line, a clock pulse output through a clock line is connected to the clock line inputs of the clock generation blocks, data synchronization inputs of the communication switching device and the pairing devices are connected to the outputs the corresponding blocks for the formation of clock pulses, the input of the line Blocking the trunk of the communication switching device is connected through the Lock magist trawl to the outputs of the same device mates. 2. A communication switching device comprising a first to third counter, registers, a trigger, a first to third group of OR elements, a first to eighth group of AND elements, a first and second OR element, a first AND element, the outputs of the AND elements of the first group are connected to the first inputs of the OR elements of the first group, the outputs of the AND elements of the seventh and eighth groups are connected to the first and second inputs of the OR elements of the third group, the outputs of which are the data bus outputs of the device, the output of the first element OR the output of lines Request for data transfer The device, direct trigger output is the output of the Request for state transfer line, characterized in that, in order to expand the functionality due to independent data transmission from any subscriber, a memory block is introduced into it, from the first to the third amplifier transmitters, from the first to the fifth amplifiers-receivers, from the first to fourth elements NOT, from the second to fifth elements AND, delay element, the first and second inputs of the second element And through the first and second amplifiers the receivers are connected to the inputs of the lines Sign of data output and Sign receiving device data, respectively, the first input of the third AND element through the fourth element NOT and the third amplifier-receiver is connected to the input of the device data continuation line, the inputs of the second register through the fourth group of And and the fourth amplifier-receiver are connected to the inputs of the device data lines, the first inputs of the first and the fourth element And, the first inputs of the third group of elements And and the input of the delay element are connected to the input of the device data synchronization, the output of the delay element is connected to the first input of the fifth element AND and the control inputs of the fourth group of elements AND, the input of the line Blocking the device backbone through the fifth amplifier-receiver and the second element is NOT connected to the second inputs of the fourth and fifth elements AND, the outputs of which are connected to the first and second inputs of the first OR element, write and read inputs of the memory block are connected to the inputs of the Write and Read lines of the device, respectively, the input · line of the initial sample of the device is connected to the first inputs of the elements of the fifth group and through the third element. NOT to the first inputs of the AND elements of the first group, the input of the Address line, the device channel is connected to the second inputs of the AND elements of the fifth group, the third inputs of which are combined with the information inputs of the first register and connected to the device data bus inputs, the input of the device channel information line is connected to the reset input trigger and recording input of the first register, the outputs of which are connected to the first inputs of elements And the sixth group, the inputs of the lines Read addresses and subscriber information of the device are connected to the first inputs of elements And the seventh and the eighth group, respectively, the output of the first AND element is connected to the input of the counter, the outputs of which are connected to the second inputs of the AND elements of the first and seventh groups, with the first inputs of the AND elements of the second group, the outputs of the AND elements of the second and sixth groups through the second group of OR elements are connected to the second inputs of the elements of the third group, the outputs of which are connected to the inputs of the third register, the outputs of which through the first amplifier-transmitter are connected to the outputs of the device data lines, the output of the second register is connected to the second inputs elements And the eighth group, the output of the second element And is connected to the second inputs of the elements And the sixth group, the third inputs of the elements And the seventh and eighth groups, the third inputs of the fourth and fifth elements And and through the first element NOT with the second inputs of the third element And, the elements And the second group and with the first input of the second OR element, the output of the third AND element is connected to the trigger installation input, the output of the second OR element is connected to the second input of the first AND element, the direct output of the trigger is connected to the second input of the second OR element the gate of the memory block, the information inputs of which are connected to the outputs of the OR elements of the first group, the first output of the memory element is connected to the third inputs of the AND elements of the sixth group, the fourth input of the fourth AND element, and through the second amplifier-transmitter with the output of the line the second output of the memory element is connected to the fourth inputs of the AND elements of the eighth group, the fourth input of the fifth AND element and through the third amplifier-transmitter with the line output. Sign of device data reception, output And the fifth group element are connected to second inputs of the OR elements of the first group. I 3. A coupler comprising first to third amplifiers-receivers, first to fourth amplifiers-transmitters, a subscriber number decoder, receiving and transmitting registers, first to sixth elements AND, the first element OR, first to third elements NOT, the first trigger, delay element, subscriber number decoder input and information inputs of the reception register through the first amplifier-receiver are connected to the inputs of the device data lines, the outputs of the reception register are connected to the data bus outputs of the device, information inputs The data of the transmitting register are connected to the data bus inputs of the device, characterized in that, in order to increase reliability by preventing loss of information during data exchange in synchronous mode, the seventh and eighth AND elements, a group of AND elements, and the second to seventh OR elements are introduced , from the second to the fifth triggers, the first inputs of the first AND element, the seventh OR element, and the input of the third element are NOT connected through the first amplifier-receiver to the line input sign Device data output, the output of the third element is NOT connected to the first m is the input of the fifth element AND, the first input of the second element AND, the second input of the seventh element OR and the input of the second element are NOT connected to the line input through the second amplifier-receiver. Sign of device data reception, the output of the second element is NOT connected to the first input of the sixth AND element, recording input transmitting register, the first input of the third AND element, and through the delay element, the first inputs of the fourth, eighth, second inputs of the first, second, sixth AND elements are connected to the synchronization output of the device data, the first input of the first element OR and the third input of the first element AND are connected to the direct input of the line. Sign of inputting device information, the second input of the first element of OR and the third input of the second element AND are connected to the direct input of the line. Sign of outputting information of the device, the reset input of the third trigger through the fourth element OR is connected to the inputs of the lines New data is ready and Data The device is received, the fourth trigger reset input through the seventh element And is connected to the inverse inputs of the lines Sign of output and Sign of input of device information, decoder output but The absorber era is connected to the fourth inputs of the first and second AND elements, the outputs of which are connected to the installation inputs of the first and second triggers, respectively, whose reset inputs through the first element are NOT connected to the output of the first OR element, the direct output of the first trigger is connected to the second input of the fourth element And and through the first amplifier-transmitter is connected to the output of the line. Sign of receiving device data, the output of the second element And is connected to the first input of the second element OR, the direct output of the second trigger is connected to the first with the inputs of the elements of the AND group, with the second input of the third and the third input of the sixth AND element and through the second amplifier-transmitter - with the line input. Sign of device data output, the output of the fourth AND element is connected to the second and first inputs of the second and sixth elements OR, respectively, with the second the input of the fifth element And and with the input of the recording of the reception register, the output of the third element And is connected to the third and second inputs of the second and sixth elements OR, respectively, the outputs of the transmitting register are connected to the second inputs of the elements And g groups whose outputs through the third amplifier-transmitter are connected to the outputs of the device data lines, the output of the second OR element is connected to the installation input of the third trigger, the direct output of which is connected to the first input of the third OR and the information input of the fifth trigger, the synchronizing input of which is connected to the output of the sixth OR element, and the direct output through the fourth amplifier-transmitter is connected to the line output Blocking the trunk and the line output Continuation of the device data, outputs of the fifth and sixth elements And through the fifth element, OR are connected to the installation input of the fourth trigger, the direct output of which is connected to the line output. Sign of the end of communication of the device and to the second input of the third OR element, the output of which is connected to the output of the device Request line, the output of the seventh OR element is connected to the second input of the eighth element And, the output of which is connected to the third input of the first OR element.