SU1474659A1 - Computer/communication channel interface - Google Patents

Abstract

The invention relates to computing and can be used in multichannel computer interface devices with remote terminals. The aim of the invention is to improve the speed of the device. The device includes a transceiver 1, a block of 5 transmitters, a block of 6 receivers, a block 7 of interrupt handling, a trigger 8, a block of elements 4, and a block 10 of flip-flops. The device interfaces the groups of remote terminals (display, teletype) with a computer. 1 il.

Description

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The invention relates to computing and can be used in multichannel computer interface devices with remote terminals.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of the device.

The device comprises a transceiver 1, a computer 2, which includes a processor 3 and a memory 4, a transmitter unit 5, a receiver unit 6, an interrupt processing unit 7, a trigger 8, an AND 9 element unit and a trigger unit 10.

The interrupt processing unit is made on the LSI KR580VN59.

The device works as follows.

The signal in the form of a sequential code from one of the subscribers is transmitted via a communication channel to the input of the receiver unit 6 corresponding to the subscriber, where it is converted to a potential form. From the block 6 output corresponding to the subscriber, the signal goes to the interrupt input to the interrupt handling block 7 and the information input of the trigger block tO. On the leading edge of the start bit of the serial code at the output of the interrupt (PR) of block 7, a low level signal is generated. In response to the PR signal, the processor 3 transmits to the block 7 an Interrupt Provisioning (RR) signal, by which at the output of the block 7, the PR signal returns to a high state, and the block 7 transmits the address of the interrupt processing program from the data line to the processor 3 subscriber. At a low level of the PR signal arriving at the D-trigger 8 installation from the information output of the D-trigger 8, a high-level signal arrives at the synchronization input of the trigger unit 10, on the leading edge of which the corresponding output of subscriber trigger signal is set to high level, and outputs information on the remaining flip-flops are set low level signals, thereby signal in a serial code corresponding to the subscriber unit receivers outlet 6 through the AND unit 9 is input to the serial input of the transceiver 1. After converting the serial

code into a parallel signal at the output ready to receive data from transceiver 1 changes from a low to a high state. This transition switches the D-flip-flop 8 to its initial low state, allowing analysis and reception of the next burst from the serial communication channel and the subscriber.

Claims (1)

Invention Formula A device for interfacing a computer with communication channels, comprising a transceiver, a transmitter unit, a unit receivers, the input-output device for connecting the computer data bus is connected to the information input-output transceiver and to the input transmitter unit, the readiness output of the transceiver is connected to the output of the device for connection to the first interrupt input of the computer, the output of the transmitter unit is connected to the output of the device for connection to informational inputs of communication channels, characterized in that, in order to increase the speed of the device, an interrupt handling unit, a trigger, a group of trigger elements and a group of elements And, and an input of the device for connecting information outputs of communication channels connected to the input of the receiver unit, the output of which is connected to the interrupt input of the interrupt processing unit, to the information inputs of group triggers and to the first inputs of group elements, the second inputs of which are connected with the trigger outputs of the group, the synchronization inputs of which are connected to the trigger output, the zero input of which is connected to the output of the interrupt processing unit and the output of the device for connecting the second computer interrupt input, the input-output of the device for connecting the computer data bus is connected to the information input-output interrupt processing unit, the device inputs for connecting the address output of the computer and the output resolution of the computer are connected respectively to the address input and the enable input of the processing unit interrupts, the trigger synchronization input is connected to the transceiver readiness output, the information serial input of which is connected to the output of the AND block,