JPH07162392A - Time-division multiplex conversion circuit - Google Patents

Abstract

PURPOSE:To convert input highways having various different speeds into the highways of designated speed and to flexibly cope with the conversion of the positions of information on an output frame. CONSTITUTION:Input highway information of various speeds are stored in input information storage circuits 11-14 matching with the speeds of the respective input highways 101-104. All information stored in the input information storage circuits 11-14 are shifted to a whole input information storage circuit 21 at a prescribed period in one frame. Information are shifted from the whole input information storage circuit 21 to output information storage circuits 31-34 by a control timing signal generated in a read/write control circuit 22 based on multiplex conversion information deciding in which position on which output frame which input information in a multiplex separation conversion information storage circuit 23 is outputted. The output information storage circuits 31-34 output information matching with the speed of the respective output highways 122-125.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex conversion circuit for converting a time division multiplex signal, and more particularly when converting an input highway having different speeds to an output highway having different speeds and outputting the output highway. The present invention relates to a division multiplexing conversion circuit.

[0002]

2. Description of the Related Art FIG. 3A is a block diagram of an example of a multiplex circuit of a conventional time division multiplex conversion circuit, and FIG. 3B is a waveform diagram of each part for explaining the operation of FIG. The multiplexing circuit shown in FIG. 3A shows an example in which four input highways of 1.5 Mbps are multiplexed into one output highway of 8 Mbps.

Further, FIG. 4A is a block diagram of an example of a separation circuit of a conventional time division multiplex conversion circuit, and FIG. 4B is a waveform diagram of each part for explaining the operation of FIG. 4A. Figure 4
The separation circuit shown in (a) shows an example in which one input highway of 8 Mbps is separated into four output highways of 1.5 Mbps.

Reference numeral 301 shown in FIG.
, 313 and the reference numerals 401 shown in FIG.
, 413 respectively show the waveforms of the reference numeral portions of the same numbers in FIGS. 3 (a) and 4 (a). Also, the shaded portion indicates the invalid bit portion.

First, the operation of the multiplexing circuit will be described with reference to FIG.

Speed conversion circuits 41, 42, 43 and 44
Input highway information is input from the input highways 301, 302, 303 and 304 by using the tiling signals 306, 308, 310 and 312 generated by the timing generation circuit 61.

As shown in FIG. 3B, the frame of the input highway 301 is composed of information A0, A1, ..., An, and similarly, the frame of the input highway 302 is composed of information B0, B1 ,. The input highway 303 frame is composed of information C0, C1, ..., Cn, and the input highway 304 frame is composed of information D0,
Dn, ..., Dn.

Speed conversion circuits 41, 42, 43 and 44
Selects the information 305, 307, 309 and 311 by speed-converting the input highway information input from the input highways 301, 302, 303 and 304, respectively.
To enter.

The selection circuit 51 is gated by the tiling signals 306, 308, 310 and 312 generated by the timing generation circuit 61 to obtain four pieces of information 305, 307, 309.
And 311 are converted into one output highway information and output to the output highway 313.

Next, the operation of the separation circuit will be described with reference to FIG.

When the input highway information of the input highway 401 is input to each of the selection circuits 71, 72, 73 and 74, each of the selection circuits 71, 72, 73 and 74 causes the tiling signal 40 generated by the timing generation circuit 91.
2, 404, 406 and 408 are respectively gated to output information 403, 405, 407 and 409 to speed conversion circuits 81, 82, 83 and 84.

Each speed conversion circuit 81, 82, 83 and 8
4 performs speed conversion of the input information 403, 405, 407 and 409 and outputs output highway information to the four output highways 410, 411, 412 and 413.

As shown in FIG. 4B, the frame of the output highway 410 is composed of information A0, A1, ..., An, and similarly, the frame of the output highway 411 is composed of information B0, B1 ,. The output highway 412 frame is composed of information C0, C1, ..., Cn, and the output highway 413 frame is composed of information D0,
Dn, ..., Dn.

[0014]

In this conventional time division multiplex conversion circuit, the multiplex circuit multiplexes the input highway and outputs it to the output highway, but the position of information on the frame of the output highway is the time division multiplex conversion circuit. Will be uniquely decided by. Further, since the highway speed is fixed, there is a problem in that in order to change this speed, the time division multiplexing conversion circuit itself must be changed.

The separation circuit has the same problem.

It is an object of the present invention to convert an input highway having various kinds of speeds into an output highway having a specified speed so as to flexibly deal with the conversion of the position of information on an output frame. It is to provide a multiple conversion circuit.

[0017]

According to the present invention, a plurality of input information storage circuits for sequentially storing a plurality of input highway information in accordance with the speed of each input highway, and all of the plurality of input information storage circuits. An all-input information storage circuit that transfers information in a fixed cycle, a demultiplexing conversion information storage circuit that stores in advance information on which input highway information to output at which position on which output frame, and A read / write control circuit that generates a control timing signal for reading from all the input information storage circuits based on the information stored in the separated conversion information storage circuit and storing the information in the output information storage circuit corresponding to the output highway; A plurality of output information storages for reading and outputting the information stored by the control timing signal according to the speed of each output highway Division multiplex conversion circuit is obtained when anda road.

Each of the input information storage circuits is a first-in-first-out type memory having a capacity of two frames or more, and all the input information storage circuits are two-sided memory. A time division multiplex conversion circuit is obtained.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time division multiplexing conversion circuit of the present invention, and FIGS. 2A and 2B are for explaining the operation when FIG. 1 is used as a multiplexing circuit and a separation circuit, respectively. 3 is a waveform diagram of each part of FIG.

In FIG. 1, when the time division multiplex conversion circuit of this embodiment is a multiplex circuit, an example in which four 1.5 Mbps input highways are multiplexed to one 8 Mbps output highway is shown. When it does, 1 of 8Mbps
An example is shown in which a book input highway is separated into four 1.5 Mbps output highways.

Reference numerals 101, ..., 125 shown in FIGS. 2 (a) and 2 (b) respectively indicate the waveforms of the reference numeral portions of the same numbers in FIG. Also, the shaded portion indicates the invalid bit portion.

Referring to FIG. 1, the time division multiplex conversion circuit of this embodiment has four input highways 101, 102, 1.
The input information storage circuits 11 and 12, each of which is a first-in-first-out type memory having a capacity of two frames or more, which sequentially stores the input highway information 03 and 104 in accordance with the speed of each input highway.
13 and 14 and these input information storage circuits 11 and 1
2, 13 and 14 all information 105, 107,
An all-input-information storage circuit 21 configured by a two-sided memory into which 109 and 111 are transferred at a constant cycle, and a multiplex that previously stores information about which input highway information is output to which position on which output frame The separation conversion information storage circuit 23 and the output information storage circuit 31 corresponding to the output highways 122, 123, 124, and 125 read out from all the input information storage circuits 21 based on the information stored in the demultiplexing conversion information storage circuit 23. , 32, 33 and 34 read control timing signal 11 when stored
5, 117, 119 and 121, and control timing signals 115, 117 and 1
Output information storage circuits 31, 32, which read and output the information stored by 19 and 121 in accordance with the speeds of the output highways 122, 123, 124 and 125,
33 and 34. The read / write control circuit 22 includes the input information storage circuits 11, 12, 13 and 14
Write control timing signals 106, 107, 110 and 112 for writing the information from 1 to all input information storage circuits 21 are also generated.

Next, the operation of this embodiment will be described with reference to FIGS.

First, when the time division multiplex conversion circuit of this embodiment is used as a multiplex circuit, as shown in FIG. 2A, the input highways 101, 102, 103 and 10 are input.
The input highway information input from 4 is stored in the input information storage circuits 11, 12, 13 and 14, respectively.

Each of the input information storage circuits 11, 12, 13 and 14 writes the stored input highway information from the read / write control circuit 22 to the control timing signal 106, 10 for writing.
Information 105, 107, 109 and 111 are sequentially written in the entire input information storage circuit 21 by using 8, 110 and 112 respectively.

The all-input information storage circuit 21 reads out based on the information of which input highway is stored in the demultiplexing conversion information storage circuit 23 and which output highway is output to which position on the frame. The information 114 is written in the output information storage circuit 31 by the address signal 113 generated in the write control circuit 22 and the write control timing signal (for example, the control timing signal 115).

Then, the output information storage circuit 31 outputs the multiplexed information according to the speed of the output highway 122.

The output of multiplexed information from the other output information storage circuits 32, 33 and 34 is the same as above.

Next, when the time division multiplex conversion circuit of this embodiment is used as a demultiplexing circuit, as shown in FIG. 2B, for example, the input highway information input from the input highway 101 is the input information storage circuit 11. Memorized in.

The input information storage circuit 11 writes the stored input highway information in order to all the input information storage circuits 21 using the write control timing signal 106 from the read / write control circuit 22.

Based on the information of which input highway is stored in the demultiplexing / conversion information storage circuit 23 and which output highway is output to which position on the frame,
Address signal 113 generated in read / write control circuit 22 and write control timing signals 115, 117, 11
9 and 121, the information 114, 116, 118 and 120 read from all the input information storage circuits 21 are written in the output information storage circuits 31, 32, 33 and 34, respectively.

Then, each output information storage circuit 31, 32,
33 and 34 are output highways 122, 123, 12
It outputs the output highway information separated according to the speeds of 4 and 125, respectively.

[0034]

As described above, according to the present invention, an input information storage circuit for sequentially storing a plurality of input highway information in accordance with the speed of the input highway, and all information from the plurality of input information storage circuits are fixed. All input information storage circuits that are transferred in a cycle, a demultiplexing conversion storage circuit that stores in advance information about which input highway information to output at which position on which output frame, and this demultiplexing conversion information storage circuit A read / write control circuit that generates a control timing signal for reading from all the input information storage circuits based on the stored information and storing it in the output information storage circuit corresponding to the output highway, and the information stored by the control timing signal Of the input information storage circuit by providing an output information storage circuit that reads and outputs The relationship between the speed of the input highway and the speed of reading internally from the input information storage circuit and the speed of writing from the internal to the output information storage circuit are independent of each other. It can be constant regardless of the speed of the highway.

Therefore, even if the speed of the input highway and the speed of the output highway are changed, the same time division multiplex conversion circuit can be used.

Further, by rewriting only the demultiplexing conversion information, there is an effect that the same time division multiplexing conversion circuit can be applied to both the multiplexing circuit and the demultiplexing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time division multiplexing conversion circuit of the present invention.

FIGS. 2A and 2B are waveform diagrams of respective parts for explaining the operation when FIG. 1 is used as a multiplex circuit and a separation circuit, respectively.

3A is a block diagram of an example of a multiplexing circuit of a conventional time division multiplexing conversion circuit, and FIG. 3B is a waveform diagram of each part for explaining the operation of FIG.

4A is a block diagram of an example of a separation circuit of a conventional time division multiplexing conversion circuit, and FIG. 4B is a waveform diagram of each part for explaining the operation of FIG. 4A.

[Explanation of symbols]

11, 12, 13, 14 Input information storage circuit 21 All input information storage circuit 22 Read / write control circuit 23 Demultiplex conversion information storage circuit 31, 32, 33, 34 Output information storage circuit 41, 42, 43, 4481, 82 , 83, 84 speed conversion circuit 51, 71, 72, 73, 74 selection circuit 61, 91 timing generation circuit 101, 102, 103, 104, 301, 302, 3
03,304,401 Input Highway 105,107,109,111,114,116,1
18,120,305,307,309,311,40
3,405,407,409 Information 106,108,110,112,115,117,1
19,121 Control timing signal 113 Address signal 122,123,124,125,313,410,4
11,412,413 output highway 306,308,310,312,402,404,4
06,408 Timing signal

Claims (3)

[Claims] 1. A plurality of input information storage circuits for sequentially storing a plurality of input highway information in accordance with the speed of each input highway, and all inputs for transferring all information from the plurality of input information storage circuits at a constant cycle. An information storage circuit, a demultiplexing conversion information storage circuit that stores in advance information about which input highway information to output at which position on which output frame, and the demultiplexing conversion information storage circuit. A read / write control circuit that generates a control timing signal when the information is read from the entire input information storage circuit based on the information and stored in the output information storage circuit corresponding to the output highway; and the information stored by the control timing signal. A plurality of output information storage circuits for reading and outputting according to the speed of each output highway. Division multiplex conversion circuit. 2. The time division multiplex conversion circuit according to claim 1, wherein each of the input information storage circuits is a first-in first-out type memory having a capacity of two frames or more. 3. The time division multiplex conversion circuit according to claim 1, wherein the all input information storage circuit is a memory having a two-sided structure.