JPH04290121A - Speed converting circuit - Google Patents

Abstract

PURPOSE:To prevent the read data from passing ahead the write data by a simple circuit which uses only one elastic store as to the speed converting circuit which converts the speed of data by varying the write speed of data to the elastic store and the read speed. CONSTITUTION:A fast reset signal generating circuit 5 generates a write reset/ read reset signal which performs control so that the fast data of plural frames are written in and read out of the elastic store 1 by single-time resetting by thinning out an original write reset signal supplied, frame by frame. A slow reset signal generating circuit 4 generates a slow read reset/reset signal which performs control so that the slow data of said frames are read continuously out of the elastic store 1 by single-time resetting. A fast-read reset signal and a slow-read reset signal are delayed behind a slow-write reset signal and a fast-write reset signal by specific timing so that the written data in a certain frame is read out in successive frames.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit that converts the speed of data by changing the speed at which data is written to and read from an elastic store.

0002

2. Description of the Related Art In a synchronous multiplexing device using a digital synchronous multiplex communication system, low-speed data (zero-order group data) that occupies the entire frame period, for example, is 8 bits, is time-compressed and converted into high-speed data. Low-speed → high-speed conversion output to the time slot (channel), or vice versa, high-speed →
Performing slow speed conversion.

[0003] For this purpose, an elastic store is used in which writing and reading can be controlled using independent timing and clocks. In the case of 64 kb/s zero-order group data in which high-speed data and low-speed data have the same frame phase and the low-speed data occupies the entire frame length of 125 μs with 8-bit 1-channel data, for example, 8 Mb/s
In order to perform speed conversion without missing or duplicating data, no matter where the time slot in the frame of the high-speed side data is set, it is necessary to add one to the elastic store.
After writing of data for the frame is completed, it is necessary to read it in the next frame. That is, in the case of 64K → 8M conversion, reading is performed in a predetermined time slot of the next frame after the written frame, and in the case of 8M → 64K conversion, no matter which time slot the input high-speed data is set to, the corresponding After writing of 8M data in a time slot is completed, it is necessary to read out the data as low-speed data from the beginning of the next frame period. Conventionally, for this purpose, two elastic stores were used, input data on the writing side was written to the two elastic stores alternately using a selector, and reading was switched in the opposite direction, and writing was completed from one elastic store. A double buffer system was used in which the data of the previous frame was read out, and the data of the current frame was written into the other elastic store.

0004

SUMMARY OF THE INVENTION The conventional speed conversion circuit described above has a problem in that it requires two elastic stores and a selector circuit, making the circuit complicated.

The present invention was created in view of the above problems, and it is an object of the present invention to prevent read data from overtaking write data using a simple circuit using one elastic store.

[0006]

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of a speed conversion circuit according to the present invention. As shown in FIG. 1, the above problem is solved by elastic stores 1 and 2 that sequentially write input data in synchronization with a write clock and sequentially read and output the written data in synchronization with a read clock that has a different speed than the write clock. is used to convert the speed between low-speed data that occupies the entire frame and high-speed data in a time slot shorter than one frame length while maintaining the frame phase. By thinning out the reset/read reset signal, the elastic stores 1 and 2 can be read with a single reset.
a high-speed reset signal generation circuit 5 that generates a write reset/read reset signal that controls writing/reading of high-speed data for multiple frames to the elastic store; and a low-speed reset signal generation circuit 4 that generates a low-speed read reset/write reset signal from a frame clock to control so that read/write of low-speed data for frames is performed continuously, and both of the reset signal generation circuits described above. 4 and 5 delay the high-speed read reset signal/low-speed read reset signal by a predetermined timing from the low-speed write reset signal/high-speed write reset signal so that the written data of a certain frame is read in the next and subsequent frames. This is solved by the speed conversion circuit of the present invention, which is characterized in that it generates.

[0007]

[Operation] Data for multiple frames is written with one reset signal, and data for multiple frames is read out with one reset signal, and the data written in each frame is written in each subsequent frame. Since the data is read out, speed conversion can be performed without reading overtaking writing and causing data loss or duplication.

[0008] By simply providing a simple circuit that thins out the high-speed reset signal and a circuit that generates the low-speed reset signal from the frame clock, the number of elastic stores and selectors can be reduced, making it possible to simplify the circuit configuration. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A speed conversion circuit according to the present invention will be explained below with reference to the accompanying drawings. FIG. 2 is a configuration diagram of an embodiment of the speed conversion circuit of the present invention, FIG. 3 is a time chart of 8 Mb/s → 64 Kb/s conversion, and FIG. 4 is a time chart of 64 Kb/s → 8 Mb/s conversion. Note that the same reference numerals represent the same objects throughout the figures.

In the embodiment, the frame frequency is 8 KHz, the input and output frame phases are synchronized, and low-speed data is
A case will be explained in which the frame length (125 μs) is a 64 Kb/s PCM signal occupied by 8-bit data, and the high-speed data is 8 Mb/s data that is 125 times faster.

In FIG. 2, 1 is an elastic store for low speed → high speed conversion, 2 is an elastic store for high speed → low speed conversion, 41 is a decoder, 42 is a D-FF, 51
, 52 is an OR gate, and 53 is an inverter. Elastic stores 1 and 2 are the same, and perform speed conversion from high speed to low speed and from low speed to high speed, respectively, using various control signals described below. Elastic stores 1 and 2 have a capacity of 256 bits, write the data input to the data input Din in synchronization with the write clock WCK, and output the data written in synchronization with the read clock RCK. It has a function to output from Dout. Elastic stores 1 and 2 have built-in write address counters and read address counters, and when the write inhibit signal Wi is "L", the write clock is invalidated, the counters do not increment, and no writing is performed. Further, the write address counter is reset to address 1 by the write reset signal WR being "L". The read address counter is reset to the 1st address at the 5th read clock from the timing when the read reset signal RR goes "L", and the read inhibit signal Ri goes "L".
In this case, the clock after four clocks is invalidated, the counter does not increment, and no reading is performed.

The low-speed read inhibit signal LRi of the elastic store 1 for reading low-speed data and the low-speed write inhibit signal LWi of the elastic store 2 for writing low-speed data are always set to the "H" level during the entire period of the frame. Low-speed data reading or writing is performed over a period of time.

64 synchronized with 64Kb/s low-speed data
The KHz clock is supplied to the write clock terminal WCK of the elastic store 2 to which low-speed data is written, and to the read clock terminal RCK of the elastic store 1 which is inverted by an inverter 53 and read out the low-speed data.

The decoder 41 receives an 8kHz frame clock and a 4K signal obtained by dividing or multiplying the frame clock.
Hz, 16KHz, 32KHz clocks are input,
The Y2 output has the timing when 8kHz and 32kHz are “L”, that is, “L” at the 3rd bit from the beginning of the frame.
The signal is 8kHz, 16KH for Y7 output.
The signal that becomes "L" at the timing when all of
The pulse width of the Y2 output has a length of one cycle of a 64KHz clock, and is hit by the D-FF42 with a 64KHz clock, shifted by half a cycle of the 64KHz clock, and is output at a low speed. The read reset signal LRR is supplied to the read reset terminal RR of the elastic store 1 for high-speed → low-speed conversion.The Y7 output is a low-speed write reset signal LWR in which the 8th bit from the beginning of the frame becomes "L" every 2 frames. The signal is supplied to the write reset terminal WR of the elastic store 2 for low-speed → high-speed conversion.

That is, the decoder 3 and the D-FF 4 output a reset signal of 1 to control the reading of low-speed data from the elastic store 1 and the writing of low-speed data to the elastic store 2 starting from the first bit of the frame. It constitutes a low-speed reset signal generation circuit that generates every frame.

For writing and reading high-speed data, a high-speed write reset signal HWR and a high-speed read reset signal HRR are supplied from a highway control LSI (not shown) every frame at the timing of a time slot that specifies a channel within the frame. but,
The write reset signal is output by OR gate 51, and the read reset signal is output by OR gate 52 at 4KHz.
Since it is blocked while the clock is at the "H" level, it is thinned out every other frame and supplied to the elastic stores 1 and 2. That is, the OR gates 51 and 52 constitute a high-speed reset signal generation circuit that thins out the reset signals supplied every frame.

[0017] Then, the desired time slot width is set to "H".
A high-speed write inhibit signal HWi and a high-speed read inhibit signal HRi are supplied to the elastic stores 1 and 2 every frame.

Next, the operation of high speed to low speed conversion will be explained with reference to FIG. Elastic store write counter is 4KH
It is reset by the high-speed reset signal HWR applied during the period of frame #1 when the z clock is “L”,
Of the 8 Mb/s input data, b1 to b8 of frame #1 corresponding to the time slot specified by the "H" level of the high-speed write inhibit signal HWi are from addresses 1 to 8, and b1' to b8 of frame #2 are ' are sequentially written from address 9 to address 16. On the other hand, for low-speed data of 64 Kb/s, the read counter reads the 3rd bit of frame #1 (5 bits from frame #2).
Since the first bit of frame #2 is reset to address 1 by the low-speed read reset signal LRR applied at the timing of (before bit), data b1 to b8 from address 1 are stored in frame #2, and data b1 to b8 from address 1 in frame #3 are
The data b1' to b8' after the address are sequentially read out over the entire frame length and output.

In the low-speed → high-speed conversion shown in FIG. 4, 64 Kb/s
Input data is changed to 8 bits b1 to 8 bits of frame #1 by the low-speed write reset signal LWR applied to the 8th bit of frame #0 corresponding to the "L" period of the 4KHz clock.
b8 is sequentially written from address 1 to address 8, and 8-bit data b1' to b8' of frame #2 are sequentially written from address 9 onward. On the other hand, for reading, the high-speed read reset signal is thinned out during the period of frame #1 when the 4KHz clock is "H" and is reset in the next frame #2, so the frame # specified by the high-speed read inhibit signal "H" 2 predetermined time slots from address 1 to 8
Data b1 to b8 up to the address are read at a speed of 1 Mb/s, and since there is no reset signal in frame #3, 9
Data b1' to b8' from address to address 16 are read out.

In this way, the write address counter reset signal is applied only once to a plurality of frames, input data is written over a plurality of frames, and an error is generated so that the data of the frame for which writing is completed will be read in the next frame. By controlling the write/read timing for the stick store, speed conversion can be performed with a simple circuit without slipping.

[0021]

As explained above, according to the present invention, only one elastic store is used to store low-speed data that occupies the entire period of the frame and high-speed data that occupies a part of the time slot of the frame at the same frame phase. Speed conversion between data and data can be performed without slipping, which has the effect of simplifying the speed conversion circuit.

[Brief explanation of the drawing]

[Figure 1] Principle diagram of the speed conversion circuit of the present invention

[Figure 2]
Embodiment configuration diagram of the speed conversion circuit of the present invention

[Figure 3] 8
Mb/s → 64Kb/s conversion time chart

[Figure 4
] 64Kb/s → 8Mb/s conversion time chart

[Explanation of symbols]

Claims (1)

[Claims] [Claim 1] Using an elastic store (1) that sequentially writes input data in synchronization with a write clock and sequentially reads and outputs the written data in synchronization with a read clock having a speed different from the write clock, The original write reset/read reset signal is supplied for each frame in a speed conversion circuit that performs speed conversion between low-speed data that occupies the entire interval and high-speed data in a time slot shorter than one frame length while maintaining the frame phase. A high-speed reset signal that generates a write reset/read reset signal that controls writing/reading of multiple frames of high-speed data to/from the elastic store (1) in a single reset by thinning out the elastic store (1). a generation circuit (5), and a low-speed read reset/write reset signal for controlling the plurality of frames of low-speed data to be read/written continuously to the elastic store (1) with a single reset. Low-speed reset signal generation circuit (4) that generates from the frame clock
and both reset signal generation circuits (4, 5).
converts the high-speed read reset signal/low-speed read reset signal to the low-speed write reset signal/
A speed conversion circuit that generates a high-speed write reset signal with a predetermined timing delay.