JPH09275594A - Time division switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace a time slot of a multiplexed signal without limiting a speed of a clock signal of an input multiplex signal and that of an output multiplex signal to be a same speed. SOLUTION: Each bit string of an input multiplex signal 200 is stored in a speech memory section 12 according to a write address signal 100 fed from a control memory 14, the bit string is read according to a read address signal 102 and an output multiplex signal 206 is outputted. The write address signal 100 is address information to attain random write or sequential write to the speech memory section 12 and the read address signal 102 is address information making random read or sequential read to the speech memory section 12 and the signal 100 is generated by a 1st control memory section 18 corresponding to the clock speed of the input multiplex signal depending on a mode signal 210 and the signal 102 is generated by a 2nd control memory section 20 corresponding to the clock speed of an output multiplex signal 206.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division type switch for exchanging time slots of digital multiplexed signals, and more particularly to a time division type switch suitable for application to a digital exchange.

[0002]

2. Description of the Related Art Conventionally, for example, a digital exchange has a time switch (TS) for changing the time positions of time slots of a multiplexed signal which is K-multiplexed (K is a natural number) within a period T.
W) performs time slot replacement processing.
This time switch is, for example, a call memory (SPM) that stores a K multiplexed signal within a cycle T, and a control memory (SCM) that generates an address for accessing the call memory.
And a sequential counter for generating a sequential address for accessing the call memory, and the time slot interchange processing is performed by changing the writing order and the reading order of the multiplexed signal to the call memory. In this way, the time slot replacement process is performed according to the value stored in the control memory of the time switch.

The time slots are exchanged by reading the contents of the control memory in the time switch (TSW). The operation of the time switch TSW includes (1) a method of exchanging time slots by sequential write and random read, or (2) a method of exchanging time slots by random write and sequential read. The addresses output from the sequential counter and the control memory are generated, for example, in synchronization with the clock signal of the input multiplexed signal.

[0004]

However, in the above-described time switch, the time slot replacement processing within the frame period T is performed in synchronization with a single clock signal, and the output is performed in synchronization with this clock signal. Since the multiplexed signal is output, the clocks of the input multiplexed signal and the output multiplexed signal are limited to the same speed. Therefore, the clock of the input multiplexed signal and the clock of the output multiplexed signal cannot be set independently of each other, and as a result, the input multiplexed signal is input at the speed and the output multiplexed signal is output at the desired speed. Could not output the time slot of.

Further, a time switch function and a speed conversion function are used by using a time switch and an elastic store memory (ES) in order to make the speed of the input multiplexed signal different from the speed of the output multiplexed signal. However, in this case, there is a problem in that the scale of the hardware becomes large and a highly reliable and compact device cannot be configured.

The present invention solves the above drawbacks of the prior art, and makes it possible to interchange the time slots of the multiplexed signal without limiting the clocks of the input multiplexed signal and the output multiplexed signal to the same speed. An object of the present invention is to provide a time division type switch capable of varying the speeds of an input multiplexed signal and an output multiplexed signal.

[0007]

In order to solve the above-mentioned problems, the present invention outputs the second multiplexed signal by exchanging the time slots of the first multiplexed signal input via the digital transmission line. In the time division type switch, the switch stores a bit string of each time slot of the first multiplexed signal, reads the stored bit string, and outputs a second multiplexed signal, and a call memory Address control means for designating an address, the address control means for generating a first address signal for designating addresses of the call memory in a first address order of either random or sequential, and a call control means. Generates a second address signal that specifies the bit string stored in the memory in a random or sequential second address order. The call memory, including read control means, stores bit strings in the order of the first address specified by the first address signal, and stores the stored bit string in the order of the second address specified by the second address signal. , The second multiplexed signal is read out and output in the multiplexing cycle.

In this case, the write control means generates a first address signal that makes one round in the multiplexing cycle of the first multiplexed signal, and the read control means, the read control means. It is preferable that the address control means generates the second address signal that makes one round at, and the address control means generates the first and second address signals based on the first and second clocks having different speeds and supplies them to the call memory. .

In this case, the write control means counts the first address control memory for storing the first address signal and the first clock, and the first count value is used as the first address control memory or The reading control includes: first counting means for outputting as an address in the call memory; and first selecting means for selecting and outputting either the output of the first address control memory or the output of the first counting means. The means counts a second address control memory that stores a second address signal and a second clock, and outputs the second count value to a second count value.
Second counting means for outputting as an address in the address control memory or the communication memory, and second selecting means for selecting and outputting either the output of the second address control memory or the output of the second counting means. The call memory stores a bit string according to a first address signal output from the first selecting means, reads the stored bit string according to a second address signal output from the second selecting means, and It is preferable to output the second multiplexed signal of the bit string.

In this case, the first and second address control memories respectively input the address information for designating the addresses of the call memory in an arbitrary order and the address for storing the address information. It is preferable that the memory has a port and a second port that inputs an address that sequentially specifies the stored address information and outputs address information corresponding to the address as first and second address signals.

Further, the first selecting means inputs a mode signal designating the operation mode of the switch, and outputs the output of the first address control memory and the output of the first counting means in response to the mode signal. You may choose either one.

The second selecting means inputs a mode signal designating the operation mode of the switch, and outputs the output of the second address control memory and the output of the second counting means in response to the mode signal. You may choose either one.

Further, the write control means receives a mode signal designating an operation mode of the switch, and a first selection circuit for selecting either a random write mode or a sequential write mode in accordance with the mode signal. Including,
A first address signal corresponding to the selected mode may be supplied to the call memory.

The second control means receives a mode signal designating the operation mode of the switch, and a second selection circuit for selecting either the random read mode or the sequential read mode according to the mode signal. And a second address signal corresponding to the selected mode may be supplied to the call memory.

The call memory has a first port for inputting the first multiplexed signal and the first address signal, and a second port for inputting the second address signal and outputting the second multiplexed signal. And a memory having a port of.

The call memory has first and second storage means for storing a bit string, and the first and second storage means store the first multiplexed signal for each bit string of each multiplexing period. The bits may be stored alternately, and the stored bit strings may be alternately read out and output in a multiplexing cycle.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a time division type switch according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, there is shown an embodiment of a time division type switch to which the present invention is applied. This time-division type switch (TSW) 10 is, for example, in a time-division speech path device of a digital exchange, a time for switching time slots of digital multiplexed signals from an input highway (transmission path) and outputting to an output highway (transmission path). Switch (TSW; T
ime Switch or TSI; Time Slot Interchanger). The time divisional switch 10 in this embodiment has an input 200
8-bit parallel input multiplexed signal (Di7 to Di
0) is stored at the timing corresponding to the write clock signal WCLK input to the input 202, and the stored multiplexed signal is read at the timing corresponding to the read clock signal (RCLK) input to the input 204. , This is the output multiplexed signal (Do7
It is a memory switch that outputs to output 206 as ~ Do0). Particularly, in the time division type switch 10, the bit string of each time slot of the input side multiplexed signal (Di7 to Di0) and the output side multiplexed signal (Do7 to Do0) is the write clock signal (WCLK) and According to the clock speed of the read clock signal (RCLK), input or output is performed at different speeds in this embodiment. In the following description, parts not directly related to the present invention are not shown and described, and reference numerals of signals are represented by reference numerals of connection lines in which the signals appear.

First, the input multiplexed signal (Di7 to Di0) 200 is
It is a K multiplex signal in which K time slots (TS) are multiplexed within a frame period T, and each time slot is an 8-bit parallel signal. The time-division switch 10 has a frame signal indicating the delimiter of the frame period T of the input multiplexed signal 200.
(F) is input to input 208. This frame signal (F) is input to the time division type switch 10 at the timing of 0 TS of the input multiplexed signal (Di7 to Di0) 200. As will be described later, the time division type switch 10 generates a sequential address for designating a storage position of an input multiplexed signal based on a frame signal (F) 208 and a write clock signal (WCLK) 202, and also a frame signal. It has a function of generating a sequential address designating the read position of the stored multiplexed signal based on (F) 208 and the read clock signal (RCLK) 204. Further, the time division type switch 10 has a function of generating a random address for exchanging time slots, and switching between the random address and the sequential address is performed by inputting the value of the mode signal (MODE0, MODE1) input to the input 210. It is decided according to.

The time-division type switch 10 also receives an input 212 for inputting an address signal (A), an input / output 214 for inputting / outputting bidirectional data (I / O), and a write signal (W / R). Input 216, a chip select signal (CS0 and CS1) input 218, and a read enable signal (OE0 and OE1) input 220. Used to preset the replacement control of the.

The output multiplexed signal 206 is an L multiplexed signal in which L time slots (TS) are multiplexed within the frame period T, and each time slot is an 8-bit parallel signal.
Each bit string of the output multiplexed signal 206 is a read clock signal.
It is output to output 206 in synchronization with (RCLK) 204.

The internal structure of the time division type switch 10 is shown in FIG. The time division type switch (TSW) 10 is a call memory unit (SPMB) 12 that stores each bit string of the multiplexed signal at a predetermined address.
And a control memory unit (SCMB) 14 that generates an address signal 212 that specifies the address of the storage area in the call memory unit 12.
And a timing unit (TIMB) 16 for generating a timing for storing the multiplexed signal in the call memory unit 12, a timing for reading the stored multiplexed signal, and the like.

Speech memory unit (SPMB)
Block 12 is a time switch for temporarily storing the multiplexed signal, exchanging time slots, and outputting.
The call memory unit 12 in this embodiment is a control memory (SCMB).
Input the write address signal (SPMWA) 100 and the read address signal (SPMRA) 102 supplied from the
16 SPM memory selection signal (SPMSEL) 104 and S
The PM write enable signal (SPMWE) 106 is input to perform an exchange operation of temporally interchanging the time slots of the input multiplexed signal 200. The call memory unit 12 outputs the output multiplexed signals (Do7 to Do0) whose time slots are exchanged to the output 206.

In the present embodiment, the time slots are switched by designating different addresses for the writing order and the reading order of the multiplexed signal to the call memory unit 12. However, the present invention is not limited to this, and for example, the call memory unit 12
It is possible to specify the writing order and the reading order of the multiplexed signal with respect to the same address so that the time slots of the input multiplexed signal 200 and the output multiplexed signal 206 are not interchanged. When the same address is designated in this way, the same random address or the same sequential address at the time of writing and at the time of reading may be supplied to the call memory unit 12.

FIG. 3 shows the detailed structure of the call memory unit 12. The call memory unit 12 alternately stores the frames of the input multiplexed signals (Di7 to Di0) 200 as shown in FIG. Two call memories (SPM0) 300 and (SPM1) 302,
A selector circuit 308 that selects the output 304 or 306 of these call memories and connects the selected output to the output 206, and an inverter (INV) that inverts the level of the SPM memory select signal (SPMSEL) 104 and supplies it to the call memory 302. Including 310 and.

Call memory (SPM0) 300 and (SPM1) 302
Input (Di) 200 to input the input multiplexed signal (Di7 to Di0)
And input the write address signal (SPMWA) Input (WA) 100
And input (W to input SPM write enable signal (SPMWE)
E) 106 and respectively. In addition, call memory (SPM0) 30
0 is the input (CS) for inputting the SPM memory selection signal (SPMSEL) 10
4 and the call memory (SPM1) 302 is the SPM memory selection signal.
It has an input (CS) 312 for inputting the inverted signal of (SPMSEL).
These inputs Di, WA, WE and CS are used as call memories 300 and 3
It is formed in each port 1 of 02.

Furthermore, the call memory (SPM0) 300 and (SPM1)
302 is an input (RA) 1 for inputting a read address signal (SPMRA)
02 and output (Do) 304 that outputs the read multiplexed signal
Or output (Do) 306 and these input (RA)
And the output (Do) is formed on port 2 of the call memory. Thus, the call memory 300 and
The 302 has a dual-port RAM configuration.
It is switched by the SPM memory select signal (SPMSEL) input to S) 104 and input (CS) 312.

For example, SPM memory selection signal (SPMSEL) 104
Goes high and the write address signal (SPMRA) 100
The SPM write enable signal (SPMWE) 106 and the call memory (SPMWE
0) When input to 300, input multiplexed signal 200
Written to (SPM0) 300. On the other hand, the SPM memory select signal (SPMSE
When the inverted signal (low level) of L) 104 is input to the input (CS) 312, the call memory (SPM1) 302 outputs the time slot of the address corresponding to the read address signal (SPMRA) input to the input 102. Output to 306.

Further, for example, the SPM memory selection signal (SPMSE
L) 104 goes low and the write address signal (SPMW
When A) 100 and the SPM write enable signal (SPMWE) 106 are supplied to the call memory (SPM0) 302, the input multiplexed signal 200 is written in the call memory (SPM1) 302. Meanwhile, the inverter
Inversion signal (high level) of SPM memory selection signal (SPMSEL) of 310 output is input (CS)
(SPM1) 301 is the read address signal input to input 102.
Output time slot of address according to (SPMRA) 304
Output to

As described above, the call memory unit (SPMB) 12 alternately switches between writing and reading in response to the SPM memory selection signal (SPMSEL) 104, and a double buffer type call memory unit 12 capable of apparently reading and writing simultaneously. Are configured.

The outputs 304 and 306 of the call memories 300 and 302 are respectively connected to the input (0) side and the input (1) side of the selection circuit (SEL) 308, and the selection circuit (SEL) 308 is connected to the SPM memory selection signal (SPMSEL). ) 104 is input to its input (S), and the output of one of the call memories 300 and 302 is selected according to the selection signal 104. The selection circuit 308
For example, when the SPM memory selection signal (SPMSEL) 104 goes high, the input (1) 306 side is selected and conversely the selection signal (SPMSE)
When L) 104 becomes low level, input (0) 304 side is selected.
The selection circuit 308 connects the selected input (0) 304 or input (1) 306 to its output 206 and outputs the multiplexed signal output from the call memory 300 or 302 to the output 206. As described above, the SPM memory selection signal (SPMSEL) 104 has a function of selecting and switching the call memory 300 or 302 for each frame of the multiplexed signal and also switching the output of the selected call memory.

Returning to FIG. 1, the control memory unit (SCMB; Speech)
The Path Control Memory Block) 14 is an address control memory that generates an address signal that specifies the writing order and the reading order of the multiplexed signal in the call memory unit 12 and supplies the address signal to the call memory unit 12. In addition, the control memory unit (SCM
B) 14 supplies sequential addresses and / or random addresses to the call memories 300 and 302 to swap the time slots of the multiplexed signal.

More specifically, the control memory unit 14 is a call memory unit.
A write address signal (SPMWA) 100 for performing a sequential write or a random write for storing the input multiplexed signal 200 to 12 is generated. Further, the control memory unit 14
Generates a read address signal (SPMRA) 102 for performing sequential read or random read for reading the multiplexed signal stored in the call memory unit 12. When performing random write and random read, the control memory unit 14 inputs the address information set in advance by the upper control device 230 (FIG. 2) to the bidirectional data input (I / O) 214.
Then, the address represented by the data is stored.

As shown in FIG. 1, the control memory unit 14 includes a first control memory unit (SCMB0) 18 for generating a write address signal (SPMWA) 100 for the call memory unit 12 and a read operation for the call memory unit 12. A second control memory unit (SCMB1) 20 for generating an address signal (SPMRA) 102 is included.

The first control memory unit (SCMB0) 18 has an address signal (A) 212, bidirectional data (I / O) 214, a write signal (R / W) 216, as shown in FIGS. Read enable signal (OE0) 220, chip select signal (CS0) 218, mode signal
Input (MODE0) 210 and write clock signal (WCLK) 202 respectively. Further, the control memory unit 18 includes the timing unit 16
Input the frame timing signal (FT0) supplied from
Type in 8. In addition, the control memory unit 18 uses the mode signal (M
Write address signal (SPMW0) depending on the random address or sequential address specified by ODE0) 210
A) is output to the output 100 to which the call memory unit 12 is connected.

The second control memory unit (SCMB1) 20 has an address signal (A) 212, bidirectional data (I / O) 214, write signal (R / W) 216, as shown in FIGS. Read enable signal (OE1) 220, chip select signal (CS1) 218, mode signal
Input (MODE1) 210 and read clock signal (RCLK) 204 respectively. In addition, the control memory unit 20 includes a timing unit 16
Input the frame timing signal (FT1) supplied from
Enter 0. Further, the control memory unit 20 uses the mode signal (M
ODE1) Read address signal (SPMR) corresponding to the random address or sequential address specified by 210
A) is output to the output 102 to which the call memory unit 12 is connected.

First and second control memory units 18 and 20
6 and 7 respectively show the internal configuration of the above, the control memory units 18 and 20 include a control memory, a counter, and a selection circuit, respectively. The first control memory unit (S
The control memory (SCM0) 400 of the CMB0) 18 is composed of a dual port RAM having a port 1 and a port 2, and each port operates independently of each other.

The control memory 400 is a random access memory having a storage area for storing write addresses for K multiplex time slots that make one round in the frame period T.
Address signal (A) 21 supplied from the host controller 230
2, bidirectional data (I / O) 214, write signal (W / R) 216, chip select signal (CS0) 218 and read enable signal (O
E0) 220 is input to port 1 and a write address for random writing to the call memory unit 12 is stored in advance. In this way, the control memory 400 has 30
The write addresses for 0 and 302 are stored, and the time slot switching control method of the time division switch (TSW) 10 is set in advance. For example, the input multiplexed signal 20
When 0 is randomly written to the call memories 300 and 302, the control memory 400 inputs the write address corresponding to these address designations in advance to the input 214 and stores it in the storage position corresponding to the address signal (A) 212. To do.

The port 2 inputs the count value sent from the counter (CNT) 402 to the input 404, and the call memories 300 and 30
Write address signal for random write to 2
(SPLWA) are sequentially read and output to the output 406. When performing random write in this way, the write address for performing random write to the call memories 300 and 302 is stored in a predetermined storage position in advance, and the count value supplied from the counter (CNT0) 402 is stored. Reference numeral 404 represents a sequential address for the control memory 400, the control memory 400 reads the stored data corresponding to the address represented by the count value 404, and outputs the random address for the call memory unit 12 to the output 406.

A counter (CNT0) 402 that outputs a count value 404
Is a sequential counter that receives the write clock signal (WCLK) 202 and the frame timing signal (FTO) 108, respectively, and counts the number of the write clock signals for each frame cycle T indicated by the frame timing signal 108. . This count value 404 is the frame timing signal (FT0) 1
It is reset at the input timing of 08, and is output to the output 404 as a sequential address for each frame period T indicated by a binary number at a speed corresponding to the cycle of the write clock signal (WCLK). This count value 404 is used as a read address for reading from the control memory 400 address data for performing random write to the call memory unit 12 when an operation mode described later (for example, random write) is set. Selection circuit described next
If the count value 404 is selected on the 408, the call memory
Functions as a write address (SPMWA) for 300 and 302. The output 406 of the control memory 400 is connected to the input (0) side of the selection circuit 408, and the output 404 of the counter 402 is connected to the input (1) side of the selection circuit 408.

The selection circuit (SEL) 408 has a selection signal input (S) 210
Control memory according to the mode signal (MODE0) input to
It is a selector that selects the input 406 to which the output of 400 is connected or the input 404 to which the output of the counter 402 is connected, and connects the selected input to the output 100. The selection circuit 408 selects the input (0) 406 side when the value of the selection signal input (S) 210 indicates 0, and inputs (1) when the value of the selection signal input (S) 210 indicates 1. Select 404. Therefore, the selection circuit 408 outputs the random address 406 sequentially read from the control memory 400 when the mode signal (MODE0) 210 indicates 0, and sequentially outputs the random address 406 when the mode signal (MODE0) 210 indicates 1. Output sequential address 404. The output 100 of the selection circuit 408 is the control memory block (SCMB0) 1
8 outputs to configure the inputs of call memories 300 and 302 (W
The write address signal (SPLWA) 100 corresponding to the mode signal (MODE0) 210 is supplied to the call memory unit (SPMB) 12. As described above, the control memory unit (SCMB) 14 is an address that specifies the storage location of the multiplexed signal stored in the call memories 300 and 302 according to the mode signal (MODE0) 210 supplied from the upper control device 230. Generate a signal.

The second control memory unit (SCMB1) 20 shown in FIG.
Is the first control memory unit shown in FIG. 6 except that a read address (SPMRA) 102 for the call memory unit 12 is generated.
A configuration similar to that of 18 may be used. That is, the control memory 20 includes a control memory (SCM1) 500 and a counter (CNT1) as shown in FIG.
502 and a selection circuit 504 are included. Control memory (SCM1) 500
Is an address signal supplied from the upper control device 230.
(A) 212, bidirectional data (I / O) 214, write signal (W / R) 216,
Input the chip select signal (CS1) 218 and read enable signal (OE1) to port 1,
A read address for random reading with respect to 12 is stored in advance at a position corresponding to the address signal (A) 212.
This read address is a read address for an L-multiplexed time slot that makes one round in the frame cycle T. Further, the control memory 500 inputs the count value sent from the counter (CNT1) 502 to the input 506 and reads out the read address signal (SPLR) for random reading to the call memories 300 and 302.
A) is sequentially read from the control memory 500 and output to the output 508 of port 2.

A counter (CNT1) 502 that outputs a count value 506
Inputs the read clock signal (RCLK) 204 and the frame timing signal (FT1) 110, respectively.
CLK) signal 204 is counted for each frame cycle T indicated by the frame timing signal (FT1) 110, and the counted value is output.
It supplies the control memory 500 and the selection circuit 504 connected to 506. The count value 506 is the frame timing signal (FT
1) 110 is reset at the input timing and is output to the output 506 as a sequential address for each frame period indicated by a binary number at a speed according to the cycle of the read clock signal (RCLK). This count value 506 is used as a read address for reading from the control memory 500 address data for performing random read to the call memory unit 12 when an operation mode (for example, random read) described later is set. When the count value 506 is selected by the selection circuit 504, the call memory 300 and
It functions as a read address (SPMWA) 102 for 302.

The selection circuit 504 controls the control memory 500 according to the mode signal (MODE1) input to the selection signal input (S) 210.
Select the input 508 to which the output of is connected or the input 506 to which the output of the counter 502 is connected, and output the selected input to 10
Connect to 2. The selection circuit 408 selects the input (0) 508 when the value of the selection signal input (S) 210 indicates 0, and the input (1) 506 when the value of the selection signal input (S) 210 indicates 1. Select. Therefore, the selection circuit 504 determines that the mode signal (MODE1) 210
If the value of 0 indicates 0, the random address 508 sequentially read from the control memory 500 is output, and the mode signal (MODE
1) When 210 indicates 1, the sequential address 506 sequentially output from the counter 502 is output. Selection circuit 50
The output 102 of 4 constitutes the output of the control memory (SCMB1) 20 and is connected to the inputs (RA) of the speech memories (SPM) 300 and 302, respectively, and the read address signal (SPLRA) corresponding to the mode signal (MODE1) 210 is output. ) 102 is supplied to the call memory unit (SPMB) 12.

As described above, the exchange operation mode of the time-division type switch 10 is set according to the mode signals (MODE0, MODE1) given to the control memory unit 14 from the host controller 230. For example, the mode signal (MOD
When E0) is 0 and the mode signal (MODE1) is 0, the first mode for performing random write and random read to the call memory unit 12, when the mode signal (MODE0) is 0 and the mode signal (MODE1) is 1 The second mode for performing random write and sequential read, mode signal (MODE
0) is 1 and the mode signal (MODE1) is 0, the third mode that performs sequential write and random read, mode signal (MODE0) is 1 and mode signal (MODE1) is 1
In this case, either of the operation modes of the fourth mode of performing the sequential write and the sequential read is set in the time divisional switch 10.

Returning to FIG. 1, the timing section (TIMB) 16 is
It is a timing control unit that controls operation timing in the call memory unit 12 and the control memory unit 14. The timing block (TIMB) 16 has a frame signal (F) 208 and a write clock signal.
(WCLK) 202 and read clock signal (RCLK) 204 are input, and the SPM memory selection signal for the call memory (SPMB) 12.
(SPMSEL) 104 and SPM write enable signal (SPMWE) 106 are output. Furthermore, the timing block (TIMB) has a control memory (S
CMB0, SCMB1) 300 and 400 frame timing signals (F
Outputs T0, FT1) 108 and 110 respectively.

More specifically, the timing section 16 uses the frame signal (F) 208 as a trigger as shown in FIG.
An SPM memory selection signal (SPMSEL) 104 which is inverted every time is generated, and writing and reading of the multiplexed signal in the call memories 300 and 302 are alternately switched every frame period T. In addition, the timing unit 16 uses the frame signal (F) 2
08 and the write clock signal (WCLK) 202, the SPM write enable signal (SPMW) that indicates the write timing of the cycle synchronized with the time slot of the input multiplexed signal 200.
E) Generate 106. Further, the timing unit 16 includes a frame timing signal (FT0) 108 representing the frame start timing of the input multiplexed signal 200 and a frame timing signal representing the frame start timing of the output multiplexed signal 206.
(FT1) 110 (FIG. 9) are generated based on the frame signal (F) 208, respectively. These frame timing signals (FT0) 1
08 and the frame timing signal (FT1) 110 are signals that are at a high level during each 0 (TS) of the input multiplexed signal 200 or the output multiplexed signal 206.

Returning to FIG. 1, the host controller 230 synchronizes with the time slot of the input multiplex signal (Di7 to Di0) 200 and writes a write clock for writing this multiplex signal in the communication memory unit 12. A signal (WCLK) 202 and a read clock signal (RCLK) 204 for reading the multiplexed signal stored in the call memory unit 12 in synchronization with the output timing of the output multiplexed signal (Do7 to Do0) 206 are generated. . The control device 230 also generates a frame signal (F) indicating the delimiter of the frame period T.

The control device 230 further includes an address signal (A) 212 for designating the addresses of the control memories 400 and 500,
Bidirectional data (I / O) 214 representing addresses for the call memories 300 and 302, a write signal (W / R) 216 for writing address data to the control memory unit 14, and addresses from the control memory units 400 and 500. Set the read enable signal (OE0, OE1) 220 to enable data read, the chip select signal (CS0, CS1) 218 to select the control memory 400 or 500 to write, and the operation mode of the time-division type switch 10. Mode signals (MODE0, MODE1) 210 are generated. These signals are used by the time division type switch 10 when presetting the time slot replacement in the TSW10.
Is a control signal supplied to the. The control device 230 generates control signals for controlling these TSWs 10 on the basis of various clocks distributed from a speech communication system clock device (not shown), and supplies the generated control signals to the time division type switch 10.

With the above configuration, the time division type switch 10
The operation will be described with reference to FIGS. 8 and 9. In the following, as an example, a mode signal (MODE0) is sent from the host controller 230.
Is supplied to the time-division type switch 10 and a signal 210 representing a value of 1 and a value of the mode signal (MODE1) is 0, respectively, and time-division in the third mode in which sequential write and random read to the call memory unit 12 are set. The operation of the die switch 10 will be described. This operation example is 0 (T
Input each bit string of the input multiplexed signal (Di7 to Di0) in which the signal A is input to S), the signal B is input to 1 (TS), and the signal C is input to 2 (TS).
The time slot of this multiplexed signal is input to, for example, 0 (TS) to signal B, 1 (TS) to signal C, and 2 (TS) to signal A.
In this mode, each bit string of the output multiplexed signal (Do7 to Do0) is output to the output 206 by switching in the order of.

First, the control memory (SCM1) 500 of the control memory unit (SCMB1) 20 output from the host controller 230 is output.
Address data for storing 1 at the 0th address, 2 at the 1st address, and 0 at the 2nd address are sequentially input to the input (I / O) 214, and are stored in the control memory 500 in the order of the address indicated by the address signal (A) 212. It is stored in the storage area. At this time, as shown in FIG. 4, a chip select signal is generated for each address.
(CS1) 218 (high level) is supplied to the control memory 500, and the address signal is generated at the rising edge of the write signal (W / R) 216.
Bidirectional data (I / O) 214 indicating address data is stored in a storage position corresponding to (A) 212. In this manner, information indicating the read address (SPMRA) for performing random read from the control memory 500 to the call memory unit 12 sequentially.
(1,2,0) is stored in the control memory 500. On the other hand, in this embodiment, the control memory 400 has a chip select signal (CS0) 2
Data indicating an address when 18 (high level) is not supplied
214 is not stored. In this way, the read address (SPMRA) to the call memory unit 12 in the third mode is set in the control memory unit 14.

In such a state, the mode signal (MODE0) 210 indicating the third mode and the write clock signal (WCLK) 202 are supplied from the host controller 230 to the first control memory unit 18, and the mode is set. Signal (MODE1) 210 and read clock signal (RCLK) 20
4 and 4 are supplied to the second control memory unit 20. Further, based on the frame signal (F) 208 input to the timing unit 16,
The SPM memory select signal (SPMSEL) 104 is generated, and the SPM memory write enable signal (SPMWE) 106 is generated based on the write clock signal (WCLK) 202. Also, the timing unit 16
Based on the write clock signal (WCLK) 204 and the frame signal (F) 208 input to the frame timing signal (FT0) 108
Are generated and read clock signal (RCLK) and frame signal
A frame timing signal (FT1) 110 is generated based on (F). Generated frame timing signal (FT0) 108
Is supplied to the control memory unit 18, and the frame timing signal
The (FT1) 110 is supplied to the control memory unit 20. In addition, SPM
Memory selection signal (SPMSEL) 104 and SPM write enable signal
(SPMWE) 106 is supplied to the call memory unit 12.

A mode signal representing a sequential write is supplied to the selection circuit 408 of the control memory unit 18 to select the count value 404 of the counter 402, and the count value 404 is a write address signal for the call memories 300 and 302 ( SPM
WA) Output as 100.

In the control memory (SCMB1) 20, the count value 506 of the counter 502 is input as its read address in order to read the address data stored in advance,
Address data corresponding to this read address is read from the control memory 500. The read address data is selected by the selection circuit 504 to which the mode signal (MODE1) 210 representing the random read is input, and the selected data is used as the read address signal (SPMRA) 102 in the call memory 30.
Output to 0 and 302.

The write address signal 100 and the read address signal 102 output from the control memory unit 14 are stored in the call memory 300.
And 302. As shown in FIG. 8, in the nth frame, the input multiplexed signals (Di7 to Di0) are at the high level.
The SPM selection signal 104 is sequentially stored in the call memory 300 according to the write address signal 100. In the present embodiment, since the third mode is set, the input multiplexed signals A, B, C of the K-multiplexed time slots are stored in the call memory 300 in the order of sequential address (0, 1, 2). It is stored in the area.

In the call memory 302 to which the inverted signal 312 of the SPM selection signal 106 is input, the stored multiplexed signals are sequentially read according to the read address signal 102. In the present embodiment in which the third mode is set, the signals (A, B, C) of each time slot of the multiplexed signal (n-1 frame) stored in the order of address (0, 1, 2) are , Signals B, C, and A are read out in order according to the random address (1,2,0) and output to the output 306. This output 306 is the selection circuit to which the high level SPM memory selection signal 104 is input.
The multiplexed signal selected by 308 and read from the call memory 302 is output to the output 206 of the selection circuit 308. Thus, in the n frames of the input multiplexed signal, the speech memory 30
Sequential write at 0, call memory 30
At 2, random reading is performed on the multiplexed signal of the previous n-1 frame.

Next, at the timing when the input multiplexed signals (Di7 to Di0) of the (n + 1) th frame are input to the speech memory (SPM1) 302, the SPM memory selection signal (SPMSEL) 104 goes high / low.
Inverted signal 312 in which the low state is inverted and further inverted
Becomes high level, and the input multiplexed signals (Di7 to Di0) of the (n + 1) th frame are sequentially stored in the storage position of the call memory 302 indicated by the write address signal 100. Also, the speech memory 30 to which the low level SPM memory selection signal 104 is supplied.
At 0, the stored multiplexed signal of the nth frame is sequentially read in the order indicated by the read address signal (SPMRA) 102. As a result, the signal (A, B, C) of each time slot of the multiplexed signal of the nth frame stored in the order of address (0,1,2) is the signal B according to the random address (1,2,0). , C, A are read in this order and output to the output 304, which is output to the output 206 as an output multiplexed signal (Do7 to Do0).

In this way, the input multiplexed signal (Di7 to Di0) 200 of each frame is converted into the output multiplexed signal (Do7 to Do) whose time slots are exchanged in the next frame period T.
0) 206 is output from the output 206 of the time division type switch 10. Also for the operation after the n + 2 frame, the time slot exchange operation is performed in the same manner as above.

In the first mode in which random write and random read are set, the control memory units 18 and 20 are set.
The address signals (A1, A2) for each of the above are supplied from the higher-order control device 230 and stored in the respective storage areas, and the stored address data for the call memory unit 12 is the count value output from the respective counters 402, 502. It is possible to sequentially specify the write address and the read address of the input multiplexed signal for the call memory unit 12 by reading them sequentially.

Further, in the second mode in which the random write and the sequential read are set, address information for randomly writing the input multiplexed signal to the call memory is stored in the control memory, contrary to the above embodiment. . The input multiplexed signal is stored in the storage location of the call memory according to this address information. The multiplexed signal stored in the call memory is sequentially read and output according to the count value of the counter.

Further, in the fourth mode in which sequential write and sequential read are set, the counter is
The count values of 402 and 502 are the selection circuits 408 and
Selected in 504, the respective control memory units 18 and 2
It is supplied from 0 to the call memory unit 12. Also in this case, the input multiplexed signal is stored in the call memory by the write address signal and the read address signal according to different clock speeds of the write clock signal and the read clock signal,
The stored multiplexed signal is read out and output as an output multiplexed signal.

The embodiment described above can be applied to, for example, a device for inputting data for interfacing at a transmission rate of a synchronous digital hierarchy primary level (STM-1) and converting the data into an internal format of a digital exchange. You can

In this case, one frame of STM-1 is 125 (μ
sec) consists of 2430 (TS) and the clock is 19.4 (MHz). An example of the internal format of the digital exchange is that one frame is 125 (μsec), consists of 4096 (TS), and has a clock of 32.768 (MHz). Therefore, the frame cycle T in the above embodiment is 125 (μsec), the write clock signal (WCLK) is 19.440 (MHz), and the read clock signal (RCLK) is 3
2.768 (MHz), Multiplex number K is 2430 (TS), Multiplex number L is 4096 (T
As S), the transmission format can be converted into the exchange format. In this case, further, format conversion and time slot exchange can be performed at the same time.

As described above, the time division type switch 10 in the above embodiment stores the multiplexed signal at the address indicated by the write address signal that makes one round in the multiplexing cycle on the input side, and the multiplexed signal on the output side. A call memory unit that reads a multiplexed signal stored at an address indicated by a read address signal that makes one cycle in a cycle, and a control memory unit that generates a write address signal and a read address signal for accessing the call memory unit The control memory unit respectively generates these address signals according to the write clock signal and the read clock signal supplied from the higher-order control device. As a result, the multiplexed signal is stored in the call memory unit at a speed synchronized with the speed of the write clock, and the stored multiplexed signal is read from the call memory unit at a speed synchronized with the speed of the read clock. The time-division type switch 10 outputs a multiplexed signal with time slots interchanged, for example.

In this way, the address update speed is independent of writing and reading, and the write address of the call memory unit is updated at the speed of the input multiplexed signal and the read address is updated at the speed of the output multiplexed signal. . Further, these addresses can be designated by the host controller and stored in the control memory unit.

As a result, the clock speeds of the input multiplex signal and the output multiplex signal can be set independently, and further, the operation mode for performing random write and random read can be set. Therefore, the applicability of time division switch (TSW) is expanded.

Further, since the control memory is composed of the dual port RAM, the write address and the read address set in the control memory unit can be updated even while these addresses are being output. it can.

Further, since it is possible to unify the frame positions by absorbing the frame phase difference between the input highway and the output highway, it is not necessary to separately prepare an elastic store memory. Compared with the case where such a function is realized by using a conventional time switch (TSW) and an elastic store memory (ES), the embodiment shown in FIG. 1 has a small hardware scale. A plurality of time division type switches (TSW) can be compactly configured with a large scale integrated circuit (LSI).

In the embodiment, the TSSI (Time Slot Seq) is changed by the configuration of the double buffer type call memory unit (SPMB).
uence Integrity) is guaranteed. However, the present invention is not limited to this, and the call memory unit (SPMB) may be configured in a single buffer format when TSSI is not guaranteed by hardware.

[0070]

As described above, according to the present invention, the addresses of the call memory are designated in the order of the first address, and the bit string of each time slot of the first multiplexed signal is stored in the call memory. The write control means controls the addresses of the call memory, and the bit strings stored in the call memory are read by the read control means by designating the addresses of the call memory in the second address order. Therefore, either random write or sequential write can be performed to the call memory, and either random read or sequential read can be performed. Further, the call memory can be accessed independently for writing and reading. As a result, the bit string can be written in the call memory in the multiplexing cycle of the first multiplexed signal, and the bit string stored in the call memory can be read in the multiplexing cycle of the second multiplexed signal. Further, since random writing and random reading can be performed, the applicable range of the time divisional switch is widened.

Further, the first address signal and the second address signal can be simultaneously supplied to the call memory to specify the write side address and the read side address.

[Brief description of drawings]

FIG. 1 is a block diagram showing a time divisional switch according to the present invention.

FIG. 2 is a diagram showing inputs and outputs of the time divisional switch shown in FIG.

FIG. 3 is a block diagram showing an internal configuration of a call memory unit.

FIG. 4 is a diagram showing a write timing with respect to first and second control memory units.

FIG. 5 is a diagram showing read timings from the first and second control memory units.

FIG. 6 is a block diagram showing an internal configuration of a first control memory.

FIG. 7 is a block diagram showing an internal configuration of a second control memory.

FIG. 8 is a time chart showing the operation timing of the time divisional switch.

FIG. 9 is a time chart showing the operation timing of the time divisional switch.

[Explanation of symbols]

 10 Time division type switch 12 Call memory unit (SPMB) 14 Control memory unit (SCMB) 16 Timing unit (TIMB) 18 First control memory unit (SCMB0) 20 Second control memory unit (SCMB1)

Claims (10)

[Claims] 1. A time division type switch for outputting a second multiplexed signal by exchanging time slots of a first multiplexed signal input via a digital transmission line, wherein the switch comprises the first multiplexed signal. A call memory for storing a bit string of each time slot of the encoded signal, reading the stored bit sequence and outputting a second multiplexed signal, and address control means for designating an address of the call memory. The control means generates a first address signal for designating an address of the call memory in a random or sequential first address order, and a bit string stored in the call memory in a random and sequential write control means. Read control means for generating a second address signal for designating one of the second address order of the call, The memory stores the bit strings in the order of the first address specified by the first address signal, and stores the stored bit strings in the order of the second address specified by the second address signal. A time-division type switch characterized by reading and outputting in a multiplexing cycle of the multiplexed signal of. 2. The time division type switch according to claim 1, wherein the write control means generates a first address signal that makes a round in a multiplexing cycle of the first multiplexed signal, and performs the read operation. The control means generates a second address signal that makes one round in the multiplexing cycle of the second multiplexed signal, and the address control means causes the first and second address signals to have different first speeds. And a time division type switch which is generated based on a second clock and is supplied to the call memory. 3. The time divisional switch according to claim 2, wherein the write control unit counts a first address control memory that stores the first address signal and the first clock, Any of a first counting means for outputting the first count value as an address in the first address control memory or the call memory, an output of the first address control memory and an output of the first counting means A second address control memory for storing the second address signal, and a second clock for counting the second clock. Second counting means for outputting a count value of 2 as an address in the second address control memory or the call memory; output of the second address control memory and the second count Second selecting means for selecting and outputting any one of the outputs of the stage, the call memory stores the bit string in accordance with a first address signal output from the first selecting means, and stores the bit string. A time division type switch, characterized in that the selected bit string is read in accordance with a second address signal output from the second selecting means, and a second multiplexed signal of the bit string is output. 4. The time division type switch according to claim 3, wherein the first and second address control memories each have address information for designating addresses of the call memory in an arbitrary order and the address information. A first port for inputting an address for storing the address and an address for sequentially specifying the stored address information, and the address information corresponding to the address is input to the first and second addresses.
And a second port for outputting as an address signal of the memory, the time division type switch. 5. The time division type switch according to claim 3, wherein the first selecting means inputs a mode signal designating an operation mode of the switch, and the first selecting means receives the mode signal according to the mode signal. A time division type switch characterized by selecting either the output of the address control memory or the output of the first counting means. 6. The time division type switch according to claim 3, wherein the second selecting means inputs a mode signal designating an operation mode of the switch, and the second selecting means receives the mode signal according to the mode signal. A time division type switch characterized by selecting either the output of the address control memory or the output of the second counting means. 7. The time division type switch according to claim 1, wherein the write control means receives a mode signal designating an operation mode of the switch, and performs random write and sequential write in accordance with the mode signal. A time division type switch including a first selection circuit for selecting any one of the modes, and supplying a first address signal corresponding to the selected mode to the call memory. 8. The time division type switch according to claim 1, wherein the second control means receives a mode signal designating an operation mode of the switch, and according to the mode signal,
A time division type switch including a second selection circuit for selecting one of a random read mode and a sequential read mode, and supplying a second address signal corresponding to the selected mode to the communication memory. . 9. The time division type switch according to claim 1, wherein the call memory has a first port for inputting the first multiplexed signal and the first address signal, and the second address. A time division type switch comprising a memory having a second port for inputting a signal and outputting the second multiplexed signal. 10. The time division type switch according to claim 1, wherein the call memory has first and second storage means for storing the bit string, and the first and second storage means, A time-division type switch characterized in that the first multiplexed signal is alternately stored for each bit string of each multiplexing cycle, and the stored bit string is alternately read and output in the multiplexing cycle.