JP3013011B2 - Buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit in data communication, and more particularly to a buffer circuit having a data speed conversion function.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional buffer circuit. FIG. 3 shows an example of an input data string S1 including redundant bits such as a unique word and overhead data and a plurality of divided main data. This input data string S1
, Each main data is composed of n bytes. First, the data rate conversion function of the buffer circuit will be described. Referring to FIG. 2 and FIG. 3, the write address counter 4 operates with the input clock S2 and generates a write address signal S5 for the speed conversion buffer unit 1. At this time, the frame synchronization detection unit 2 establishes frame synchronization by detecting the unique word 21 included in the input data sequence S1. Thus, by using the frame synchronization signal S3 output from the frame synchronization detection unit 2, the blink control unit 3 writes the redundant bits included in the input data string S1 with the address blink signal S4 so as not to write the redundant bits into the speed conversion buffer unit 1. Address blink control is performed on the address counter 4. Therefore,
Only the input data sequence excluding the redundant bits is written into the speed conversion buffer unit 1 to separate the redundant bits and convert the data speed. In the clock speed conversion unit 6, an input clock S2 synchronized with the input data sequence S1 is input.
To generate an intermediate clock S6 by n / (n + 1). The read address counter 5 is operated by the intermediate clock S6, a read address signal S7 is generated, and a blink data string S8 synchronized with the intermediate clock S6 is generated.
Read out.

[0005] Next, the clock reading function of the buffer circuit will be described. The write address counter 8
It operates by the intermediate clock S6, generates a write address signal S9, and writes the blink data string S8 read from the speed conversion buffer unit 1 to the clock read buffer unit 7. An output clock S1 generated by the output clock generator 10 and having the same frequency as the intermediate clock S6.
1, the read address counter 9 is operated, a read address signal S10 is generated, and the output data string S1 is output.
2 is read from the clock rewriting buffer unit 7. Therefore, in the clock rewriting buffer section 7, writing and reading are performed by using the intermediate clock S6 and the output clock S11 having different phases, and the clock is rewritten.

[0004]

In the conventional buffer circuit described above, since the speed conversion buffer unit and the clock read-out buffer unit are separate, a RAM (Random Access Memory) is provided in each buffer unit.
Have the disadvantage that they must be kept separately.

It is an object of the present invention to provide a buffer circuit capable of simplifying the circuit and saving RAM.

[0006]

According to the present invention, frame synchronization is established by a buffer unit having both a data rate conversion function and a clock reading function, and a unique word included in an input data string input from an external device. A frame synchronization unit for outputting a frame synchronization signal, a write address counter which operates in response to an input clock input from an external device and generates a write address signal for the buffer unit, and an address spread control for the write address counter by the frame synchronization signal A clock control unit for generating an output clock;
A buffer circuit is provided, comprising: a read address counter that operates according to the output clock and generates a read address signal for the buffer unit.

[0007]

In the present invention, by using the data rate conversion function and the clock reading function in the buffer section, the data rate conversion buffer section read in the prior art is read based on the intermediate clock from the clock rate conversion section. However, sending out the address signal and sending out the write address signal to the clock rewriting buffer section based on the intermediate clock from the clock speed conversion section can be omitted, the circuit can be simplified, and the RAM associated with the buffer section can be saved. it can.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a buffer circuit according to the present invention. FIG. 3 shows an input data string S1 including redundant bits such as a unique word and overhead data.
It is a figure showing an example of. As shown in FIG.
A write address counter 4, a buffer section 11, a frame synchronization detection section 2, a flash control section 3, an output clock generation section 10, and a read address counter 9 are provided. The buffer unit 11 has a data rate conversion function and a clock reading function.

The write address counter 4 operates according to the input clock S2 and generates a write address signal S5 for the buffer unit 11. At this time, the frame synchronization is established by detecting the unique word 21 included in the input data string S1 as shown in FIG. Thus, the blink control unit 3 uses the frame synchronization signal S3 output from the frame detection unit 2 to control the write address counter 4 by using the address blink signal S4 so as not to write the redundant bits of the input data string S1 into the buffer unit 11. , Address blink control is performed. Therefore, only the input data string excluding the redundant bits is written in the buffer unit 11, and the redundant bits are separated and the data speed is converted.

The read address counter 9 has a frequency of n / (n + 1) of the input clock S2, is operated by the output clock S11 generated by the output clock generator 10, generates a read address signal S10, and The output data sequence S12 thus read is read from the buffer unit 11. Therefore, only the input data string excluding the redundant bits is written into the buffer unit 11, and the separation of the redundant bits,
Data speed conversion is performed, and the input clock S2 and the output clock are read.

[0012]

As described above, in the present invention, the provision of the buffer unit having both the speed conversion function and the clock reading function enables the circuit to be simplified and the R
This has the effect of saving AM.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a buffer circuit of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a conventional buffer circuit.

FIG. 3 is a diagram illustrating an example of an input data sequence.

[Explanation of symbols]

 Reference Signs List 1 speed conversion buffer unit 2 frame synchronization detection unit 3 blink control unit 4 write address counter 5 read address counter 6 clock speed conversion unit 7 clock read buffer unit 8 write address counter 9 read address counter 10 output clock generation unit 11 buffer unit S1 input data string S2 input clock S3 frame synchronization signal S4 address blink control signal S5 write address signal S6 intermediate clock S7 read address signal S8 blink data string S9 write address signal S10 read address signal S11 output clock S12 output data string

Claims (1)

(57) [Claims] A buffer unit having both a data rate conversion function and a clock reading function; and a frame synchronization unit for establishing frame synchronization by a unique word included in an input data sequence input from an external device and outputting a frame synchronization signal. A write address counter that operates by an input clock input from an external device and generates a write address signal for the buffer unit; a flash control unit that performs address flash control on the write address counter by the frame synchronization signal; A buffer circuit, comprising: an output clock generating unit that generates the data; and a read address counter that operates by the output clock and generates a read address signal of the buffer unit.