JPH03237523A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To easily transfer stored data to a new device by most suitably setting the constitution of a cylinder address signal and a head address signal of the new device to an optimum condition while matching a conventionally used system. CONSTITUTION:When a write mode set signal 9 is inputted from a high-order device to a memory control circuit 1, the circuit 1 holds a data signal 6 by an address set signal 7 and outputs it as a write address signal 11 and holds the data signal 6 by a data set signal 8 to output it as a write data signal 14; and when a write indication signal 10 is inputted, the circuit 1outputs a memory write signal 15. A memory control circuit 2 outputs a cylinder address signal 4 and a head address signal 5 as a memory address signal 13 in the normal using state and sends the write address signal as the memory address signal 13 to a memory circuit 3 only at the time of input of a write mode signal 12 from the memory control circuit 1. The memory circuit 3 outputs a corresponding physical cylinder address signal 16 and a corresponding physical head address signal 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device that is widely used as a device for storing data in information processing devices.

[Conventional technology]

Some conventional magnetic disk drives record data for online databases, but the technology of magnetic disk drives has progressed at a remarkable pace, and with the advancement of technology, new devices are being developed frequently. Therefore, how to transfer accumulated data to a new device is a major problem for computer system users.

Moreover, the specifications of the system and equipment that the user is currently using are different from those of the new system and equipment, so
Migration of data to a new device often does not proceed smoothly.

[Problem to be solved by the invention]

The problem to be solved by the present invention, in other words, the purpose of the present invention is to eliminate the drawbacks of conventional magnetic disk devices as described above, and to migrate data from the system and device currently in use to a new device. By configuring the cylinder address signal and head address signal configuration of the new device to suit the system and device previously used before normal use, it is possible to easily transfer accumulated data to the new device. An object of the present invention is to provide a magnetic disk device that can be transferred to other devices.

[Means to solve the problem]

In the magnetic disk device of the present invention, when a write mode setting signal is input, a data signal sent from a host device is held as an address set signal as a write address signal, and a data signal held as a data set signal is used as a write data signal. a memory control circuit that sends the write address signal and write mode signal to a memory address signal generation circuit, and instructs the memory circuit to write the write data signal in response to a write instruction signal input from the host device; In normal use, a cylinder address signal and a head address signal sent from the host device to designate a track on which a write or read operation is to be performed are sent to the memory circuit as memory address signals, and the write mode signal is sent to the memory circuit. a memory address signal generation circuit that switches the memory address signal to a write address signal only when input from a control circuit; a physical cylinder address signal selected in accordance with the memory address signal based on data written in advance by the host device; and the memory circuit that outputs a physical head address signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a memory control circuit 1 holds a data signal 6 as an address set signal 7 and outputs it as a write address signal 11 when a write mode setting signal 9 is input from a host device at system startup. , the data signal 6 is held as the data set signal 8 and the write data signal 1 is
4, and outputs a memory write signal 15 when the write instruction signal 1o is input.

Memory address signal generation circuit 2 generates write mode signal 1
When the write mode signal 2 is inactive, the cylinder address signal 4 and the head address signal 5 input from the host device are sent to the memory circuit 3 as the memory address signal 13, and when the write mode signal 12 is active, the cylinder address signal 4 and the head address signal 5 input from the memory control circuit 1 are sent to the memory circuit 3. The write address signal 11 is sent to the memory circuit 3 as a memory address signal 13.

The memory circuit 3 inputs the write address signal 11 as the memory address signal 13 when the memory control circuit 1 activates the write mode signal 12, and inputs the write data signal 14 as data when the write instruction signal 10 is input. write to the specified address. Furthermore, when the write mode signal 12 is inactive, the memory circuit 3 inputs the cylinder address signal 4 and head address signal 5 from the host device as the memory address signal 13, and receives the physical cylinder address signal stored at that address. 16 and a physical head address signal 17 are output to designate a track on which a write or read operation will actually be performed.

FIG. 2 is a circuit diagram showing details of the memory address signal generation circuit of the embodiment of FIG. 1.

In FIG. 2, the memory address signal generation circuit 2 includes 9
It is configured with a set of AND gates 21 and 22 and an OR gate 23, and either the AND gate 21 or the AND gate 22 is opened depending on the state of the write mode signal 12, and the cylinder address signal 4 and the head address signal 5 are opened. or write address signal 1
1 is outputted through the OR gate 23. That is, when the write mode signal 12 inputted from the memory control circuit 1 is inactive, the output of the inverter 24 to which the write mode signal 12 is connected becomes active, and the AND gate 21 is opened to output the cylinder address signal 4 and the head address. Signal 5 is AND gate 2
1 and further passes through an OR gate 23 and is output as a memory address signal 13. Also, write mode signal 1
When 2 becomes active, AND gate 22
is opened, address signal 11 and memory address signal 13
is output as

FIG. 3 is a circuit diagram showing details of the memory control circuit of the embodiment of FIG. 1.

In FIG. 3, a register circuit 31 and a register circuit N
Reference numeral 32 is a circuit consisting of nine sets of flip-flops, which holds 9-bit data through a common lock terminal. The data signal 6 input from the host device is connected to nine input terminals of the register circuit 31, and the address set signal 7 is connected to a common lock terminal. When address set signal 7 is input, data signal 6 is held as write address signal 11. Similarly, the data signal 6 is connected to each of the nine input terminals of the register circuit 32, and the data set signal 8 is connected to a common lock terminal. Data set signal 8
When , data signal 6 is written and data signal 14 is input.
hold as. The write mode setting signal 9 is output as is as a write mode signal 12. The write instruction signal 10 is connected to an AND gate 33 and is ANDed with the write mode setting signal 9, and becomes valid only when the write mode setting signal 9 is active and is output as a memory write signal 15. Instructs circuit 3 to write data.

FIG. 4 is an explanatory diagram showing an example of a physical cylinder address signal and a physical head address signal output in response to input of a cylinder address signal and a head address signal in the memory circuit of the embodiment shown in FIG.

In this embodiment, the cylinder address and head address sent from the host device are 6 bits and 3 bits, respectively. Here, the simplest conversion is performed to convert the lower 1 bit of the cylinder address to the higher 1 bit of the physical head address. Therefore, the head address is 0 to 7, but the physical head address is 0 to 15.
Until now.

〔Effect of the invention〕

As explained above, the magnetic disk device of the present invention freely transmits data for converting cylinder address signals and head address signals sent from a host device into physical cylinder address signals and physical head address signals of a new device. By selecting the most suitable conversion data for one type of new equipment according to the previously used system and equipment and setting it before normal use, the cylinder address signal of the new equipment can be changed. This also has the effect of optimizing the structure of the head address signal and realizing a magnetic disk device that can effectively utilize previously used data in a new system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the memory address signal generation circuit of the embodiment of FIG. 1, and FIG. 3 is a memory diagram of the embodiment of FIG. 1. FIG. 4 is an explanatory diagram showing an example of the physical cylinder address signal and physical head address signal output in response to input of the cylinder address signal and head address signal in the memory circuit of the embodiment shown in FIG. 1. It is. In the figure, 1... Memory control circuit, 2...
...Memory address signal generation circuit, 3...
...Memory circuit, 21.2 3...AND get 3...OR get, 24...Inverter, 2... register circuit.

Claims (1)

[Claims] When the write mode setting signal is input, the data signal sent from the host device is held as an address set signal and is used as the write address signal.The data signal held as the data set signal is used as the write data signal.The write address signal and the write mode a memory control circuit that sends a signal to a memory address signal generation circuit and instructs the memory circuit to write the write data signal in response to a write instruction signal input from the host device; A cylinder address signal and a head address signal sent from the device to designate a track on which a write or read operation is to be performed are sent to the memory circuit as memory address signals, and only when the write mode signal is input from the memory control circuit. A memory address signal generation circuit that switches a memory address signal to a write address signal, and outputs a physical cylinder address signal and a physical head address signal selected in accordance with the memory address signal based on data written in advance by the host device. A magnetic disk device comprising: the memory circuit described above.