JPS62239476A - Sequence control circuit - Google Patents

Abstract

PURPOSE:To change programmably a sequence and to cope with every format by making a sequence generating circuit into a RAM. CONSTITUTION:When a sequence ROM is made into a sequence RAM and to a sequence generating RAM circuit 33' constituted so as to be programmed from an external part, an optional format is inputted, the following action comes to be the same action as the conventional action except the generation of the pattern of an optionally set format. Thus, the sequence can cope with the optional format of respective types of the recording device programmably and without the wide hardware change, the format change can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is adapted to various formats of floppy disk devices, hard disk devices, and optical disk devices.

The present invention relates to a sequence control circuit used to control write and read sequences.

(Configuration of conventional example and its problems) FIG. 3 shows a conventional sequence control circuit. The configuration of this conventional example will be explained below using FIG. 3.

In FIG. 3, 1 to 22 are signal lines, 30 is a sector buffer for storing data in units of sectors, and this sector buffer 30 is controlled by a sequence latch 34.

A mark generation circuit 35 generates marks necessary for access, synchronization, clocking, etc. This mark generation circuit 35 is also controlled by the sequence latch 34. below,
Modulation circuit 36. The demodulation circuit 37 and PLL circuit 38 are also controlled by the sequence latch 34.

Reference numeral 31 denotes a basic timing generation circuit for generating a sequence using an asynchronous signal from a drive 39 as a basic timing for sequence control (in units of pie 1).

32 is a sequence address generation circuit for generating a sequence, and this sequence address generation circuit 32 is controlled by the basic timing generation circuit 31.

33 is a sequence generation ROM circuit, and this sequence generation ROM circuit 33 is accessed by the basic timing generation circuit 31 and the sequence address generation circuit 32 to generate a predetermined format pattern.

The sequence latch 34 is connected to the sequence generation ROM circuit 3.
This is a circuit that holds 3 for a predetermined period of time.

Next, the operation of the above conventional example will be explained.

In FIG. 3, when data input to the sector buffer 30 is completed, the control start signal on the signal line 2 causes J! This timing generation circuit 31 is activated and enters a standby state for receiving the iD detection pulse (signal line 4) from the drive 39.

FIG. 4 is a diagram showing the timing for format 1 in FIG.

Due to the iD detection pulse from the drive 39, gate signals are sent to the sector buffer 30, mark generation circuit 35. Modulation circuit 36, demodulation circuit 37, I)
L L circuit: 38. The data is generated to the drive 39 to generate a predetermined format pattern.

However, in the conventional example described above, the sequence is generated in the ROM', and there is a drawback that it can only support fixed button formats 1 through 1.

(Object of the Invention) The present invention is intended to eliminate the drawbacks of the above-mentioned conventional example, and aims to make it possible to change the sequence in a programmable manner.

(Structure of the Invention) In order to achieve the above object, the present invention provides sequence RO
M is a sequence RAM and has a structure that can be programmed from the outside, so that it can be changed programmably and can be adapted to any format.

(Example) The configuration of an example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment showing the configuration of a sequence control circuit according to the present invention.

In FIG. 1, 40 is a sequence generation RAM circuit 33.
This is a multiplexer for the address when writing an arbitrary sequence to '.

The sequence generation RAM circuit 33' is a circuit that generates an arbitrarily set format. The rest of the structure is the same as that of the conventional example explained in FIG. 3, so the explanation will be omitted.

Next, the operation of the above embodiment will be explained.

In FIG. 1, an arbitrary format is input to the sequence generation RAM circuit 33'.

The following operations are similar to those of the conventional example except that a pattern of an arbitrary set format is generated.

This embodiment has the advantage that it can be programmably adapted to any format of various recording devices, and that the format can be changed without major hardware changes.

FIG. 2 is a diagram showing timing for the format in FIG.

(Effects of the Invention) The present invention has the above-described configuration, and since the sequence generation circuit is implemented as a RAM, it is possible to obtain the effect of being compatible with all formats 1-.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment showing the configuration of a sequence control circuit according to the present invention, FIG. 2 is a diagram showing timing for the format in FIG. 1, FIG. 3 is a diagram showing a conventional sequence control circuit, and FIG. FIG. 4 is a diagram showing the timing for the format of FIG. 30... Sector buffer, 31... Basic timing generation circuit, 32... Sequence address generation circuit, :3:3...
- Sequence generation ROM circuit, 33'...Sequence generation RAM circuit, 34...Sequence latch, 35...Mark generation circuit, 36...Modulation circuit, 37
... Demodulation circuit, 38... PLL circuit. 39... Drive, 4o... Multiplexer. Figure 2 Figure 4

Claims (1)

[Scope of Claims] A sequence address generation circuit that generates addresses for sequence control, a sequence generation RAM that can programmably set various arbitrary formats, and a control signal for each control element using the output of the sequence generation RAM. A basic timing generation circuit that synchronizes drives (optical disks, hard disks, floppy disks) that operate asynchronously,
A sequence control circuit comprising: