JPH0251714A - System clock generator - Google Patents

Abstract

PURPOSE:To minimize the number of parts and the circuit area despite a large number of zones and to reduce the cost of a system clock generator by using a register, a D/A converter and a voltage/frequency converter and setting the frequency data on a system clock via a CPU. CONSTITUTION:A CPU 1 outputs the system clock frequency data to a data bus A in response to a zone where the information is recorded and reproduced and at the same time outputs a write signal B. Then a system 2 stores the system clock frequency data on the bus A via the signal B and outputs the system clock frequency C. A D/A converter 3 outputs the system clock frequency voltage D decided by the data C. A voltage/frequency converter 4 outputs a system clock S.C. having a frequency decided by the voltage D. Then the CPU 1 sets the system clock frequency data to produce the system clock for the zone where the information is recorded and reproduced. In such a way, the number of parts and the circuit area can be minimized despite a large number of zones.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a system clock generator of an information recording/reproducing device using an information recording medium.

[Conventional technology]

An information recording and reproducing device having an information recording and reproducing method (hereinafter referred to as modified LV) that divides a track on the recording surface of an information recording medium into at least two or more zones and writes data in each zone and changes the frequency. In this case, for example, as shown in FIG. 2, if the modified-CLV format medium 5 has eight zones E-L, the information recording/reproducing clock frequency is changed for each zone and the entire information recording medium is The bit recording density is uniformized to a limited extent.

Conventionally, as shown in FIG. 3, the system clock, which is this type of information recording/reproduction clock, has oscillators 6 to 13 corresponding to zones E-L in FIG. The register 2 stores the selection information of the oscillators 6 to 13 of the data bus A by the write signal B, and is reselected by the oscillator selection signal M-T output by the register 2. The oscillator was in an oscillating state and was generating system clocks S and C for the zone in which information was to be recorded and reproduced.

[Problem to be solved by the invention]

The above-described system clock generator requires as many oscillators as there are zones on the information recording medium, so it requires a large number of parts and a large circuit area, which has the drawback of increasing cost.

[Means to solve the problem]

The system clock generator of the present invention is:

A central processing unit, a register that stores system clock frequency data set by the central processing unit, and a digital/analog converter that converts the system clock frequency data stored in the register and set by the central processing unit into an analog voltage. , and a voltage/frequency converter whose output clock frequency is controlled by the voltage output from the digital/analog converter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is the central processing unit, 2 is the register, 3 is the digital/analog converter, 4 is the voltage/frequency converter, A
is the data bus, C is the system clock frequency data, D
is the system clock frequency voltage, and S, C, is the system clock.

The operation of this embodiment will be explained below.1 For example, assuming that the modified-CLV format medium 5 has eight zones E-L as shown in FIG. In this case, it is necessary to change the frequency of the system clock, which is the information recording/reproducing clock, for each of these eight zones.To do this, as shown in Figure 2, the central processing unit 1 has to change the frequency of the system clock, which is the information recording/reproducing clock, for each of these eight zones. system clock frequency data to be output to data bus A, and write signal B is output. Register 2 stores system clock frequency data of data bus A in response to write signal B, and outputs system clock frequency data C. digital/
Analog converter 3 outputs a system clock frequency voltage determined by system clock frequency data C. The voltage/frequency converter 4 outputs system clocks S, C, with frequencies determined by the system clock frequency voltage.

By setting the system clock frequency data by the central processing unit in this manner, it is possible to generate the system clock for the zone in which information is to be recorded and reproduced.

〔Effect of the invention〕

As explained above, in the present invention, by setting the frequency data of the system clock by the central processing unit, it is possible to generate a maximum of types of system clocks that can be expressed on the data bus using the same circuit. Even in this zone, the number of parts and circuit area are minimized, resulting in low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a general information recording medium, and FIG. 3 is a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Register, 3...Digital/analog converter, 4...Voltage/frequency converter, 5...Modified-CLV format medium, 6-13...Oscillator , A...Data bus, B...Write signal, C...System clock frequency data, D...System clock frequency voltage, E-L...Zone, S, C,...System clock .

Claims (1)

[Claims] A central processing unit, a register that stores system clock frequency data set by the central processing unit, and a digital/analog converter that converts the system clock frequency data stored in the register and set by the central processing unit into an analog voltage. , and a voltage/frequency converter whose output clock frequency is controlled by the voltage output from the digital/analog converter.