JPS59207419A - Absorbing device for fluctuation of time axis - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to attain the miniaturization and small power consumption of an absorbing device for fluctuation of time axis, by securing the synchronism between the read and write of a memory and therefore absorbing the jitter with just a single memory. CONSTITUTION:The OFF section of the output CC of a counter 44 is set at 1/2fCA second by a read clock signal RC of a frequency of 2A times as much as the frequency fC of a reproduction clock signal PC. The read timing is produced with a one-shot clock having approximately the same cycle as the signal PC. While the output NC obtained from an NAND gate 60 produces the one-shot clock with the 2A-fold read clock RC after securing the synchronism for the signal PC with the fall of an A-fold clock signal and produces the write timing. Therefore no overlap is produced between the write timing and read timing. Thus plural memories are not needed since the synchronism is secured between the read and the write of a memory. This attains the miniaturization and small power consumption of an absorbing device for fluctuation of time axis.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for absorbing time axis fluctuations, and more particularly to an apparatus for absorbing time axis fluctuations in an Okel reproducing circuit for a multi-track day-to-day data recording apparatus.

Conventionally, as this type of time axis fluctuation absorbing device, one shown in FIG. 1 has been proposed.

In the figure, reference numeral 10 denotes a reproducing circuit which converts reproduced data reproduced by a magnetic head or the like into a digital signal. 12 is P
The LL reproduction clock circuit generates a reproduction clock signal synchronized with reproduction data supplied from the reproduction circuit 10. Reference numeral 14 denotes a demodulation circuit, which demodulates the digital data modulated based on the reproduction data of the reproduction circuit 10 and the reproduction clock signal from the PT and L reproduction click 2, and also detects a frame synchronization signal. These digital signals 101 and frame synchronization signals 102 are output. , 16 is a write address counter, and PL
The regenerated clock signal of the L regenerated clock circuit 2 is supplied, and write addresses of the time axis fluctuation absorbing memories 18, 20 and 22 are specified. Numerals 24, 26 and 28 are multiplexers which designate the read/write state of each memory 18, 20 and 22 and switch the address designation. 30 is a read address counter, which generates a read address according to the time 4iHt+read clock signal 103 with no fluctuation;
A frame address counter 2 generates a read frame address, which is supplied to each multiplexer 24, 26, and 28 via a multiplexer 34. 3
Reference numeral 6 denotes an output line connected to the output side of each memo IJ18, 20 and 22, and transmits data output with time axis fluctuations absorbed.

Next, the operation will be explained. Each multiplexer 2 is
4 to 28 are activated, and each memory 18 to 22 is set to a loading or reading state.

As shown in FIG. 2, the Nth data N of the output signal J] from the demodulation circuit 14 and the demodulation data N shown in FIG. By the frame synchronization signal 102 of the third time, data is written to the memory 18 which is set to the write state as shown in FIG.
It is set to the read state as shown in FIG.

Next, by the N+1st frame synchronization key 102, the memory 20 is set to the write state as shown in FIG.
Write the first data N-1-1 and write the first data N-1-1 to the memory 18.
22 is set to the read state.

Furthermore, by the N+2 frame synchronization (g 102), the memory 22 is set to the write state as shown in FIG.
+2nd data N+2 is written, memory i8, zo
id is set to the read state, and thereafter the above three states are repeated every time the frame synchronization signal 102 is obtained.

Note that the timing of switching from the reading state to the writing state of each memory depends on the amount of knocking and memory capacity of the data recording device, so it may be necessary to change the timing when switching from the reading state to the writing state for each memory, so it may be necessary to change the timing when switching from the reading state to the writing state. .

Then, to the memory set to the write state.

To write data, the write address counter 16 is driven by the F T,L recovered clock signal, and l frames of data are written into the memory according to the write address generated thereby.

Next, the memory set to the write state is set to the read state for two frames by the next frame synchronization signal. To read from the memory in this state, the read address counter 34 is fully driven by a read clock signal 103 with no time axis fluctuations obtained by a crystal oscillator or the like so as to absorb time axis fluctuations, and the read address generated by this drives the read address counter 34. When the writing is completed and there is a delay of A reproduced data string shown in FIG. 2(e) is obtained.

In other words, by using three memories in parallel, %
It constitutes a time axis fluctuation absorbing device with a knock margin of up to one frame. In FIG. 2, the hatched areas indicate the write state, the dotted areas indicate the read state, and the blank areas indicate the read set state.

However, since the conventional time axis fluctuation absorbing device is configured as described above, it requires three or more memories per dock, and accordingly the number of multiplexer circuits increases, making it difficult for multi-track recording equipment. The disadvantage of this method was that the circuit size became large.

The present invention has been devised in view of the above-mentioned conventional problems with VC, and its purpose is to reduce the number of required 11 tracks by making it possible to absorb knocks with one memory, and in particular to reduce the number of required 11 tracks. It is an object of the present invention to provide a time axis fluctuation absorbing device that can reduce the circuit scale of the recording device 19-.

In order to achieve the above object, the present invention provides a time axis fluctuation absorbing device for recording and reproducing a digital data string and absorbing time axis fluctuations of the reproduced data, in which a reproduced clock 218 generated from the reproduced data is used. A write address counter of the memory is driven by a signal, and a read address counter of the memory is driven by a read clock signal of 2A (A is a positive integer) times the reproduction clock signal without time axis fluctuation. and a control circuit that controls the write state of the memory in synchronization with the read address counter, and writes write data asynchronous to read data into the memory at intervals between read timings. It is characterized by

Hereinafter, preferred embodiments of the present invention will be described based on figures and fI.

FIG. 3 is a block diagram showing one embodiment of the present invention.

The reproduction circuit 10, the PLL reproduction clock circuit 12, and the demodulation circuit 14 have the same configuration as in FIG.

38 is a bit address counter, PLT, .

The reproduced clock signal pc is supplied from the reproduced clock circuit 12, and the frame signal j0 from the demodulator circuit 14 is supplied.
A signal FS is supplied, and a write address signal for a memory 46, which will be described later, is supplied to a multiplexer 40. 42 is a read address counter, which is the output of a 3AN counter 44 that counts a read clock signal RC that is 2A (A is an integer greater than or equal to 3) times the reproduced clock signal pc and is supplied from a crystal oscillator or the like with no time axis fluctuation. is supplied, and based on this, a read address signal is supplied to the multiplexer 40.

The multiplexer 40 is switched and controlled by the output CC of the counter 44.

46 is a memory, demodulated data D from the demodulation circuit 14
D is supplied, the output of the multiplexer 40 is supplied, and the counter 4 is also supplied to the back input terminal of the input/readout j.
4 output CC is supplied, and the enable terminal is supplied with ! from a control circuit 52, which will be described later. The Iji control signal CS is supplied, and the readout output thereof is sent to the output line 50 as a reproduced data string with time axis fluctuations absorbed through a latch circuit 48 which is latched at the timing of the output CC of the counter 44.

52 control circuits, including a T-type flip-flop 54 to which the read clock signal RC is supplied, and its output TC.
is supplied to the T input terminal, and the reproduced clock signal pc is supplied to the D input terminal.
A D-type flip-flop 58 to which C is supplied to the T input terminal, a Nant gate 6o to which its negative output D2 and a positive output D1 of the above-mentioned flip-flop 56 are supplied, its output NC, and the output CC of the counter 44. is supplied h
- Consists of 7nd r-1-62, and 6nd dart
The output of 2 is supplied to the enable terminal of the memory 46 as a control signal cs.

Note that the counter 44 is a write/read switch f of the memory 46.
lii control and the multiplexer 40
A controller that performs long-term control of switching the IJ address counter output and read address counter output to the memory 46).
Play the role of a roller.

Next, the operation will be explained with reference to the timing chart of FIG.

The demodulated data DD shown in FIG. 4(a) is output from the demodulated θ('Q circuit 14, and the recovered clock signal pc shown in FIG. 4(b) is outputted from the PLL recovered clock circuit 12.These demodulated data DD and the reproduced clock signal PC are synchronized, but they are asynchronous with the read clock signal RC shown in FIG. For ease of explanation, the explanation will now be made assuming that the periods of the reproduced clock signals p and c are slightly shorter than the period of the read clock signal RC.

Since the read clock signal RC is supplied to the T-type flip-flop 54 of the mass control circuit 52, from its output side, the frequency of half of the read clock signal RC as shown in FIG. 4(d), that is, the reproduced clock signal pc. An output TC with a frequency A times (3 times in the figure) the frequency is output. Therefore, an output DI as shown in FIG. 4(e) is obtained from the D-type flip-flop 7'56 based on the reproduced clock signal PC and the output TC.

In response, the NAND circuit 60 outputs an output DI and a read clock RC based on the output D1 of the D-type flip-flop 56 and the negative output obtained from the D-type flip-flop 58 based on the output D1 and the read clock signal RC. It turns off at the rising edge of the read clock signal RC.
An output NC is obtained which continues for a pulse width interval of , and is supplied to the AND gate 62.

On the other hand, the AND gate 62 has a counter 44 shown in FIG.
) is supplied, and therefore a control signal C8 as shown in FIG. 4(h) is obtained from the AND gate 62, and this is supplied to the enable terminal of the memory 46.

Therefore, as shown in FIG. 4(1), the memory 46 is accessed to read out the period 7f4 in which the output CC of the counter 44 is off, and the period in which the output of the counter 44 is on,
and the control (i'j number C) supplied to the enable terminal
It is accessed in the write state in the S or OFF section, and is not accessed in other sections.

The read data read from the memory 46 in the read state is latched by the latch circuit 64 at the timing of the output CC of the counter 44, so that the data is sent from the latch circuit 64 to the output line 66 as shown in FIG. 4(j). It absorbs time axis fluctuations, aligns it, and outputs it as a data string.

In this case, the output CC of the counter 44 is a one-shot signal having approximately the same period as the reproduced clock signal pc, whose off interval is ZfeA (seconds) due to the read clock signal RC having a frequency 2A times the reproduced clock coefficient PC frequency fc. With the clock
It forms the reading evening and timing, while Nandgut 6
The output NC obtained from 0 is obtained by synchronizing the reproduction signal PC with the falling edge of the A-times clock signal, and then generating a one-shot clock using the 2A-times read clock signal RC to form the write timing. Therefore, if the write timing and read timing overlap, it is impossible.

Note that in the above embodiment, the present invention is merely an example of the present invention, and is not limited to the upper side. The write data, which is asynchronous with the read timing, is synchronized with the read address counter in the gap between the read timings. All you have to do is take it and put it in by 1.

As described above, according to the present invention, since reading and writing of the memory are configured to be performed in synchronization, it is possible to absorb the sock υ with a 1m memory, unlike the conventional example where multiple Because it does not require a single memory, the circuit scale can be reduced, and it has an excellent effect of promoting miniaturization, lower power consumption, and lower cost of devices, especially for multi-track type data. It is possible to provide a time axis variation absorbing device suitable for application to a recording device.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a timing chart for explaining its operation, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 shows signal waveforms of each part. It is a timing chart figure shown. In each figure, the same reference numerals are given to the same 11 materials, 10 is a regeneration circuit, 12 fd: PLL regeneration clock circuit,
14 is a demodulation circuit, 38 is a write address counter, 40 is a multiplexer, 42 is a read address counter, 44-digit counter, 46 is a memory, 48 is a latch circuit, and 50 is an output line. Agent: Patent attorney Masuo Oiwa (and 2 others) Figure 1

Claims (1)

[Claims] (1) In a time axis fluctuation absorbing device that records and reproduces a digital data string and absorbs time axis fluctuations in the reproduced data, an address counter written into the memory is activated by a reproduced clock signal generated from the n raw data. drive the read address counter of the memory with a read clock signal that is twice as large as the reproduced clock 4< (A is an integer of 3 or more) and has no time axis fluctuation; 2. A control circuit for controlling a write state of the memory in synchronization with the read data, the write data being asynchronous with the read data being written into the memory at a gap between the read timings. Axis fluctuation absorption device.