JPS63119068A - Time base converter for digital data - Google Patents

Abstract

PURPOSE:To send a digital data at an optional transmission rate without causing a missing of even one byte by storing the input digital data in a memory and reading it out of the memory at a prescribed transmission rate. CONSTITUTION:The input digital data is written in the memory and read out of the memory at a prescribed period to convert the input digital data at an optional transmission rate into a digital data at a prescribed transmission rate for the purpose of output. That is, the input digital data is written in memories 21, 22 and read out of the memories 21, 22 at a prescribed period to convert the input digital data at an optional transmission rate into the digital data at a prescribed transmission rate for the purpose of output. Thus, the digital data at an optional transmission rate is sent through a transmission system whose transmission rate is fixed without causing missing of even one byte. Thus, the digital data at an optional transmission rate is recorded and reproduced by connecting a digital data recorder to the system externally without revamping the data recorder itself.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital data time axis conversion device that converts input digital data at an arbitrary transmission rate into digital data at a predetermined transmission rate and outputs the converted data. It is commonly used as a data input means in a data transmission system such as a synchronous digital tape recorder with a fixed data transmission rate.

[Summary of the invention]

In a data transmission system with a fixed transmission rate, such as a synchronous digital tape recorder, the present invention stores input digital data in a memory and reads it from the memory at a predetermined transmission rate. This allows data to be reliably transmitted via the data transmission system.

[Conventional technology]

2. Description of the Related Art Conventionally, digital data recorders employing a helical scan method, for example, have been used to record and reproduce digital data.

In general, helical scan type digital data recorders record and reproduce digital data at a constant rotational speed of a rotating magnetic head for recording and reproducing data, and at a constant data transmission rate according to a predetermined recording format. ing. In a synchronous data recorder with a constant data transmission rate, even if the input digital data transmission rate is lower than the recording/playback system transmission rate, the transmission rate is divisible by a synchronized integer. For example, the transmission rate of the recording/reproducing system must be 60 Mbps (bit/5
30Mbp for a 6G) data recorder
When supplying and recording input digital data of s,
By assigning 1 bit of input digital data to a recording area corresponding to 2 bits on the data recorder, problems such as data loss occur because there is a clear relationship between the input digital data and the data on the recording area. Never. However, if the transmission rate of the input digital data is 35 Mbps, for example, 60/35-q
1, 7, and the correspondence between data bits on the recording area becomes unclear, making it meaningless as a digital data recording, and normal reproduction cannot be performed.

[Problem that the invention seeks to solve]

By the way, as mentioned above, in a data transmission system with a fixed transmission rate such as a synchronous digital tape recorder, even if the transmission rate of input digital data is smaller than the transmission rate of the transmission system, the transmission rate is If the data is not divisible by a synchronized integer, normal data transmission will not be possible, and digital data at any transmission rate cannot be handled.

Therefore, in view of the above-mentioned problems, the present invention aims to record and reproduce digital data at an arbitrary transmission rate without modifying the digital data recorder itself. An object of the present invention is to provide a time axis conversion device for digital data having a novel configuration that allows digital data at any transmission rate to be transmitted in a data transmission system without missing a single byte.

[Means for solving problems]

In order to solve the above-mentioned problems, the digital data time axis conversion device according to the present invention includes first and second memories each capable of MII4 data of one frame at the maximum transmission rate of input digital data; A value corresponding to the amount of data in approximately one frame period of the input digital data is set, and a counter is provided to count the clocks of the input digital data, and a synchronization pulse is output as a count output by the counter, and a synchronization pulse is output by the counter. a write control section that selectively controls the write operation of the input digital data to the first and second memories by counting output; It is characterized by comprising a read control section that selectively performs an operation of reading data at a predetermined cycle.

[Effect]

The digital data time axis conversion device according to the present invention converts input digital data at an arbitrary transmission rate into digital data at a predetermined transmission rate by writing the input digital data into a memory and reading it from the memory at a predetermined period. and output it.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital data time axis conversion device according to the present invention will be described in detail below with reference to the drawings.

The embodiment shown in the block diagram of FIG. 1 has an effective recording rate of 60 Mbp, which is synchronized with a 30 MH2 synchronizing signal.
s (250,000 bytes/7 frames) when connected externally to a maximum transmission rate of 60 M
This implements a time axis conversion device that enables recording and reproduction of input digital data at any transmission rate up to bps, and includes two bank memories 21 and 22- each having a storage capacity of 250,000 bytes; A write control unit 10 that controls the write operation of input digital data to each of the bank memories 21 and 22, and a read control unit 30 that controls the read operation of input digital data to each of the bank memories 21 and 22. There is.

Each of the bank memories 21 and 22 has a multiplexer 15
．． 25 to the write control section 10 and read control section 30, and when one side is connected to the write control section 10, the other side is connected to the read control section 30.
It is designed to be connected to.

The write control unit 10 is configured to be supplied with input digital data (Byte) and its data clock (DCLK) from a data source (not shown), and is connected to a counter 11 that counts the clock (DCLK) and the input digital data. It is composed of a programmable divider 12 and the like for setting a value corresponding to the amount of digital data (byte) in approximately one frame period. A dividing rate switch 14 is externally connected to the programmable divider 12 . Then, the counter 11
The dividing rate switch 14 applies the ratio of the data clock frequency of the input digital data (Byte) to the reference synchronization frequency of the digital data recorder side to the programmable divider 12 as a dividing rate, so that the digital A value corresponding to the amount of input digital data (Bytes) in approximately one frame period at the transmission rate on the data recorder side is set. Above counter 1
1 generates digital data (not shown) based on the data clock (DCLK) by repeatedly counting the data clock (DCLK) supplied from a data source (not shown) up to the value set by the dividing rate switch 14. Forms a synchronizing signal (SYNC) for running control of the recorder, and also inputs the digital data [Byte] to each bank memory 21 and 22.
form write address data.

The read control unit 30 also controls each of the bank memories 21 selectively connected by the multiplexer 25.
．． 22 data of 250,000 bytes each within one frame period to a data recorder (not shown).As shown in FIG. 2, a 66 MHz clock (
CLK), and a gate signal (CLK) that counts the clock (CLK) and indicates a data period.
A counter 32 that forms a readout address data and a P/S conversion that converts byte-by-byte parallel data read from a storage location specified by the address data formed by the counter 32 into bit serial data. It is composed of a container 33 and the like.

In the embodiment configured as described above, the write control unit 10 receives data from a data source (not shown) at a transmission rate of 56 Mbps (7 Mbps) as shown in FIG.
e/s e c) input digital data (Byte)
is supplied, and a data clock (DCLK) with a repetition frequency (7MHz) corresponding to that 1 byte is supplied.
When l is supplied, the dividing rate of the reference synchronization frequency 7 x 10'#233333 is set to the dividing rate switch 14, and the dividing rate of the counter 1
1, the data clock (DCLK) is actually repeatedly counted up to the value of the dividing rate plus 1 to form a synchronization signal (SYNC) having a SYNC frequency of 7 x 10" = 29.999914 MHz. .Then, in each of the bank memories 21 and 22,
During one frame period, 233,334 bytes of input digital data (Bytes) are alternately written from address O to address 233,334 every frame. Each of the bank memories 21 and 22 into which the input digital data [BYTE] is written is read by the read control unit 30 every frame period, starting from the one to which data is not written by the write control unit 10. 249 from the address
250000 bytes of data up to address 999 (D
ATA) are all read out and sent via the P/'S converter 33 to a data recorder (not shown), where they are recorded.

In addition, during playback operation, the read control section 30 is used as a write control section, and the write control section 10 is used as a read control section, so that 250,000 bytes of playback data is transferred to each bank memory for each frame period by the data recorder. Write to 1J21.22 and 23333 from address O
Read the contents up to address 3.

As in this example, input digital data [Byte]
A synchronizing signal (SYNC) is formed by dividing the frequency of the data clock (DCLK) by the counter 11.
By controlling the running of the digital data recorder using this synchronization signal (SYNC), 233
Fixed recording and reproduction of 334 bytes can be performed reliably.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the digital data time axis conversion device according to the present invention writes input digital data to a memory and reads it from the memory at a predetermined period, thereby converting input digital data at an arbitrary transmission rate. Since the data is transmitted at a specified rate and converted to a single digital data before being output, digital data at any transmission rate can be transmitted without missing a single byte. Therefore, by externally connecting the digital data time axis converting device according to the present invention to a digital data recorder, the data recorder itself can be It becomes possible to record and reproduce digital data at any transmission rate without modification, and according to the present invention, the intended purpose can be fully achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart of data recorder control signals output from the device of the above embodiment, and FIG. 5 is a timing chart of data source signals supplied to the device. 10...Write control unit 11.32...Counter 12...Programmable divider 14...
...Dividing rate switch 15.25...Multiplexer 21.22...Bank memory

Claims (1)

[Claims] First and second memories each capable of storing one frame of data at the maximum transmission rate of input digital data, and a value corresponding to the amount of data in approximately one frame period of the input digital data. a counter for counting the clocks of the input digital data; the counter outputs a synchronizing pulse as a count output; and the input digital data is written to the first and second memories by the count output of the counter. a write control unit that selectively controls operations; and a read control unit that selectively performs an operation of reading data written in a memory that is not in a write state among the first and second memories at a predetermined cycle. A digital data time axis conversion device that converts input digital data at an arbitrary transmission rate into digital data at a predetermined transmission rate and outputs the digital data.