JPH0237639B2 - - Google Patents

Abstract

PURPOSE:To read out a series of data at a high speed by providing a control memory which produces an address for sound record/reproduction to be stored in a voice data memory and an address selecting ciircuit. CONSTITUTION:In a reproduction mode a microprocessor muP sets a head address A corresponding to a message, end address B and a working address C on a control memory CM. When no coincidence is obtained between address C and B compared by a comparator COM, i.e., the message is under transmission, the working address data is replaced by +1 to prepre for the next reading. Thus the output of an adder ADD is used as the input of the memory CM. While the output of a register 2 holding the address A is used as the input of the memory CM when the coincidence is obtained between addresses C and B, i.e., the message is completely transmitted.

Description

[Detailed description of the invention] (1) Technical field of the invention The present invention digitizes audio data and stores it in a memory.
The present invention relates to a voice data recording and reproducing method for a device that records messages on an IC and reads out multiple messages from the memory IC in a time-sharing manner.

(2) Background of the technology Conventionally, the common method for recording and reproducing audio data and supplying it to an external device was to record audio on magnetic tape in an analog manner and then reproduce it.

However, in recent years, mechanical parts such as rotating bodies have become obsolete due to maintenance concerns, and recording and playback devices convert audio data into digital signals such as PCM, store it in an IC, and then read the data from a memory IC for playback. This is becoming a method of supplying it externally.

(3) Prior art and problems Figure 1 shows an example of the configuration of a conventional circuit. In this example, all addresses for the memory holding audio data in digital format (hereinafter referred to as audio memory) are given by the microprocessor μp. As is well known, if audio data is sampled at a sampling rate of 8kHz, the quality when played back is guaranteed. Therefore, when recording audio with this device, a write pulse is given to the audio memory from the microprocessor at a rate of 8 kHz, or once every 125 μs, and at the same time, the writing address is updated, and at that time the analog-digital The digital audio data output from the converter A/D will be written into the audio memory.

Next is the reproduction method, in which data is read from the audio memory and sent to an external device in accordance with the read address given by the microprocessor μp. An external device converts this audio data into a digital-to-analog converter (not shown).
It is possible to play back the original analog audio by inputting it to . Of course, no write pulse is applied when reading data from the audio memory.

As for the readout speed during playback explained above, this can also be done at a rate of 8kHz, but if the readout address is updated every 125μs, only one message can be played back. This 125μs is required to play and send multiple messages.
It is only necessary to divide the message into several parts, read out the data of each message from the voice memory in a time-division manner, and supply it to the external device. However, the area occupied by each message on the audio memory is managed by the microprocessor μp, and in order to play back the message endlessly, when the read address is updated, the message may extend beyond the message area. In some cases, simply add +1 to the address to play from the beginning of the message.
Instead, it is necessary to perform processing for each message such as setting the address to the first address that the message occupies in the audio memory. Ta.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a memory for a device for recording and reproducing audio data in digital format so as to speed up the transmission of time-division messages to the outside.
The purpose is to provide an audio data recording and playback method that can control IC addresses.

(5) Structure of the Invention According to the present invention, the object is to digitize audio data, record it in a memory IC, read out a plurality of messages from the memory IC in a time-sharing manner, and supply the audio data to the outside. By providing an audio data processing method that is equipped with a control memory that generates an address for recording and playing back to memory and an address selection circuit, and is characterized by controlling reading and writing of a series of audio data at high speed. will be achieved.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an example of the circuit configuration of the audio data recording and reproducing system according to the present invention, FIG. 3 shows an example of address allocation of the control memory CM shown in FIG. 2, and FIG. 4 shows an address allocation time chart of FIG. 3.

To explain from an example of playback, first, A, B, and C on the control memory CM are provided corresponding to messages, where A is the first address occupied by the message on the audio memory, B is the last address, and C is the working address. and are set in the control memory CM by the microprocessor μp at the timing f in the time chart. Note that this setting from the microprocessor .mu.p need only be done once for each message in response to recording, and nothing is done thereafter at the timing f corresponding to that message.

In FIG. 4, a; Data is read from the working address and sent to the audio memory and held in register 1 b; Data from the last address is read and held in register 2 c; The contents of register 1 and register 2 are compared and the result held d; Start address Data is held in the read register 2 e; Selector output is written to the working address of the control memory f; Indicates the time period in which data is set from the microprocessor to the control memory.

The operation shown in FIG. 2 will be explained below along with the time chart shown in FIG. 4.

At timing a of the message to be reproduced, the address generator ADRG outputs the control memory CM.
The address of C corresponding to the message is generated, and the audio data is read from the audio memory in accordance with the data outputted from the control memory CM as working address data, and after being held in the buffer BUF, is sent to an external device. Note that at timings b to f, some data is output from the control memory CM, and audio data is read from the audio memory VM accordingly, but no holding signal is sent to the buffer BUF at this timing. The working address data read from the control memory CM is also sent to register 1REG1 and held there.

Next, at timing b, the address generator ADRG
generates the B address, and the last address occupied on the voice memory VM of the message read from the control memory CM is registered in register 2.
is maintained.

Next, at timing c, the above two registers
The contents of REG1 and REG2 are compared and the result is held in the comparator COM. and timing d
Then, the first address occupied on the voice memory VM of the message read from the control memory CM in accordance with the address A output by the address generator ADRG is held in the register 2.

Finally, at timing e, the output of selector SEL is written to address C of control memory CM. This address C is the address generator
Needless to say, it is the output of ADRG. Now, this selector SEL, its input is an adder
These are the outputs of ADD and register 2REG2, and the output switching control is the output of comparator COM. That is, if the working address compared at timing c does not match the last address, that is, if the message is in the middle, the working address data is updated by +1 in preparation for the next read, so the adder ADD output is sent to the control memory CM. If the comparison at timing c matches, that is, if the message has been sent to the end, the message will be played back from the beginning, so the output of register 2REG2, which holds the beginning address, is stored in the control memory. It works as input for CM.

Then, at the next timing a, address A of the control memory corresponding to message 1 is output in order to read data corresponding to message 1 from the voice memory as shown in FIG.
In this way, the address generator ADRG sequentially reads out the address of the voice memory where each message is stored from the control memory.

As described above, each message can be read out endlessly in time division.

In the case of recording, the microprocessor writes the smallest recordable address in the audio memory to addresses A and C of the control memory CM, that is, the addresses where the start address and working address data are to be stored. Of course, timing is f in the time chart. As address B, that is, the last address, the largest address in the empty area of the audio memory is set.

After that, it is the same as during playback, but at timing a, a write pulse is sent to the audio memory VM,
Audio data that has passed through the A/D converter A/D and has become a digital format is written to the audio memory VM.

Finally, the working address data at the end of recording is set as the last address in the control memory.
Just set it to CM address B and you're done.

(7) Effects of the Invention As explained in detail above, according to the audio data recording and playback method of the present invention, the processing speed is controlled by the access time of the control memory CM, and the memory access time is
Since there are ICs on the order of nanoseconds, this method is much faster and more effective than the microprocessor's cycle time of several microseconds.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional audio data recording/playback system, FIG. 2 is a block diagram of an audio data recording/playback system according to the present invention, FIG. 3 is an example of address assignment of the control memory shown in FIG. The figure is a control memory address allocation time chart. In the drawing, VM is audio memory, μP is microprocessor, A/D is A-D converter, CM is control memory, SEL is selector, ADD is adder, REG1 and 2 are registers, and COM is comparator. , ADRG is address generator, BUF is buffer,
TIM each indicates a timing circuit.

Claims (1)

[Scope of Claims] 1. A memory IC that stores digitized audio data in predetermined areas for each of a plurality of messages, and a read address, a final address, and a first address of each area in which each message of the memory IC is stored. For each area, following the control memory address where the read address of one area is stored, the address where the final address and start address of this area are stored is output. an address generation means for sequentially executing the read address of the control memory; a comparison means for comparing the read address of the one area read from the control memory with the final address; and an increment means for incrementing the read address; The audio data recording and reproducing method is characterized in that when the comparison result of the comparing means does not match, the contents are rewritten to the output of the advancing means, and when they match, the content is rewritten to the start address.