JPH0568033B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a time axis correction circuit for reproducing digital signals using a multihead from a digital recording medium such as an audio tape deck in which bit positions are recorded at the same position on a plurality of tracks. .

[Prior Art] In fixed head type digital audio tape decks, etc., the tape running speed relative to the head is slow, so a multi-head playback system is used to increase the code transmission speed with high-density recording. In multi-track recording, the starting point of the track is aligned in the width direction of the tape from the reference edge of the tape, and recording is made at fixed positions. but,
When this recording tape is run and played back by a multi-head, the playback signals detected from each track do not match in time due to errors in assembly and installation of each head, twisting during tape running, etc., resulting in a so-called skew. Therefore, when the skew is significant, code errors may occur if the reproduced signals of each track are processed using the same bit clock. Therefore, it is necessary to align the time axes of each reproduced signal by some means. Skew depends on each individual machine, and it is difficult to completely adjust it by mechanical adjustment alone, and ultimately it must be adjusted by electrical means.

Generally, memory is used to correct errors in the time axis of digital signals. Even in the fixed multihead system, the signals of each track are usually written into a common large memory, and the reading times are made the same when reading them out. On the other hand, in the fixed head system, the signals of each channel are divided into a plurality of tracks and recorded (interleaved), so the divided data are aligned when read out according to the format after being written into the memory. The above method has the disadvantage that when the number of tracks and channels is large, the memory control circuit becomes extremely complex.

[Problem that the invention seeks to solve]

The purpose of the present invention is to use a buffer with a memory function when inputting each track signal to the memory, instead of the conventional method of storing all data in a common memory and then burdening the memory control circuit. By performing time axis correction with and inputting the memory input address to the memory to be deinterleaved according to the format
An object of the present invention is to provide a skew killer circuit with a simple circuit configuration that serves both time axis correction and deinterleaving.

[Means for solving problems]

In the present invention, a data storage section is provided for each track, and a common track control section sends the data in the data storage section to the common bus in a time-division manner using the synchronization signal of one specific track as a time reference. ,
The control section identifies from which track data is currently being sent to the common bus, and creates an address according to the format, thereby writing the deinterleaved data into the memory.

That is, each data storage section extracts a synchronization signal from the playback signal of each track, writes it together with the playback signal as data to a buffer that functions as a memory, and when there is a read signal, it gives priority to writing and transfers it to the common bus. The data is sent from the buffer.

The track control section inputs a synchronization signal from one specific track, supplies timing pulses generated in a time-division manner in synchronization with this synchronization signal to each track as a readout signal, and sends them out to the common bus. Controls writing of each track's data to memory. The track control section inputs a synchronization signal from the synchronization signal line of the common bus, identifies the track being read, and generates a deinterleave write address to the memory.

〔Example〕

FIG. 1 is a circuit block diagram of one embodiment of the present invention. Data storage sections 10 and 20 are provided for each number of tracks. Here, the synchronization signal a of the data storage section 10 is sent to the track control section with the first track as a specific track. The data storage section 20 represents the other tracks as the i-th track. Since the circuit configurations of the data storage units 10 and 20 are the same, the data storage unit 10 will be explained. The reproduced signal of the track is converted into a parallel signal by the serial/parallel conversion circuit 11, and a buffer 1 with a memo function is created.
2 are stored. At this time, the synchronization detection/synchronization protection circuit 13 extracts the synchronization signal and stores it in the buffer 12 as data together with the reproduced signal.
In this example, 7 bits of 8-bit data are used as a reproduction signal. The synchronization signal a is sent to the timing generator 14
The data is written into the buffer 12 by inputting the read/write signal 14a as a write signal. The write address is determined by the address generator 16.

The track control section 30 consists of a timing generator 31 and an address generator 32.
The timing generator 31 inputs the synchronization signal a of the data storage unit 10, which is a specific track, and generates time-divided signals b ₁ , b ₂ , . . . b _i , . . .
b to generate _o . These signals are sent to the first track, . . . the nth track, respectively. The timing generator 31 also has a common data bus 4.
A signal from one line 401 of 0 is input. A line 401 is one bit of the data bus 40, and a synchronization signal is transmitted from each data storage section 10, 20 in a time-division manner.

Signals b ₁ to _{b o} are input to priority determination circuits 15 and 25 of each data storage section 10 and 20. When this signal is input, the timing generators 14 and 24 preferentially read the read/write signals 14a and 24a, and the data at the address determined by the address generators 16 and 26 is sent from the buffers 12 and 22 to the data bus 40. . Since the signals b _{1 -bo} are generated in time division at a fixed time in synchronization with the synchronization signal a of a specific track, the reproduced signals of each track are carried on the data bus 40 in a time division manner.

Since a synchronization signal is input to the timing generator 31 from the synchronization signal line 401 in the data bus 40, the track control unit 30 receives a signal indicating which track is currently on the data bus 40.
It can be distinguished by contrasting with b ₁ to b _o . The address generator 32 is then driven by the identification information and generates a write address for the RAM 50 taking deinterleaving into consideration. Each track reproduction signal on data bus 40 is recorded in RAM 50 according to its address.

〔Effect of the invention〕

As described in detail above, the track reproduction signals of the multihead are once stored in a buffer for each track and sent out on the data bus in a time-division manner. This transmission timing is preferentially determined by a timing pulse created in a time-division manner from a synchronization signal extracted from a signal of one specific track. Therefore, skew can be completely corrected. It is also easy to write to addresses that are deinterleaved from a common path in RAM. As described above, according to the present invention, it is possible to perform skew correction and deinterleaving simultaneously with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention. 10, 20...Data storage unit, 30...Track control unit, 40...Data bus, 50...RAM, 12,
22... Buffer, 13, 23... Synchronization detection/synchronization protection circuit, 14, 24, 31... Timing generator, 16, 26, 32... Address generator, 15, 25... Priority determination circuit, 401... Synchronization signal line.

Claims (1)

[Scope of Claims] 1. In a multi-head reproduction method from a digital recording medium recorded on a plurality of tracks, a synchronization signal is extracted from the reproduction signal of each track,
a data storage unit provided for each track that writes data together with a playback signal to a buffer having a memory function, and sends the data from the buffer to a common bus with priority over writing when there is a read signal; A synchronization signal from one specific track is input, a timing pulse generated in a time-division manner in synchronization with the synchronization signal is supplied to each track as a readout signal, and the data of each track is sent to a common bus. and a track control unit that controls writing to the memory, and the track control unit inputs a synchronization signal from a synchronization signal line of a common bus to identify the track being read, and controls the write to the memory. A skew killer circuit characterized by generating interleaved write addresses.