JP3252426B2 - Digital sound recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio recording / reproducing apparatus which records digital waveform data obtained by sampling an audio signal in an external storage device such as a hard disk and reads out the waveform data to reproduce an audio signal.

[0002]

2. Description of the Related Art Conventionally, digital recording in which an analog waveform input from the outside is sampled and sequentially converted into PCM data by A / D conversion, and the PCM data is simultaneously recorded with the conversion and written to an external storage such as a hard disk in real time. There is a device. In addition, there is a digital reproducing apparatus that sequentially reads out the PCM data from an external storage that stores the PCM data, converts the read PCM data into an analog waveform, and reproduces the analog waveform. Further, there is an apparatus in which such a recording apparatus and a reproducing apparatus are configured as a single hardware so that recording or reproduction can be performed by switching functions.

[0003]

By the way, this type of device is often used for editing and creating music and the like.
In a recording operation, for example, recording another part in accordance with a previously recorded music part, recording is often performed while playing back previously recorded sound. However, in the above-described conventional apparatus, if it is intended to record simultaneously input waveforms while reproducing already recorded PCM data, it is necessary to prepare reproduction and recording apparatuses completely independently.

The present invention provides a digital audio recording / reproducing apparatus in which the reproduction and the recording can be performed by one apparatus at a time, and the configuration of the entire apparatus is simple by sharing a bus for transferring waveform data. The task is to provide.

[0005]

According to the present invention, there is provided a digital audio recording / reproducing apparatus for sampling an audio signal and converting the audio signal into waveform data. A buffer memory for temporarily storing waveform data, an interface circuit for inputting and outputting the waveform data to and from an external storage device, a waveform data storage circuit for storing a predetermined amount of waveform data, A reproducing means for reading out the waveform data from the waveform data storage circuit to reproduce an acoustic signal; a bidirectional bus connected to each of the sampling means, buffer memory, interface circuit and waveform data storage circuit; second from the first transfer to an external storage device to the storage device to the waveform data storage circuit And transfer control means for controlling the transfer door,
Timing control means for performing time-division control of the bidirectional bus at a period shorter than the sampling period of the sampling means, and for the time slot of the bidirectional bus in the time-division control, a time slot corresponding to the sampling period. The other time slots used for the write operation to the buffer memory are stored in the first
Characterized by the transfer and it has to be used in the second transfer preparative alternates timing.

[0006]

In the digital sound recording / reproducing apparatus of the present invention, during recording, the sampling means samples the sound signal and converts it into waveform data, which is written to a buffer memory via a bidirectional bus and temporarily stored. Is done. Further, the waveform data stored in the buffer memory, transfer (feeding first rolling) to an external storage device via the bi-directional bus and the interface circuit by the transfer control means
And stored in an external storage device.

On the other hand, at the time of reproduction, the waveform data stored in the external storage device is via the interface circuit and the bi-directional bus transfers to the waveform data storage circuit (second transfer) by the transfer control unit, the waveform data Stored in the storage circuit. Further, the waveform data stored in the waveform data storage circuit is read by the reproducing means, and the acoustic signal is reproduced.

Here, the timing control means performs time-division control of the bidirectional bus at a cycle shorter than the sampling cycle of the sampling means. Also, the time slots of bi-directional bus in the time-division control, the time slots corresponding to the sampling period used in the write operation to the buffer memory, sending the other time slot the first rolling <br/> the first for use in the timing of alternating two of the transfer door. The timing at which the reproducing means reads the waveform data from the waveform data storage circuit substantially corresponds to the timing at the time of recording.

Therefore, even with a single bidirectional bus, the first data is written while temporarily writing the waveform data to the buffer memory and reading the waveform data from the waveform data storage circuit.
And a second eg DMA transfer can be performed simultaneously.

[0010]

FIG. 1 is a diagram showing the configuration of an audio recording / reproducing system using a digital audio recording / reproducing apparatus according to an embodiment of the present invention.

The digital audio recording / reproducing apparatus 1 is connected to two hard disks A and B, a microphone 2 for stereo input with two channels, a sound system 3 for stereo output, and a personal computer 4. Command commands such as recording and playback are input,
In the digital sound storage / playback apparatus 1, recording and playback functions are selected.

At the time of recording, the acoustic signal input from the microphone 2 is converted into waveform data and recorded on the hard disk A or the hard disk B. At the time of reproduction, the waveform data is read from the hard disk A or the hard disk B, converted into an analog sound signal, and the sound is reproduced by the sound system 3.

FIG. 2 is a block diagram of the digital audio recording / reproducing apparatus 1 of the embodiment. The A / D conversion circuit 11 samples the left and right two-channel stereo sound signals input from the microphone 2 via the analog input circuit 12 at a sampling frequency of 50 kHz (sampling cycle is 20 μsec), and each of the 16-bit waveform data. Convert to

In this embodiment, the sampling period of 20 μsec of the A / D conversion circuit 11 is divided into 128 time slots, and the timing of the time division operation is controlled according to the slot numbers “0” to “127” of each time slot. Is done.

The clock generation circuit 13 generates a 6.4 MHz system clock φ _SYS (1
A clock width of about 160 nsec is output to each block, and each block operates in synchronization with the system clock φ _SYS .

The clock generation circuit 13 generates a clock signal corresponding to the slot numbers “0”, “2”, “64”, “66”, that is, 20 μm in the A / D conversion circuit 11.
During the sampling period of sec, a data output clock φ _C which becomes four clock signals is generated, and this data output clock φ _C is transmitted through a gate circuit 15 which is opened at the time of recording by a control signal from the control unit 14. The data is supplied to the A / D conversion circuit 11 and the write counter 16.

Further, clock generation circuit 13 generates an even-numbered clock corresponding to the even-numbered slot number and a coded clock φ _REC corresponding to the odd-numbered slot number, respectively.
The play clock φ _PLAY is obtained by the logical product of the data output clock φ _{C and} the inverted signal of the circuit 18 by the circuit 18, and is input to the matrix circuit 19 together with the coded clock φ _REC .

That is, the recorded clock φ _REC corresponds to all odd slot numbers, but the play clock φ _PLAY has slot numbers “0”, “2”, “64”,
The clock signal corresponds to an even slot number other than “66”.

The matrix circuit 19 changes input terminals x and y to output terminals A and B in response to a switching signal from the control unit 14.
The play clock φ _{PLAY is set} to D
MA control clock phi _A and Reko state of outputting a de clock phi _REC as a DMA transfer clock φ _B (x → A,
y → B) and a state (y → A, x → B) in which the coded clock φ _REC is output as the DMA control clock φ _A and the play clock φ _PLAY is output as the DMA transfer clock φ _B.

The A / D conversion circuit 11 divides each sampled 16-bit waveform data of the left and right two channels into upper 8 bits and lower 8 bits of data in synchronization with the data output clock φ _C, and performs one sampling period. 4 bytes of data are sequentially output to the buffer RAM 20 via the 8-bit data bus 100 within 20 μsec.

The write counter 16 sequentially outputs write addresses in the buffer RAM 20 in synchronization with the data output clock φ _C and supplies the write addresses to the buffer RAM 20 via the address bus 200. 1-byte data output from 11 is sequentially written to the buffer RAM 20. The write counter 16 controls the start and stop of the operation by a start / stop signal from the control unit 14 and also sends a FULL signal to the control unit 14 in accordance with a write address of the buffer RAM 20 as described later. Output.

FIG. 4 is a diagram showing a memory map of the buffer RAM 20.
This is a 256-kbyte memory divided into an A buffer and a B buffer for each byte. The operation of writing data from the A / D conversion circuit 11 and the operation of writing and reading during DMA transfer are controlled alternately for the A buffer and the B buffer, and the write counter 16 determines when the writing to the A buffer is completed. And output a FULL signal at the end of writing to the B buffer.

The waveform data is, for example, the upper 8 bits (S1L) of the left channel of the first sampling data.
H), lower 8 of the left channel of the first sampling data
Bit (S1LL), upper 8 bits (S1RH) of the right channel of the first sampling data, lower 8 bits (S1RL) of the right channel of the first sampling data,...
, One byte is written in order from address 0.

The hard disk A is connected to the SCSi interface circuit 21A, the hard disk B is connected to the SCSi interface circuit 21B, and the hard disk A is connected to the SCSi interface circuits 21A and 21B.
MA controllers 22A and 22B are connected respectively.

Each SCSi interface circuit 21A,
21B controls data transfer between the microcomputers in the hard disks A and B, respectively.
The DMA controllers 22A and 22B latch the upper 8 bits of each of the hard disks A and B, the buffer RAM 20, and the waveform data via the respective SCSi interface circuits 21A and 21B and the 8-bit data bus 100.
Latch 23 and L latch 2 for latching lower 8 bits
4 are respectively controlled.

Here, the DMA controllers 22A and 22A
B has a PLAY signal or RE signal from the control unit 14 respectively.
The C signal is input to each of the DMA controllers 22A and 22A.
B outputs the read address of the buffer RAM 20 to the address bus 200 based on the DMA control clocks φ _A and φ _B when the REC signal is input, and outputs the data read from the buffer RAM 20 via the 8-bit data bus 100. Is DMA-transferred to the corresponding hard disks A and B.

On the other hand, when the PLAY signal is input, the data read from the corresponding hard disks A and B based on the DMA control clocks φ _A and φ _B are DMA-transferred to the 8-bit data bus 100 and transmitted to the address bus 200. A write address is output, and the data on the 8-bit data bus 100 is stored in the H latch 2 as described later.
3 and the DMA in the waveform RAM 25 through the L latch 24.
It is recorded at the timing of transfer.

FIG. 3 is a timing chart showing the relationship between each clock signal and the time slot of the 8-bit data bus 100.
0 upper left 8 bit data (L
chH), lower 8-bit data of the left channel (Lch
L), upper 8-bit data of the right channel (RchH)
And lower 8-bit data of the right channel (RchL)
Are output to the 8-bit data bus 100 in the time slots of slot numbers “0”, “2”, “64”, and “66”, respectively, in synchronization with the data output clock φ _C.

The DMA controller 22A (or 22B) to which the PLAY signal is input from the control unit 14
From the hard disk A (or B) by the control of
The transferred reproduction data (P) is transmitted by a DMA control clock φ.
Play clock φ used as _A (or φ _B )
_In synchronization with _PLAY , slot numbers “0”, “2”, “6”
The data is output to the 8-bit data bus 100 in even time slots other than 4 "and" 66 ".

Further, the DMA controller 22A (or 22B) to which the REC signal is input from the control unit 14
Control from the buffer RAM 20 to the hard disk A
(Or B), the recorded data (R) transferred by DMA is
Synchronized with the record clock φ _REC used as the DMA control clock φ _A (or φ _B ), they are output to the 8-bit data bus 100 in odd time slots, respectively.

Therefore, each operation of writing data to the buffer RAM 20, DMA transfer from the buffer RAM 20 to the hard disk A (or B) and DMA transfer from the hard disk A (or B) is performed by one 8
The bit data bus 100 can be shared and performed substantially simultaneously.

Next, a description will be given of an operation of fetching data to be DMA-transferred from the hard disk A (or B). The data on the 8-bit data bus 100 is supplied as input data to an H latch 23 for latching the upper 8 bits of the waveform data and an L latch 24 for latching the lower 8 bits of the waveform data.

The lower one bit signal of the address bus 200 is supplied to the L latch 24 as a latch signal, and an inverted lower one bit signal is supplied to the H latch 23 via an inverter 26 as a latch signal.

The signal of the upper remaining bits of the address bus 200 is supplied as an address signal to an Ad latch 27 for latching a write address of the waveform RAM 25, and the Ad latch 27 supplies a clock corresponding to an even slot number. The signal is provided as a latch signal.

Further, 8 of the H latch 23 and the L latch 24
The bit output line is connected to the waveform RAM 25 as a 16-bit data bus 300, and the 16-bit data bus 300 is a data bus from the waveform RAM 25 to the PCM tone generator. The output address line of the Ad latch 27 and the output address line of the PCM tone generator 29 are
Is connected to the write / read address bus 400.

On the other hand, the lower one bit signal of the address bus 200 is also supplied to a write timing generating circuit 30, and the write timing generating circuit 30 outputs the signal at the timing of the next time slot after the L latch 24 has latched the data. A latch output clock φ _W is output, and this latch output clock φ _W is supplied to the H latch 23, the L latch 24, and the Ad latch 2
7 are supplied as output timing signals.

Further, the latch output clock φ _W from the write timing generation circuit 30 is also supplied to the write pulse generation circuit 31, and the write pulse generation circuit 31 synchronizes with the latch output clock φ _W to the waveform RAM 25. Generate a write pulse.

FIG. 5 is a diagram showing a memory map of the waveform RAM 25. The waveform RAM 25 is a memory divided into A blocks and B blocks of 64 k words each, and writes DMA transfer data from the hard disks A and B. And the operation of reading the waveform data by the PCM tone generator 29 are controlled alternately for each of the A block and the B block. The PCM tone generator 29 outputs a NEXT signal to the control unit 14 when the reading of the waveform data from the A block is completed and when the reading of the waveform data from the B block is completed.

The DMA transfer data is transferred as 8-bit data.
And L-latch 24 to form 16-bit waveform data. The waveform data is, for example, left-channel waveform data (S1L) of first sampling data, right-channel waveform data (S1R) of first sampling data, and second sampling data. Waveform data (S
2L), the right channel waveform data of the second sampling data (S2R),..., Are written one word at a time in order from address 0.

FIG. 6 is a timing chart showing the operation of writing waveform data to the waveform RAM 25. Since this writing operation is performed at the time of reproduction, data transferred by DMA from the hard disk A (or B) appears on the 8-bit data bus 100 in, for example, an even number of time slots as shown in the figure.

At this time, the DMA controller 22A
(Or 22B), the lower 1 bit of the address bus 200 changes alternately like “0” / “1”,
The lower 1 bit is set to “0” in synchronization with the upper 8 bit data (LH, RH) of the left and right 2 channels,
It becomes "1" in synchronization with the lower 8-bit data (LL, RL) of the channel.

Therefore, the upper 8 bits of the waveform data are latched and held in the H latch 23 to which the inverted signal of the lower 1 bit is input as a latch signal.
The lower 8 bits of the waveform data are latched and held in the L latch 24 to which the lower bits are directly input as a latch signal.

The write timing generation circuit 30 outputs H
Since the latch output clock φ _W inputted to the latch 23 and the L latch 24 becomes the next time slot after the L latch 24 latches the lower 8 bits, that is, every other odd time slot, this latch output clock φ _W In synchronization with the odd time slots, the left channel waveform data (LH, LL) and the right channel waveform data (R
H, RL) are output to the 16-bit data bus 300, respectively.

On the other hand, since the address signal input to the Ad latch 27 is an address signal of the remaining bits excluding the lower 1 bit, the Ad latch 27 stores the time slot of each data of the upper and lower 8 bits of the left channel. , An even address (2n, etc.) is latched, and an odd address (2n + 1, etc.) is latched in the time slot of each data of the upper and lower 8 bits of the right channel. These addresses correspond to the latch output clock φ, respectively.
It is output to the write / read address bus 400 of the waveform RAM 25 in synchronization with _W.

Then, in synchronization with the write pulse output from the write pulse generating circuit 31, waveform data (LH, LH) of the left channel of the 16-bit data bus 300 according to the write address of the write / read address bus 400.
L) and the right channel waveform data (RH, RL) are alternately written to the waveform RAM 50.

On the other hand, a start / stop signal is input from the control unit 14 to the PCM tone generator 29. Under the control of the control unit 14, the PCM tone generator 29 reads out waveform data from the waveform RAM 25 at a timing corresponding to the playback pitch during playback. Output to the D / A conversion circuit 32. Then, the D / A conversion circuit 32 outputs the waveform data as a stereo two-channel sound signal from the analog output circuit 33 to the sound system 3 for sound reproduction.

The PCM tone generator 29 performs a read operation with a clock signal corresponding to an even slot number. For example, as shown by a broken line in FIG.
Since the waveform data (L) read from M25 is output to the 16-bit data bus 300 in an even number of time slots, it is possible to perform the write operation and the read operation of the waveform data in the waveform RAM 25 during the DMA transfer substantially simultaneously. it can.

FIG. 7 shows the write and read operations to the buffer RAM 20 and the waveform RAM in the recording operation and the reproduction operation.
FIG. 9 is a diagram showing an example of an operation of writing and reading waveform data to and from 25, where the time of an address of each RAM elapses.

Here, the recording operation and the reproducing operation will be described with reference to FIG. The control circuit 14 performs an operation in accordance with a command from the personal computer 4, as shown in FIG. (A), when performing the recording operation, for example, a write counter 16 and the data output clock phi _C A / It outputs the start signal to the D counter 11 and the write counter 1
6 to divide the waveform data into 8-bit data and start writing data to the buffer RAM 20.

When the writing to the A buffer of the buffer RAM 20 is completed, the write counter 16 sets the FULL
The controller 14 receives this FULL signal, outputs a REC signal to the DMA controller 22A, for example, and outputs the record clock φ _REC to the DM controller 22A.
Supplied to the DMA controller 22A as A control clock phi _A, DMA transfer only the data written in the A buffer of the buffer RAM20 to the hard disk A.

During the DMA transfer, the A / D conversion circuit 11 and the write counter 16 continue to write data to the B buffer of the buffer RAM 20. When the writing to the B buffer is completed, the data is written. Since the FULL signal is output from the incorporation counter 16, the control unit 14
Upon receiving the UL signal, the data in the B buffer is
Forward.

By repeating the above operation, the data obtained by dividing the waveform data into eight bits is stored in the buffer RAM 20.
Via the hard disk A.

Next, as shown in FIG. 7B, when performing a reproducing operation, for example, if data is recorded on the hard disk A, the DMA controller 22A
The LAY signal is output and the play clock φ _PLAY is used as the DMA control clock φ _A to set the DMA controller 22
A, and writes 128 k words of data from the hard disk A to the waveform RAM 25 by DMA transfer,
When the DMA transfer is completed, a start signal is output to the PCM sound source 29, the waveform data is read from the waveform RAM 25, and the sound is reproduced.

When the reading of the waveform data of the block A from the waveform RAM 29 is completed, the NEXT signal is output from the PCM tone generator 29.
Upon receiving the XT signal, the waveform data for the next 64 k words is written to the A block of the waveform RAM 25 by DMA transfer.

During the DMA transfer, the PCM sound source 29 sequentially reads out the waveform data from the B block to perform sound reproduction. When the reading of the waveform data of the B block ends, the PCM sound source 29 outputs a NEXT signal. Therefore, the control unit 14 receives this NEXT signal and further transfers the next 64 kwords of waveform data by DMA transfer to the waveform R.
Write to B block of AM25.

Recording and reproduction are performed as described above. As described above, the buffer R
Data transfer to AM 20, DMA transfer from buffer RAM 20 to hard disk A (or B), and DM from hard disk B (or A) to waveform RAM 25
Since the A transfer is performed using different time slots, it is possible to simultaneously perform the recording operation and the reproducing operation, such as recording on the hard disk B while reproducing from the hard disk A or performing the reverse operation. it can.

Since different DMA transfers can be performed at substantially the same time using different time slots as described above, for example, as shown in FIG.
_The data may be DMA-transferred from the hard disk to the buffer RAM by _PLAY , and the DMA transfer may be performed from the buffer RAM to the hard disk by the record clock φ _REC . Since the DMA transfer using the record code φ _REC uses four more time slots than the DMA transfer using the play clock φ _PLAY , the speed of the DMA transfer to the hard disk is slightly higher.

In the above embodiment, the DMA at the time of reproduction is
Buffer R in even time slot used for transfer
Although the write operation to the AM is performed, an odd number of time slots such as slot numbers “1”, “3”, “65”, and “67” are used for the write operation to the buffer RAM. You may.

Further, as shown by the broken line in FIG.
A / D conversion circuit 1 converts waveform data output from sound source 29
1 and add the input waveform data to the waveform data converted by the A / D conversion circuit 11 to record a composited waveform.

In the above embodiment, one of the two hard disks is read (PLAY) and the other is written (RE).
C) is used, but both may be read simultaneously and played back simultaneously. In that case, the 8-bit data bus is time-divided by even / odd time slots on two hard disks, and the 8-bit data bus and 16
A latch may be added between the bit data bus and the 16-bit bus may be used as an odd-numbered timing on a hard disk, and the PCM sound source may be used as an even-numbered timing.

[0061]

As described above, in the digital sound recording / reproducing apparatus of the present invention, the sound signal is sampled by the sampling means and converted into waveform data, and this waveform data is temporarily stored in the buffer memory. controlled by the second transfer preparative transfer control means from the first transfer to an external storage device from the memory to the external storage device to the waveform data storage circuit, based on the waveform data of the waveform data storage circuit by the reproduction means A digital audio recording / reproducing apparatus configured to reproduce an audio signal in a sampling means, a buffer memory, an interface path, and a bidirectional bus connected to each of a waveform data storage circuit and a timing control means. Time-division control is performed at a period shorter than the sampling period, and For toward the bus time slot,
The time slot corresponding to the sampling period used in the write operation to the buffer memory, since the other time slots were to be used in the first transfer timing for alternating the second transfer bets, one in bi-directional bus, the first and second example DMA transfer while reading the waveform data from the temporary write the waveform data storage circuit of the waveform data can be performed simultaneously to the buffer memory,
By sharing a bus or the like, the configuration of the entire apparatus can be simplified, and digital sound can be reproduced and recorded at once using an external storage device such as a hard disk.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an audio recording / reproducing system using a digital audio recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a digital audio recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 3 is a timing chart showing a relationship between each clock signal and a data bus time slot in the embodiment.

FIG. 4 is a diagram showing a memory map of a buffer RAM in the embodiment.

FIG. 5 is a diagram showing a memory map of a waveform RAM in the embodiment.

FIG. 6 is a timing chart showing a write operation of a waveform RAM in the embodiment.

FIG. 7 is a diagram illustrating an example of writing and reading operations of waveform data to and from a buffer RAM and a waveform RAM in a recording operation and a reproducing operation of the embodiment.

FIG. 8 shows a DM between two hard disks in the embodiment.
FIG. 9 is a diagram illustrating an example of a data write operation when performing A transfer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital sound recording / reproducing apparatus, 2 ... Microphone, 3 ... Sound system, 4 ... Personal computer, 11 ...
A / D conversion circuit, 13 clock generation circuit, 14 control unit, 20 buffer RAM, 21A, 21B SCSi
Interface circuit, 22A, 22B DMA controller, 25 Waveform RAM, 29 PCM sound source, 100
... 8-bit data bus, 200 ... address bus.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 31/20 G10H 1/00 101 G10H 7/00 511 G11B 20/10

Claims (1)

(57) [Claims] 1. A sampling means for sampling an acoustic signal and converting the same into waveform data; a buffer memory for temporarily storing the waveform data converted by the sampling means; and an external storage device for inputting the waveform data. An interface circuit for outputting; a waveform data storage circuit for storing a predetermined amount of waveform data; a reproducing means for reading the waveform data from the waveform data storage circuit to reproduce an acoustic signal; A bidirectional bus connected to each of a memory, an interface circuit, and a waveform data storage circuit; a first transfer from the buffer memory to the external storage device; and a transfer from the external storage device to the waveform data storage circuit. Second
Of a transfer control means for controlling the transfer bets, and a timing control means for time division control in short cycles from St. bling cycle of the sampling means the bidirectional bus, the bidirectional bus in the time division control for time slots, the time slots corresponding to the sampling period used in the write operation to the buffer memory, and the other time slot the first transfer and the second
Digital audio recording and reproducing apparatus characterized by being adapted for use at a timing alternates transfer and.