JPH0614427B2 - Digital interface circuit - Google Patents

Description

The present invention relates to an output device for transmitting digital data, such as a compact disc, and a pitch for performing key conversion so that the audio signal is an accompaniment that matches the pitch of a singing voice. The present invention relates to a digital interface circuit for controlling connection with a conversion device.

[Prior Art] Karaoke devices using a cassette tape or the like have been in widespread use for some time, but it is necessary to change the pitch conversion in order to obtain an accompaniment that matches the pitch of a singing voice. Therefore, in these karaoke devices using the deep reproduction, pitch conversion is possible by changing the running speed of the tape in order to match the pitch according to the user's request.

Furthermore, in recent years, as a reproducing device for music and images, a reproducing device using an optical disc such as a compact disc or a laser disc (product name) has been put into practical use.
This playback device has come to be used as a karaoke device.

[Problems to be Solved by the Invention] When the optical disk reproducing apparatus is used as a karaoke apparatus as described above, pitch conversion is performed by simply changing the tape reproducing speed as in the first conventional example. ,
That is, it is extremely difficult for the apparatus itself to perform pitch conversion by changing the rotation speed of the optical disk apparatus, that is, the reproduction speed. Therefore, in order to change the pitch, it is necessary to guide the pitch to another pitch conversion device, and it is required to realize an interface circuit that connects the two.

The present invention provides a digital data interface circuit capable of appropriately controlling connection between a disc device using an optical disc and a pitch conversion device, and directly deriving digital data to the pitch conversion device based on a request of the pitch conversion device. With the goal.

[Means for Solving the Problems] According to the present invention, a digital data output means for reproducing and outputting predetermined digital data and a digital data output means for introducing the digital data in a predetermined word unit and performing a latch process with a predetermined latch control signal are provided. First latch means for putting the latched data in word units into an output standby state and a frequency ratio of a control signal for controlling writing and reading of the digital data are set, and a write control signal based on this setting is pitch-converted. Pitch conversion means for outputting to the output means and the second latch means, and the data in word units is latched by the write control signal according to the frequency of the read control signal, and the latched word units are processed. Second latch means for putting data in an output standby state and the digital data based on the write control signal. And pitch conversion output means for outputting to the pitch conversion means as serial digital data, and pitch control is performed by writing control of the digital data for each predetermined word unit based on the writing control signal. The digital interface circuit is characterized in that

The digital data output from the digital data output means is L channel data and R channel data, and the first latch means stores the first L channel latch circuit for latching the L channel data and the R channel data. It is a first R channel latch circuit for latching.

The second latch means latches the L channel data introduced from the first latch means, and the second L channel latch circuit latches the R channel data introduced from the first latch means. A channel latch circuit, wherein the pitch conversion output means further serially mixes the L channel data and the R channel data introduced from the second latch means word by word and sends them to the pitch conversion means. It is a multiplexer.

[Operation] According to the present invention, the word unit data sent from the device is latched by the first latch means arranged in the next stage of the device outputting digital data in accordance with a predetermined latch control signal, and the data is latched. Put in output standby state.

Then, a desired pitch is selected or set by the pitch conversion device. The pitch converter sets the frequency ratio of the write and read control signals of the digital data to a desired ratio based on this setting, and the write control signal based on the set ratio is converted to the second latch means and the pitch converter. Output to output means.

Then, the second latch means latches the data in word units latched by the first latch means according to the frequency ratio of the read control signal by the write control signal, and puts it in the output standby state.

Further, the pitch conversion output means in the next stage introduces the digital data in word units based on the write control signal and outputs the left and right signals as serial word data to the pitch conversion device.

[Embodiment] FIGS. 1 to 5 are views showing an embodiment of the present invention.
Reference numeral 1 in FIG. 1 denotes digital data output means such as a compact disc device, which directly outputs digital data. The output means 1 outputs the following signals to the line | ₁ | ₂ | ₃ .

That is, L channel data (corresponding to 1 word) LchDATA (hereinafter referred to as Lch) and R channel data Rch composed of digital data as shown in FIG. 2 (b) on the data signal line | ₁ are respectively MSBs (bits indicated by L16 in the figure). ) ~ L
The data is serially output in the order of SB (the same as the first bit). The clock signal line | ₂ to output the shift clock CL as shown in FIG. (C), further control signal line | outputs a latch control signal LRCK shown in ₃ in the diagram (a).

The latch control signal LRCK is, for example, a signal that is at “1” level during the output time interval of the channel data Lch and at “0” level during the output time interval of the R channel data Rch. 2 is a shift register, which is the data LchRch
Is input serially for each data, and the shift clock CL
To output the respective data LchRch in parallel to the output terminals D01 to D016. Reference numerals 3 and 4 denote a first L channel latch circuit and a first R channel latch circuit, respectively.
Both latch circuits 3 and 4 form a first latch means 5. Then, the second L-channel latch circuit 6 and the second R-channel latch circuit 7 constitute second latch means 8.

The output lines derived from the output terminals D05 to D016 of the shift register 2 are connected to the respective input terminals of the first L channel latch circuit 3 and the first R channel latch circuit 4. In the example shown in the figure, the output terminal D01 to D04 of the shift register 2 is not used because the pitch conversion device (using an IC) described later is compatible with 12 bits. In addition, each control terminal in the first L channel latch circuit 3 and the first R channel latch circuit 4,
The control signal line | ₃ from the digital data output means 1 of the compact disk device is the first inverter 9
The latter is directly connected via. Next, the output line of the first L channel circuit 3 is connected to the input terminal of the second L channel latch circuit 6 in the second latch means 8, and the output line of the first R channel circuit 4 is connected to the input terminal of the second R channel latch circuit 7. Are connected respectively.

Further, one of the control signal lines | ₄ in the second L-channel latch circuit 6 and the second R-channel latch circuit 7 is directly connected to the other via the second inverter 10. A write control signal ADLR is derived from the control signal line | ₄ as shown in FIG. 4 (a). Incidentally, the write control signal ADLR has the same signal waveform as the latch control signal LRCK, but is asynchronous in time.

Furthermore, 11 is a multiplexer which is pitch conversion output means for introducing digital data based on the write control signal ADLR and outputting it as serial data to the pitch conversion device 12. The multiplexer 11 receives L channel data Lch and R channel data Rch from the second L channel circuit 6 and the second R channel circuit 7.
By operating the write control signal ADLR from the control signal line | ₄ to send the L channel data Lch and the R channel data Rch to the pitch conversion device 12 in word serial (serial in word units). .

The pitch conversion device 12 uses digital data LchRch.
By providing a writable and readable memory and setting the frequency ratio between both clock signals of the write control signal and the read control signal to a desired ratio, the pitch of the output audio signal is converted at a preset rate.

Further, the pitch conversion device 12 includes a control unit (not shown) and a data processing unit, which send a write signal for controlling the write frequency and a read signal for controlling the read frequency to the RAM.

Then, the pitch conversion is performed by arbitrarily setting the frequency ratio between the read frequency (f _r ) and the write frequency (f _w ). The writing frequency is a constant frequency value,
Arbitrary pitch conversion is performed by making the read frequency value variable. That is, the control unit divides the master clock by the first clock divider at a constant division ratio to create a write clock signal corresponding to the write signal, and further, the second divider divides the master clock into The frequency division is performed to create a read clock signal corresponding to the read signal, but the frequency division ratio is variable because the read frequency is variable as described above. Furthermore, the data processing unit performs fade-in / fade-out processing so that the external reproduction sound does not have discontinuity.

By the way, when the desired pitch is set to a high pitch (f _w < _fr ) or a low pitch ( _fw > _fr ) in the control unit of the pitch conversion device 12, _R is set as the writing frequency elapses.
The data written in the AM is read twice in the former, and the remaining data is skipped in the latter, so that the RAM is read.
The progress of the address of writing and reading within is corrected, and writing and reading are apparently progressed at the same time as a whole.

Next, the operation of the present invention will be described.

FIG. 2 output from the digital data output means 1
When the data LchRch shown in (b) is serially input to the shift register 2 (each pitch means serial), and the shift clock CL is also input, the data Lch
chRch is shifted by this shift clock CL, and each data LchRch shown in FIGS. 2D to 2S is output to the output terminals D01 to D016 in word units.

Then, when the latch control signal LRCK changes (falls) from "1" to "0", the output terminal D
01 to D016 from No. 1 to L1 corresponding to this terminal number
Each bit up to the sixth, that is, L channel data Lch1
Pieces are output in parallel.

Further, at this output timing, the latch control signal LRCK changes from "1" to "0" as described above, and this changes from "0" to "1" (rising) in the first inverter 9 and the first L channel latch circuit 3 The latch control signal LRCK of "1" level is introduced to. At this timing, the operation of the first L channel latch circuit 3 is controlled, and the L channel data Lch is input in parallel and latched in the first L channel latch circuit 3 as shown in FIG. 3 (b).

Then, as the shift progresses, as shown in FIG. 2 (a), the latch control signal LRCK is reversed from the above "0" to "1".
At the time of (rising), the output terminals D01 to D016
Each bit of R channel data Rch is output in parallel.

Next, at this timing, the "1" level latch control signal LRCK is introduced to the first R channel latch circuit 4 side, and the R channel data Rch1 is input in parallel and latched. Similarly, as the shift progresses, the subsequent L
The channel data Lch2 Lch3 ... Are individually latched in the first L channel latch circuit 3 by the control signal LRCK from the digital data output means 1 side (FIG. 3). The data Lch1 ... Rch1 ... Latched in this way are in an output standby state at the output terminals OUT of the respective latch circuits 3 and 4.

On the other hand, the write control signal ADLR is introduced to the second L channel latch circuit 6 and the second R channel latch circuit 7 in the second latch means 8 from the side of the pitch conversion device 12 described later. The write control signal ADLR changes from "1" to "1" as in the operation of the first latch circuit 5.
At the timing of 0 "(falling), the L channel data Lch1 ... Is transferred to the second L channel latch circuit 6 and latched. Further, the write control signal ADLR is"
At the timing from 0 "to" 1 "(rising), the second
R channel data Rch1 in the R channel latch circuit 7
... are transferred and latched.

In this way, the second L-channel latch circuit 6 and the second
The R channel latch circuit 7 has L channel data L
.. and R channel data Rch1, Rch2 ... Are individually latched by the write control signal ADLR in the pitch conversion device 12 (FIG. 4).

The data Lch1 ..., Rc thus latched
h1 ... are the second L channel latch circuit 6 and the second R channel, respectively.
The output terminal of the channel latch circuit 7 is in an output standby state.

Next, the L channel data Lch1 ... And the R channel data Rch1 ... Which are respectively sent from the second L channel latch circuit 6 and the second R channel latch circuit 7 are superimposed by the pitch conversion output means, for example, the multiplexer 11, and are shown in FIG. As shown in d), it becomes word-serial data that is serially mixed in word units.

Then, the word-serial data is input to the multiplexer 11 as a select signal, which is a write control signal AD.
Controlled by the LR, at the timing of the ADLR signal, the L channel data signals Lch1 ... And the R channel data signals Rch1.

In this way, each data is transferred in units of word L at the output timing of the write control signal ADLR from the pitch converter 12 by the intervention of the digital interface circuit of the present invention.
Each ch1, ..., Rch1 ... is written at proper timing, and pitch conversion is performed at a required rate.

Next, FIG. 6 shows a second embodiment of the present invention. This embodiment is a circuit example in the case where each data of the L channel data Lch and the R channel Rch is taken out from the digital data output means 1 in word serial at the timing of the latch control signal LRCK.

When deriving the data in word serial like this,
Regarding the data output mode, the arrangement of the shift register 2 in the first embodiment is omitted. By the way, in FIG. 6, the respective circuits after the second latch circuits 6 and 7 in FIG. 1 have the same operation as in the above-mentioned embodiment except for the shift register, and therefore are not shown. .

[Effects of the Invention] As described above, according to the present invention, the digital data derived from the digital data output means such as a compact disk device is serially taken in by the first latch means for the time being, and the data transmission of the disk device is hindered. On the other hand, by providing the second latch means and the pitch conversion output means so that the control signal from the pitch conversion device can be transmitted as the suitable data for the key conversion that matches the pitch of the user, Since the pitch conversion of the output audio signal is performed based on the ratio of the frequency ratio between the clock signals of the write control signal and the read control signal set by the pitch conversion device, the digital data is converted into word units at appropriate timing. You can now input to the pitch converter.

Further, since the digital data can be directly input to the pitch conversion device, there is an advantage that an A / D converter is not required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
(a) to (s) are diagrams showing input / output signals of the shift register, the third
FIGS. 4 (a) to 4 (c) are diagrams showing latch control signals and latch signals in the first latch circuit, and FIGS. 4 (a) to 4 (c) are write control signals and latch signals in the second latch signal. FIGS. 5 (a) to 5 (d) are diagrams showing output signals of pitch conversion output means such as a multiplexer, and FIG. 6 is a block diagram showing another embodiment of the present invention. 1: Digital data output means, 2: Shift register, 3: First L channel latch circuit, 4: Second L channel latch circuit, 5: First latch means, 6: First R channel latch circuit, 7: Second R channel latch Circuit, 8: second latch means, 9: first inverter, 10: second inverter, 11: pitch conversion output means such as multiplexer, 12: pitch conversion device, | ₁ : data signal line, | ₂ : Clock signal line, | ₃ : Latch control signal control signal line, | ₄ : Write control signal control signal line.

Claims (2)

[Claims] 1. A digital data output means (1) for reproducing and outputting predetermined digital data, and a latch control signal (LRC) which is introduced from the digital data output means (1) by introducing the digital data in word units.
K), the latch process is performed at the same time, and the first latch means (5) that puts the latched data in word units into an output standby state and the frequency ratio of the control signal for controlling the writing and reading of the digital data ( f _w : f _r ), and the pitch conversion means (12) for outputting the write control signal (ADLR) based on this setting to the pitch conversion output means (11) and the second latch means (8), Write the data in word units to the above write control signal (ADLR)
The second latch means (8) which is introduced from the first latch means (5) to put it in an output standby state, and the digital data, the write control signal (ADLR) set by the pitch conversion means (12). Pitch conversion output means (11) which is introduced from the second latch means on the basis of and is output to the pitch conversion means (12) as word serial digital data.
A digital interface circuit comprising: and a digital control circuit, wherein the digital data is sequentially and serially sent to the pitch conversion means word by word at every output timing of a write control signal (ADLR) toward the pitch conversion means. 2. The digital data output from the digital data output means (1) is L channel data and R channel data, and the first latch means (5) is a first L channel for latching the L channel data. A latch circuit (3) and a first R-channel latch circuit (4) for latching the R-channel data, and a second latch circuit (8) for the L-channel data introduced from the first latch means (5). A second L channel latch circuit (6) for latching the R channel data and a second R channel latch circuit (7) for latching the R channel data introduced from the first latch means (5), and the pitch conversion output means (11) Is the second latch means
The multiplexer according to claim 1, wherein the multiplexer is a multiplexer which sequentially and serially mixes the L-channel data and the R-channel data introduced from (8) word by word and sends them to the pitch conversion means. Digital interface circuit.