JPS59167809A - Digital interface circuit - Google Patents

Abstract

PURPOSE:To use a compact disc device as a device for recorded orchestral accompanyment by providing a digital interface circuit being able to connect properly the compact disc device and a pitch converter. CONSTITUTION:Lch and Rch data are outputted serially to a signal line l1, a shift clock CL is outputted to a line l2, and a latch control signal is outputted to an l3 further from a compact disc CD. A shift register SR to which the Lch, Rch data are inputted serially at each data is activated by a clock CL and transmits in parallel the Lch, Rch data. The Lch, Rch data are transmitted to the pitch converter U via the 1st L, R latch circuits L1, L2, the 2nd L, R latch circuits L3, L4 and a multiplexer MX operated by a control signal ADLR. The converter U can convert the pitch of an output sound signal in a required rate by setting the frequency ratio between both clocks of a write control signal and a read control signal to a desired ratio. Thus, the compact disc is adapted to the device for recorded orchestral accompanyment or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital interface circuit for coupling a compact disc device to a pitch conversion (key conversion) device.

Recently, compact disc devices have been put into practical use as playback devices for music and the like. By the way, when such a compact disc device is used as a karaoke device, pitch conversion becomes necessary in order to create an accompaniment that matches the pitch of the singing voice. However, it is no exaggeration to say that it is extremely difficult for compact disc devices to perform pitch conversion on their own by changing the rotational speed of the disc, or in other words, the playback speed.

Therefore, in order to convert the pitch of the output of a compact disc device, this output must be led to a separate Bi/Sochi conversion device and the pitch conversion must be performed by that device. It was requested to be implemented.

This invention was made based on such requests.
It is an object of the present invention to provide a digital interface circuit that can properly connect a compact disc device and a pitch conversion device.

The present invention will be explained below based on the drawings. Figures 1 to 5
The figure shows an embodiment of the present invention.

First, to explain the configuration, reference numeral CD in FIG. 1 is a compact disk device, and the following signals are outputted from this compact disk device CD to its signal lines i1t, t. That is, first, the data signal line t1 is connected to the data signal line t1 (see FIG.
L channel data (equivalent to 1 word) LchDATA (hereinafter simply referred to as Lch) and R channel data Rch consisting of digital data as shown in b)
, □ MSB (bit indicated by L16 in the figure) ~
It is output serially in the order of LSB (bit number 1). Furthermore, a shift clock CL as shown in the figure <at is output to the clock signal line t2, and a latch control signal LRC as shown in Fig.
Output K. For example, the latch control signal LRCK is L.
This signal is at the "1n level" at the output time interval of the channel data Lch, and at the "'0# level" at the output time interval of the R channel data Rch. SR is a shift register that serially transfers the data LchRch for each data. It is operated by the shift clock CL and outputs each data Lch and Rch in parallel to its output terminals DOI to D016.L and L are the first L channel latch circuit and the first R channel latch circuit, respectively, and both latch circuits the law of nature.

L2 constitutes a p first stage latch circuit. Also L3L4
are a second L channel latch circuit and a second R channel latch circuit, respectively, and these two latch circuits L3 and L4 constitute a second stage latch circuit. Output lines derived from the output terminals DO5 to DO16 of the shift register SR are connected to each input terminal of the first L channel latch circuit and the first R channel latch circuit, respectively. In the example shown in the figure, the pitch conversion device (using an IC) described later is compatible with 12 bits, so the output terminals DOI-4 of the shift register SR are not used.゛Also, each control terminal in the first L channel latch circuit and the glR channel latch circuit L2 is connected to a control signal line t3 from the compact disc device;
The other is directly connected via the inverter INV. Next, the input terminal of the second L channel latch circuit L3 is connected to the output line of the first L channel circuit L1, and the input terminal of the second R channel latch circuit L4 is connected to the output line of the first R channel circuit. Further, a control signal line t4 derived from the pitch conversion device U is connected to each control terminal of the second L channel latch circuit L3 and the second R channel latch circuit L4, one through the second inverter INV, and the other directly connected. ing. The control signal line t4 is connected to the control signal line t4 in Fig. 4 (a
), the write control signal ADLR is derived.

Incidentally, this write control signal ADLR has the same signal waveform as the latch control signal LRCK, but is asynchronous in terms of time. Nagi is a multiplexer that becomes an output stage circuit, and this one outputs L channel data Lch from the second L channel circuit L3 and the second R channel circuit L4.
and R channel data Rch are introduced, and activated by the write control signal ADLR from the control signal line t4, the L channel data Lch and R channel data Rch are word serially (meaning serial in units of words).
The signal is then sent to the pitch conversion device U. Further, the pitch converting device U is a known one, and the pitch converting device U is a known one, and the digital data Lch Rc
The pitch of the output audio signal can be set to the desired ratio by providing a mesori (not shown) that can write and read data h and setting the frequency ratio between the clock signals of the write control signal and the read control signal to a desired ratio. It converts by rate.

Next, the operation will be explained.

When the data Lch and Rch shown in Figure 2 (bJ) output from the compact disk device are input serially (each pit means serial) to the 77 register SR, and the shift clock CL is also input together, each data Lch and Rch is Shifted by this shift clock CL, the output terminals DOI to DO16 are outputted from FIG. 2(d) to (81).
Each data Lch and Rch as shown in FIG. 2 are output in word units. And the latch control signal LRCK is 1
At the time of change (fall) from `` to '0#, each bit from No. 1 to Li21 corresponding to this terminal number, that is, one piece of L channel data Lch, is output in parallel to the output terminals DOI to D016 as shown in the figure. is output to.

At this output timing, the latch control signal LRCK does not change from P1# to 0'' as described above, and this is the first
The latch control signal LRCK at the level "1#" is introduced into the first L channel latch circuit when the input signal INV1 changes from "0" to "1" (rise). At this timing, the operation of the first L channel latch circuit L1 is controlled, and as shown in FIG.
are input in parallel and latched. Next, as the shift progresses, as shown in FIG. 2(a), when the latch control signal LRCK changes from "On" to "1" (rising), contrary to the above, R channel data Rch is sent to the line output terminals DOI to D016.
One piece of each bit is output in parallel. And at this timing, the start control signal LRC of "1# level"
K is introduced into the first R channel La Sochi circuit L2 side, and this IcR channel data Rch1 is input in parallel and latched. Similarly, as the shift progresses, subsequent L channel data LcJLcbH... are transferred to the first L channel La Sochi circuit, and R channel data R
cJ, Rch3, . . . are individually latched in the first R channel latch circuit by control signals from the control disk device CD side (FIG. 3).

And each data Lch1 latched in this way...
RcJ... is in an output standby state at the output terminals of the respective two-notch circuits t and tL.

On the other hand, a write control signal ADLR is guided from the pitch conversion device U side to the second L channel latch circuit L3 and R channel latch circuit L4 in the second stage latch circuit. Similarly to the operation in the first stage latch circuit, the write control signal ADLR changes from #1 # to "o".
(fall), the L channel data Lch1 . . . is transferred to the second L channel latch circuit L3 and latched. Also, the write control signal ADLR is “
2nd R at the timing from “0” to “1” (rising)
R channel data Rch to channel latch circuit L4
1... are transferred and latched. In this way, the second L channel latch circuit L3 and the second R channel latch circuit L4 receive L channel data LchI L
ch2... and R channel data RchI Rc
J... is the write control signal A in the pitch conversion device U
Each is latched separately by the DLR (Figure 4). Each data Lch 1...Rch latched in this way
l... are in an output standby state at the output terminals of the respective latch circuits t and s L4.

Next, L channel data Lch 1... and R channel data R are sent out from the second L channel circuit L3 and the second R channel latch circuit L4, respectively.
chl... is superimposed by the multiplexer, and the result is shown in Figure 5 (
The resulting data is so-called word serial data that is serially mixed word by word as shown in d). This word serial data is controlled by the write control signal ADLR input to the multiplexer claw as a select signal, and the L channel data signal L is output at the timing of this ADLR signal.
ch□・°・ and R channel data signal Rch1・
Pitch conversion device U serially in word units of...
is sent to and written to. In this way, with the intervention of the digital interface circuit, the pitch converter U
The write control signal ADL from this pitch conversion device is
At the output timing of R, each data is output in word unit Lchl.
. . , RcJ . . . are written at appropriate timing, and pitch conversion is performed at a required rate.

Next, FIG. 6 shows a second embodiment of the present invention.

This embodiment is an example of a circuit in which L channel data Lch and R channel Rch data are taken out word-serially at the timing of the latch control signal LRCK from a compact disc device CD. In this way, when each data Lch and Rch is derived from the compact disk device CD in a word serial manner, the data output mode is similar to the output mode from the shift register SR, so in this embodiment, the data output mode is the same as the output mode from the shift register SR. The arrangement has been omitted.

Incidentally, in FIG. 6, the second stage latch circuit and the circuits below L4 in FIG. 1 are not shown.

The operation is similar to that of the previous embodiment except for the shift register.

As described in detail above, according to the present invention, digital data derived from a compact disk device is introduced and latched word by word by a required latch control signal derived from this compact disk device, and the data is always in an output standby state. a first-stage latch circuit; a second-stage latch circuit that introduces and latches the word-by-word data at the timing of the write control signal derived from the pitch conversion device side; and a second-stage latch circuit that always stands by for output; Since it is equipped with an output stage circuit that introduces each of the above-mentioned data and sends it as word serial data to the pitch conversion device, the digital data derived from the compact disk device is converted into word units at the appropriate timing required for pitch conversion. This provides the advantage of being able to be input to the pitch conversion device. Furthermore, since a pitch converter performs pitch conversion operations digitally, its input stage is usually equipped with an A/D converter, but digital data is sent from the output stage circuit to the pitch converter. Therefore, it is possible to omit the provision of an A/D converter in the pitch converter dedicated to this compact disc device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the digital interface circuit according to the present invention, and FIGS. 2(a) to (8)
~ Figures 5 (al ~ (d) are diagrams showing each signal waveform and signal content for explaining the operation of the same embodiment as above, and Figure 2 (
al~(S) is a diagram showing the input/output signals of the shift register,
Figures 3 (a) to (C1 are diagrams showing latch control signals and latch signals in the first stage latch circuit, Figure 4 (al to
(C) is a diagram showing the write control signal and latch signal in the second stage latch circuit, FIG. It is a block diagram showing CD: compact disk device LH1L3: first and second L channel latch circuits,
, L4! First and second R channel latch circuits Mx: multiplexer (output stage circuit) INVB, INVz: first and second inverters S
R: Shift register U: Pitch converter tl: Data signal line t2: Clock signal line l-3 Two-touch control signal control signal line t4: Write control signal control signal line Tararion Co., Ltd. Agent Ashi 1) Direct Mamoru

Claims (1)

[Claims] 1. Digital data derived from a compact disc device is introduced and latched in word units by a required latch control signal derived from the compact disc device, and the latched data in word units is constantly output. a first stage latch circuit that is in a standby state; and a write control signal derived from the pitch conversion device to introduce and latch the word unit data from the first stage latch circuit, and to latch the latched word unit data. a second stage latch circuit that is always in an output standby state; and an output stage that introduces each word unit data from the second stage latch circuit according to the write control signal and sends it as word serial data to the pitch conversion device. A digital interface circuit comprising: a circuit; 2. The digital data output from the compact disk device includes L channel data and R channel data, and the first stage latch circuit is a first L channel latch circuit that latches the L channel data, and the R channel data.
a first R channel latch circuit that latches channel data, a second stage latch circuit that includes a second L channel latch circuit that latches the L channel data, and a second R channel latch circuit that latches the R channel data; 2. The digital interface circuit according to claim 1, wherein the output stage circuit is a multiplexer that converts the L channel data and R channel data into word serial data.