JPS6065838U - analog signal input device - Google Patents

analog signal input device

Info

Publication number
JPS6065838U
JPS6065838U JP15801483U JP15801483U JPS6065838U JP S6065838 U JPS6065838 U JP S6065838U JP 15801483 U JP15801483 U JP 15801483U JP 15801483 U JP15801483 U JP 15801483U JP S6065838 U JPS6065838 U JP S6065838U
Authority
JP
Japan
Prior art keywords
analog signal
input device
signal input
analog
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15801483U
Other languages
Japanese (ja)
Inventor
北 哲夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15801483U priority Critical patent/JPS6065838U/en
Publication of JPS6065838U publication Critical patent/JPS6065838U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来方法に於ける1ワードのビット構成図、第
2図は本考案の実施例の為のブロック図、第3図は本考
案の1ワードのビット構成図、第4図はアナログ入力読
込み時のフローチャートである。 1・・・A/D変換部、2・・・マルチプレクサ、3・
・・ラッチ、4・・・シリアル伝送部、5・・・CPU
、6・・・アナログ入力回路、7・・ゼット合成回路。
Figure 1 is a bit configuration diagram of one word in the conventional method, Figure 2 is a block diagram for the embodiment of the present invention, Figure 3 is a bit configuration diagram of one word of the present invention, and Figure 4 is an analog It is a flowchart at the time of input reading. 1... A/D conversion section, 2... Multiplexer, 3...
...Latch, 4...Serial transmission section, 5...CPU
, 6...analog input circuit, 7...Z synthesis circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CPUと、Piloとの信号を伝送する為のシリアル伝
送部と、同一モジュール内に複数のアナログ信号をディ
ジタル変換することができるアナログ入力より成る装置
において、アナログ信号を選択する為の選択アドレスの
中で0すなわち全ピットOのパターンをアドレスとして
ではなく、選択可能状態としたことを特徴とするアナロ
グ信号入力装置。
In a device consisting of a serial transmission unit for transmitting signals between the CPU and the Pilot, and an analog input that can convert multiple analog signals into digital in the same module, the selection address for selecting an analog signal. An analog signal input device characterized in that a pattern of 0, that is, a pattern of all pits O, is not used as an address, but is in a selectable state.
JP15801483U 1983-10-14 1983-10-14 analog signal input device Pending JPS6065838U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15801483U JPS6065838U (en) 1983-10-14 1983-10-14 analog signal input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15801483U JPS6065838U (en) 1983-10-14 1983-10-14 analog signal input device

Publications (1)

Publication Number Publication Date
JPS6065838U true JPS6065838U (en) 1985-05-10

Family

ID=30348213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15801483U Pending JPS6065838U (en) 1983-10-14 1983-10-14 analog signal input device

Country Status (1)

Country Link
JP (1) JPS6065838U (en)

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