JP2696876B2 - Channel switching device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel switching method for a so-called bilingual recorded signal in digital audio such as a compact disk or an optical video disk.

[Summary of the Invention]

The present invention relates to a channel switching method, wherein a control signal used for writing data to a register and a channel control signal are gated, and the register write control is performed using the gated signal, thereby performing gating. By selecting conditions, good channel switching can be easily performed.

[Conventional technology]

For digital audio such as compact discs (CDs) and optical video discs (LDs), so-called bilingual recording standards have been defined. According to this, in the bilingual recording of these digital sounds, the audio signals of the main channel and the sub-channel are recorded corresponding to the audio signals of the stereo left channel and the right channel, respectively.

[Problems to be solved by the invention]

In general, when reproducing a bilingually recorded audio signal, the audio signals of the main and sub channels are respectively
In addition to outputting independently from the right audio system, a main channel or a sub-channel is selected as necessary, and the selected audio signal is output from both the left and right audio systems.

In this case, the reproduction of outputting the audio signals of the main and sub-channels from the left and right audio systems is performed as described above.
When the sub-channels correspond to the left and right channels of the stereo, the conventional stereo reproduction can be performed as it is. On the other hand, in the case of outputting the audio signal of the selected channel from both the left and right audio systems, conventionally, the left and right independently reproduced audio signals are switched at the final stage to output both audio systems. The output was done.

However, when performing such switching,
When a reproduced analog audio signal is processed by a general-purpose so-called analog switch, digital performance may be impaired due to frequency characteristics and the like. Therefore, conventional CD, L
In the reproducing apparatus such as D, channel switching is performed using a plurality of relays instead of the analog switch, but there are problems such as a complicated configuration and an increase in cost.

In digital audio such as CDs and LDs, signal recording is performed in one system by dividing 16-bit audio data into upper 8 bits and lower 8 bits, and time-division multiplexing left and right (main and sub) audio data. ing.

On the other hand, in reproduction, data processing such as error correction and data rearrangement is performed by 8 bits, and upper and lower 8 bits forming one audio data are successively rearranged by rearrangement, and the corresponding left and right bits are processed. -8-bit parallel data in which the right audio data is provided alternately is formed. This signal is converted to 16 bits, and the converted signal is separated into left and right audio data, and processing such as average value interpolation and pre-hold for the signal that cannot be corrected by the above error correction is performed. Output to the left and right audio systems.

In view of such a point, the present application is intended to perform good channel switching with a simple configuration.

[Means for solving the problem]

The present invention comprises a plurality of channel data each composed of a predetermined number of bits, wherein the bits of each channel data are divided into a plurality of bit strings, and data composed of the divided bit strings is formed. And a channel switching device in which each of the formed data is continuous for each of the channels and the plurality of channels are formed and supplied (input terminals (1a) to (1h)) sequentially. , First parallel data storage means comprising a number of registers (2a) to (2h) corresponding to the bit string to which each of the formed data is input;
Number of registers (2i) to (2p) corresponding to the above bit string
And second parallel data recording means to which the output data from the first parallel data storage means is inputted. The control signal for each of the formed data and the control signal for each of the channels are provided. The first and second parallel data storage means are driven for each of the formed data of the digital signal to connect and extract the formed data for each channel; or
The first and second parallel data storage means are driven for each of the formed data during the period of the arbitrary channel of the digital signal, and the formed data of the arbitrary channel are connected and taken out. Control circuit (circuit (4)) for generating a channel switching signal for switching
(5) A channel switching device provided with (16) to (19)).

[Action]

According to this, since the channel switching is performed by digital processing, digital performance is not impaired, and can be realized only by adding a simple gate circuit, etc., so that there is no risk of cost increase and the like, and good channel switching can be performed. It can be performed.

〔Example〕

FIG. 1 shows the above-described 8-bit data-processed signal.
This is a circuit for converting to 16 bits. In this figure, the parallel data signal of the bit from the previous stage is input terminal (1a)
Are supplied to the registers (2a) to (2h) through (1h). A system clock signal supplied to the terminal (3)
SCK is supplied to the registers (2a) to (2h), and the write enable signal WEN supplied to the terminal (4) is supplied to the registers (2a) to (2h) through the selection switch (5). This allows the input terminal (1
The 8-bit data signals supplied to a) to (1h) are written to the registers (2a) to (2h).

The data signals from the registers (2a) to (2h) are supplied to the registers (2i) to (2p), respectively. Signals from terminals (3) and (4) are supplied to registers (2i) to (2p). As a result, 1 is stored in the registers (2i) to (2p).
The previous 8-bit data signal is written, and the register (2
A) to (2p) form a 16-bit data signal.

The data signals from the registers (2a) to (2p) are supplied to the OR circuits (6a) to (6p), respectively. Also, a parallel load signal supplied to the terminal (7) and having a low potential when desired.
PLD is OR circuit (6a)-(6) through inverter (8)
p). The data signals from the OR circuits (6a) to (6p) are passed through the NOR circuits (9a) to (9p) and the inverters (10a) to (10p), respectively, to register (11a) to (11p).
p).

The signal SCK from the terminal (3) is connected to the registers (11a) to
The enable signal EN supplied to (11p) and further supplied to the terminal (12) is supplied to the registers (11a) to (11p). Thus, when the signal PLD has a low potential and the signal EN has a high potential, 16-bit data signals of the registers (2a) to (2p) are written to the registers (11a) to (11p).

Further, data signal signals from the registers (11a) to (11o) are supplied to OR circuits (13b) to (13p) of adjacent bits, respectively. The signal PLD from the terminal (7) is supplied to the OR circuits (13a) to (13p), and the OR circuits (13a) to (13p)
The signal from (13p) is passed through the NOR circuits (9a) to (9p) and the inverters (10a) to (10p) to the registers (11a) to (11p).
p). The other end of the OR circuit (13a) is supplied with, for example, a ground potential. Then, the data signal from the register (11p) is supplied to the output terminal (14).

Thus, when the signal PLD is at a high potential and the signal EN is at a high potential, the data signals of the registers (11a) to (11p) are sequentially shifted to adjacent bits in synchronization with the signal SCK, and a 16-bit serial data signal is output. It is taken out to the terminal (14).

The data signals from the registers (2o) and (2p) are supplied to the registers (2q) and (2r), respectively, and the terminal (3)
The signal from (4) is supplied to the registers (2q) and (2r), and pointer data and the like transmitted together with the audio data are output to the output terminals (15q) and (15r) through these registers (2q) and (2r). Be taken out.

Further, in this circuit, the signal WEN from the terminal (4) is supplied to the OR circuits (16) and (17), and
A signal LRC for determining left and right (main / sub) channels of the input data signal supplied to 8) is supplied to an OR circuit (16) and also supplied to an OR circuit (17) through an inverter (19). The signals from the OR circuits (16) and (17) and the signal from the terminal (4) are selected by the switch (5) and supplied to the registers (2a) to (2r).

Signals supplied to terminals (4) (7) (12) (18)
WEN, PLD, EN, LRC, etc. are supplied from the central control circuit (not shown), these signals are synchronized with the system clock signal SCK of the terminal (3), and are input to the input terminals (1a) to (1h). Connected pre-stage circuit and output terminals (14) (15q) (15r)
Are also driven in synchronization with the clock signal SCK.

In this circuit, a signal as shown in FIG.
When WEN is supplied to the terminal (4), for example, the first lower data L11 of the left channel is written into the registers (2a) to (2h) at the first pulse a as shown in FIG. Next, this data L1l is written into the registers (2i) to (2p) by the pulse b, and the register (2a) is written as shown in FIG.
The first upper data L1u of the left channel is written to (2h).

Further, the signals PLD and EN as shown in FIGS.
(12), data L1u and L1l from the registers (2a) to (2p) are supplied to the registers (11a) to (11p) while the signal PLD is at a low potential. Because of the high potential, this data is stored in the registers (11a) to (11
written in p). Next, when the signal PLD becomes high potential, the data of the registers (2a) to (2o) are sequentially transferred to the adjacent register (2b).
To (2p). At this time, since the signal EN is at a high potential, 16-bit data is serially extracted to the output terminal (14) as shown in FIG.

After this serial data signal is taken out, the signal EN
Is set to a low potential, and in this state, when the signal WEN is supplied again, for example, the first lower data R1l and the upper data R1u of the right channel are written into the registers (2a) to (2p), and so on. The operation is repeated. As a result, a normal stereo signal in which 16-bit left and right audio signals are alternately provided is output to an output terminal (14), and processing such as separation of left and right audio data, average value interpolation, and pre-holding is performed by a subsequent circuit. Is performed.

In contrast, the terminal (18) is supplied with a signal LRC as shown in FIG. So, for example, switch (5)
When the output signal of the OR circuit (16) is selected in (2), the signals (WEN) from which the pulses c and d corresponding to the right channel are deleted are supplied to the registers (2a) to (2p) as shown in FIG. Will be done. As a result, the right channel data R11 and R1u are not written into the registers (2a) to (2p) as shown in FIGS. I and J, and the previous left channel data L11 and L1u are held for a double period. On the other hand, the same signals as in the normal state are supplied to the terminals (7) and (12), and the signals taken out from the registers (11a) to (11p) to the output terminal (14) are, as shown in FIG. Only the data of the left channel is repeated twice, and a signal in which the left and right channels are both left channel data is extracted.

Therefore, if the left and right audio data are separated from this signal by the subsequent circuit, the left channel audio signal is output from both the left and right audio systems. For example, the main channel audio signal is converted to both the left and right audio signals. Can be output from the system.

Similarly, when the output signal of the OR circuit (17) is selected by the switch (5), the audio signal of the right (sub) channel is output from both the left and right audio systems.

Thus, according to the above-described circuit, the channel switching is performed by digital processing, so that the digital performance is not impaired and can be realized only by adding a simple gate circuit and the like. Channel switching can be performed.

In addition, since data for pointers and the like are similarly extracted, circuits at the subsequent stage such as average value interpolation and pre-hold can be used as they are, and the present invention can be carried out without any modification of the conventional device.

Further, the selection of the switch (5) can be easily controlled by a simple command signal from a central control circuit (not shown) or the like, and can be easily implemented.

Further, in the above-described example, the channel switching is performed by gating the write enable signal WEN of the registers (2a) to (2r). Thus, the same channel switching can be performed.

That is, in the above-described drawing, the write enable signal WEN
The circuits (shown by dashed lines) such as OR circuits (16) and (17) provided in the system are moved to the input portion of the parallel load signal PLD and provided, and the signal obtained at the output terminal (14) is provided. It returns to the other input of the OR circuit (13a) as shown by the broken line.

According to this, the parallel loading of the registers (11a) to (11p) is performed only on one channel, and the output signal is fed back during the period of the other channel so that the previous signals are stored in the registers (11a) to (11p). ).

Even in this case, channel switching by digital processing can be performed.

〔The invention's effect〕

According to the present invention, the channel switching is performed by digital processing, so that the digital performance is not impaired and can be realized only by adding a simple gate circuit and the like. You can now do.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the configuration. (1) is an input terminal, (2) and (11) are registers, and (3)
(4) (7) (12) (18) are signal terminals, (5) is a selection switch, (6) (13) (16) (17) is an OR circuit (8)
(10) (19) is an inverter, (9) is a NOR circuit, (14)
(15) is an output terminal.

Claims (1)

(57) [Claims] 1. A plurality of channel data each consisting of a predetermined number of bits, wherein the bits of each channel data are divided into a plurality of bit strings, and the data constituted by the divided bit strings are A channel switching device that is formed and that the formed data is continuous for each of the channels, and that the plurality of channels are formed and supplied so as to be sequential; A first parallel data storage unit comprising a number of registers corresponding to the bit string to be output; and a second parallel data storage unit comprising a number of registers corresponding to the bit string and receiving output data from the first parallel data storage unit. A control signal for each of the formed data and a control signal for each of the channels. The first and second parallel data storage means are driven for each of the formed data of the digital signal using the signal, and the formed data is connected and extracted for each channel; Alternatively, the first and second parallel data storage means are driven for each of the formed data during the period of the arbitrary channel of the digital signal, and the formed data of the arbitrary channel are connected. A channel switching device provided with a control circuit for generating a channel switching signal for switching whether or not to take out.