JP2623556B2 - Digital multi-channel recorder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital multi-channel recorder used for record production and the like.

[Summary of the Invention]

The present invention relates to a digital multi-channel recorder,
By writing the reproduced digital signal of each channel to the random access memory in a predetermined order, reading this memory in an arbitrary order, and recording the memory in each channel,
This is a digital signal copy between arbitrary channels with a simple configuration.

[Conventional technology]

For example, in the production of a record, audio signals recorded on independent channels for each musical instrument and the like are sequentially mixed and the like, and finally the channels (tracks) are reduced to desired two-channel audio signals. ing.

In this case, when a so-called multi-channel recording device (recorder) is used, an inter-channel copy operation of transferring a recording signal of an arbitrary channel to another channel is required.

However, in this case, if an arbitrary copy is to be made between the channels of a 2-channel recorder, for example, four switches are required as shown in FIG. 3, and generally a switch of the square of the number of channels is required. . For example, when the number of channels is 48, as many as 2304 switches are required, which is difficult to realize due to the circuit configuration, and it is not easy to operate these switches to predetermined positions.

By the way, in the above multi-channel recorder,
Digital recording of signals has been put to practical use.
According to such a digital multi-channel recorder, even if signal processing such as mixing is performed, there is very little risk of signal deterioration, so that good track down can be performed. However, even if such a digital multi-channel recorder is used, conventionally, the same switch circuit and complicated switching operation as described above were required to perform the above-described inter-channel copy operation.

[Problems to be solved by the invention]

As described above, in the conventional technique, there is a problem that a complicated switch circuit is required when an arbitrary inter-channel copy is performed, and the operation is not easy.

[Means for solving the problem]

According to the present invention, a reproducing means (head (2)) for reproducing a signal recorded for each of a plurality of channels, and converting the reproduced reproduced signals of the respective channels into a time-division serial signal. The parallel / serial conversion means (circuit (21)), the address setting circuit (25), and the parallel / serial converted signal are written, and the signals are read out in an order based on the address set by the address setting circuit. A random access memory (22), serial-parallel conversion means (circuit (29)) for serial-to-parallel conversion of a signal read from the random access memory and returning the signal to each channel. Switching means (cross fader (7)) for switching and outputting a signal output from the means and a reproduction signal from the reproducing means, and the respective channels from the switching means. It has a recording means for recording a signal with the (head (15)) is a digital multi-channel recorder according to claim.

[Action]

According to this, the random access memory (RAM) is interposed when copying between channels,
The movement between channels can be easily performed only by changing the write address and the read address of the RAM, and the inter-channel copy can be performed with a simple configuration, and the operation at that time can be performed very easily. .

〔Example〕

In FIG. 1, a plurality (for example, 48) on the tape (1)
Are reproduced by, for example, 48 reproducing heads (2) provided opposite to the respective tracks, and the reproduced signals are respectively reproduced and equalized by an equalizer amplifier (3). ) Is supplied to the PLL (4), and a data clock is generated to be digital data. These digital signals are respectively supplied to a decoder (6) through a time base collector (5) for removing fluctuations in the tape running system, and interleave demodulation and error correction are performed.

The signal from the decoder (6) is supplied to the crossfader (7). Normally, the selector (8) is switched to the lower side of the figure, and another signal supplied to the terminal (9) is supplied to the AD conversion circuit (10) to be converted into a digital signal. Is supplied to the fader (7) and cross-fade with the signal from the decoder (6). The signal from this fader (7) is applied to the DA conversion circuit (1
The signal is output to the output terminal (12) through 1), and the signal from the fader (7) is supplied to the encoder (13) to perform interleaving and error correction code addition. (15) and recorded on each track on the tape (1).

The above circuits are provided in parallel for each track (= channel) on the tape (1), and signal processing is performed in parallel for each channel.

On the other hand, in the above apparatus, the signal of 48 channels from the decoder (6) is converted into a parallel-serial (PS) conversion circuit (21).
The conversion circuit (21) is read out in series with a clock signal 48 times the data clock to form a one-channel time division serial signal. This signal is supplied to a random access memory (RAM) (22).

On the other hand, write addresses in a predetermined order are formed by the address counter (23). Further, a signal from the keyboard (24) is supplied to an address setting circuit (25), and an address set in an arbitrary order is supplied to a parallel / serial conversion circuit (26) to form a read address in an arbitrary order. These addresses are supplied to the selector (27). Further, a write / continue control signal corresponding to each half cycle of the 48-times clock signal is supplied to the terminal (28), and the selector (2)
7) is controlled. The signal from the selector (27) is supplied to the address input of the RAM (22), and the control signal from the terminal (28) is supplied to the RAM (22).

The signal read from the RAM (22) is supplied to a serial / parallel (SP) conversion circuit (29), and the conversion circuit (29) is read in parallel by the above data block to form a 48-channel parallel signal. You. This signal is supplied to the selector (8).

Therefore, in this device, when a serial signal as shown in FIG. 2A is supplied to the data input of the RAM (22), the counter (23) outputs the data in a predetermined order as shown in FIG. Address is supplied. On the other hand, for example, a read address in an arbitrary order as shown in FIG. C is supplied from the conversion circuit (26), and the selector (29) is controlled by a control signal as shown in FIG. By the switching, the address as shown in FIG.
2) supplied to. In addition, the control signal from terminal (28)
By being supplied to the AM (22), a serial signal in which the order of the data of each channel is changed as shown in FIG. F is taken out from the data output of the RAM (22).

Then, this signal is subjected to serial-parallel conversion by the conversion circuit (29), whereby the data of each channel is exchanged.
This signal is supplied to the fader (7) through the selector (8) and cross-fade with the original signal, so that a digital signal copy between desired channels is performed.

That is, in the above-described example, for example, the third channel is copied to the first channel, the first channel is copied to the second channel, and the copying of each channel can be performed simultaneously. By setting the same read address to a plurality of channels, for example, the first channel is copied to the sixth channel together with the second channel, and can be simultaneously copied to a plurality of channels.

In this manner, digital signal copying between desired channels is performed. According to the above-described apparatus, when performing inter-channel copying, this R is achieved by interposing a RAM.
The movement between channels can be easily performed only by changing the write address and the read address of the AM, the copy between channels can be performed with a simple configuration, and the operation at that time can be performed very easily.

In the above-described apparatus, the system from the time base collector (5) to the encoder (13) can be processed by the time-division serial signal. Circuit, encoder (1
The serial-to-parallel conversion circuit is provided on the output side of 3), and the conversion circuits (21) and (29) described above become unnecessary.

Further, according to the above-described device, even when the number of channels increases, it is only necessary to add an address of the RAM (22), and it is possible to easily correspond to a desired multi-channel recorder.

〔The invention's effect〕

According to the present invention, when a random access memory (RAM) is interposed at the time of performing inter-channel copying, movement between channels can be easily performed only by changing a write address and a read address of the RAM. Copying between channels can be performed with a simple configuration, and the operation at that time can be performed very easily.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIG. 3 is a diagram for explaining a conventional technique. (1) is a tape, (2) is a reproducing head, (6) is a decoder, (7) is a crossfader, (8) and (27) are selectors, (13) is an encoder, (15) is a recording head, and (21) )
(26) is a parallel / serial conversion circuit, (22) is a random access memory, (23) is an address counter, (24) is a keyboard, (25) is an address setting circuit, (28) is a write / read control terminal, (29) ) Is a serial-parallel conversion circuit.

Claims (1)

(57) [Claims] 1. A reproducing means for reproducing a signal recorded for each of a plurality of channels, a parallel-serial converting means for converting the reproduced reproduced signals of the respective channels into a time-division serial signal. An address setting circuit, a random access memory in which the parallel-to-serial converted signal is written, and wherein the signals are read out in an order based on the address set by the address setting circuit; Serial-to-parallel conversion means for performing a serial-to-parallel conversion on the output signal and returning the signals to the respective channels, and switching means for switching and outputting a signal output from the serial-parallel conversion means and a reproduction signal from the reproduction means. Recording means for recording a signal for each channel from said switching means. Channel recorder.