JPS5984315A - Memory circuit - Google Patents

Abstract

PURPOSE:To minimize the capacity of an RAM, by optionally changing the readout order of data from the RAM in accordance with the stored content of a read-only memory. CONSTITUTION:A counter 11 is a 24-notation write symbol counter and the value of the counter 11 itself is used as the low-order five bits of an RAM18. The high-order two bits of the RAM18 are optionally selected from an ROM14 in accordance with the frame counter value of another counter 12. A counter 13 is a 24-notation readout symbol counter and the value of the counter 13 itself is used as the least significant bit of the RAM18 and the other four bits of the RAM18 are inputted into the RAM18 after key are passed through an ROM16 and rearrangement of the symbol is performed on them. The high-order two bits of the RAM18 are optionally selected from an ROM15 in accordance with the frame counter value of the counter 12. Therefore, the capacity of the RAM18 can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention converts, for example, an audio signal into a pulse code modulation signal (hereinafter abbreviated as a PCM signal), and converts this PCM signal into pits on a disk in a spiral or concentric pattern. The present invention relates to a memory circuit used to perform time axis manipulation of data in a digital signal processing circuit such as a playback device for arranged PCM audio discs.

Conventional configuration and its problems The decoding method for optical PCM audio discs is CI.
It is called an RC decoder and has a configuration as shown in FIG. In Figure 1, C1 decoder (2) and C2
The decoder (4) is a part that performs code error detection and correction using parity, and the C1 descrambling circuit (1
), dinterleave (3), and C2 descrambling circuit (5) are the parts that perform time axis operations such as delaying, arranging, and rearranging data in symbol units in a predetermined format. It is. Here, the symbol means data of the upper or lower 8 bits of a PCM signal in which 1 word is made up of 16 bits. In addition, a collection of symbols is expressed by the word frame, and after decoding by the CIRC decoder in Fig. 1, one frame consists of 24 symbols, and before decoding, 8 symbols of parity are added, and one frame consists of 82 symbols. It is made up of symbols.

Figure 2 is a diagram showing the actual operation of data symbols in the C2 descrambling circuit. In the signal names Sm and n,
m indicates a frame number, and n indicates a symbol number. Also, ■ indicates a two-frame delay operation. For example, S2
．． o is the 0-total H symbol of the second frame, So, 12
represents the 12th symbol of the θ-th frame.

To perform the operation shown in FIG. 2, a random access memory (hereinafter abbreviated as RAM) is usually used.

The CIRC decoder shown in Figure 1 is generally implemented as a large-scale integrated circuit (hereinafter abbreviated as LSI) from a cost perspective.
A C2 descrambling circuit is also included therein. However, since the C2 descrambling circuit uses RAM,
If you have sincerity outside of LSI, the cost will be high again, so LS
It is better to put RAM inside I. However, since the vote occupies a larger area within the LSI than a read-only memory (hereinafter abbreviated as ROM) or the like, the capacity must be increased as much as possible.

OBJECTS OF THE INVENTION The present invention provides a C2 descrambling circuit having a configuration as shown in FIG.
Of the 4 symbols, the first 12 symbols have no frame-by-frame delay, and only the latter 12 symbols have a 2-frame delay, so by considering the RAM of the memory space as shown in Figure 8, the voting condition can be determined. The purpose is to minimize.

Structure of the Invention In order to achieve the above object, the present invention provides a first counter that determines a write address of the random access memory, a second counter that determines a read address of the memory, and a second counter that determines a read address of the memory. an eighth counter that determines an upper address; a first read-only memory whose address inputs are the outputs of the first and eighth counters; and a second read-only memory whose address inputs are the outputs of the second counter. , an eighth read-only memory whose address inputs are the outputs of the second and eighth counters, and a first memory which is the last write address of the random access memory.
a counter and a selection path for switching between the output of the first read-only memory and the outputs of the second and third read-only memories serving as the final read address, and the random access memory is provided with an output of the selection circuit. has an arbitrary number of bits as an address input, and is configured so that data can be read out from the random access memory in any order (depending on the memory contents of the eight types of read-only memories). .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 8th
The figure shows the memory address space of the RAM of the 02 descrambling circuit of the present invention. One square represents the memory space for 12 symbols. The two columns on the left represent the first 12 symbols, and the four columns on the right represent the second half. It represents 12 symbols.

Also, solid line and broken line arrows indicate the order of writing and reading, respectively. (a), (b), (c), (
d) represents the position in the memory space of l writing and reading for each frame, and (a
)→(b)→(C)→(d)→(a)→... is repeated every 4 frames. The state of the memory space in FIG. 8 is 12 x 6 symbols, and one symbol is 8 bits, so 12 x 6 x 8 = 576 bits, which can be included in an LSI.

If the block diagram of the entire C2 descrambling circuit including the memory space in FIG. 8 is blanked out, it becomes as shown in Figure 34. Fourth
In the figure, counter 0 is a 24-base write symbol counter, and when the selection circuit 0η selects the write side,
The lower 5 bits of the RAM O field are input with the value of counter 01), and the upper 2 bits are input from ROM 0 fathom to (a in Fig. 8) according to the value of the frame counter of counter 04.
) to (d) is selected. The counter (to) is a 24-decimal readout symbol counter, and the selection circuit α
When the read side is selected, the value of the counter 03 is input as is to the lowest 5 bits of the RAM Qll, and the other 4 bits are input to the ROM Qfl.
After the symbols shown in FIG. 2 are rearranged through , the symbols are input to RAM 01. The upper two bits select one of the states (a) to (d) in FIG. 8 from the ROM (c) according to the value of the frame counter of the counter (6). Figure 4 (7J ROM Q4, ROM C16,
ROM CIG It is all 48 bits and small so it does not occupy a large area inside the LSI.

As described above, according to the present invention, the entire circuit is simplified,
In addition, when considering LSI implementation, the RAM capacity is minimal, and even if the symbol rearrangement format of the C2 descrambling circuit changes, it can be handled simply by changing the ROM coding. It is something that can be demonstrated.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the configuration of the CIRC decoder, Fig. 2 is a diagram showing the data manipulation of the C2 descrambling circuit,
FIG. 8 is a memory address space diagram of the RAM according to the present invention, and FIG. 4 is a block diagram showing the configuration of the C2 descrambling circuit according to the present invention. (5)...C2 descrambling circuit, uU Oa O
:1...Counter, OΦQIjαQ...ROM,
αη...Selection circuit, 0→...RAM. Agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 (a)
c) td) Figure 4

Claims (1)

[Claims] 1. A first counter that determines a write address of the random access memory, a second counter that determines a read address of the memory, and a second counter that determines an upper address for reading and writing of the memory. 8 counter and the first
and a first read-only memory whose address input is the output of the eighth counter, a second read-only memory whose address input is the output of the second counter, and whose address is the output of the second and eighth counters. An eighth read-only memory that is manually operated, a first counter that is the final write address of the random access memory, and a second counter that is the output of the first read-only memory and the final read address.
and a selection circuit for switching the output of the eight read-only memories, and the random access memory has an arbitrary number of bits using the output of the selection circuit as an address input, and Depending on the memory content,
A memory circuit configured to read data from a random access memory in any order. 2. The scope of the patent claim is characterized in that the contents of the read-only memory are reduced to an appropriate value by 1, thereby reducing the state of the random access memory to a minimum, so that it is not lost to the large-scale detection and collection circuit. The memory circuit according to item 1.