JPH07210994A - Digital multi-channel recorder - Google Patents

Abstract

PURPOSE:To arbitrarily shunt respective channels to be synthesized. CONSTITUTION:Parallel signals from a decoder 6 are supplied to parallel series conversion circuits 21, 31, each one channel time division series signal is formed. These signals are supplied to random access memory (RAM) 22, 32. Also, writing addresses of the prescribed order are formed by address counters 23, 33, and addresses set in arbitrary order from setting circuits 25, 35 are supplied to parallel series conversion circuits 26, 36, thereby read-out addresses of arbitrary order are formed. These addresses are selected for each half period of a clock signal and supplied to address input terminals of RAMs 22, 32. Also signals read out from these RAMs 22, 32 are supplied to series parallel conversion circuits 29, 39, these parallel signals are supplied to selectors 8, 80, selected with an external digital signal and supplied to input terminals (a), (b) of a cross fader 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multi-channel recorder used for record production and the like.

[0002]

2. Description of the Related Art For example, in the production of records, acoustic signals recorded on independent channels for each musical instrument,
In some cases, mixing (sequential) or the like is performed and finally channel (track) down to desired acoustic signals of two channels or the like is performed. In this case, when a so-called multi-channel recording device (recorder) is used, an inter-channel copy operation of transferring a recording signal of an arbitrary channel to another channel is required.

However, in that case, if an arbitrary copy is to be made between the channels of a 2-channel recorder, for example, four switches are required as shown in FIG. 4, and generally a switch for the square of the number of channels is required. Becomes This is 230 if the number of channels is 48, for example.
As many as four switches are required, it is difficult to realize the circuit configuration, and it is not easy to operate each of these switches at a desired position.

By the way, in the above-mentioned multi-channel recorder, it has been put into practical use to record signals digitally. According to such a digital multi-channel recorder, even if signal processing such as mixing is performed, the possibility of signal deterioration is extremely small, and therefore good track down can be performed. However, even if such a digital multi-channel recorder is used, in order to perform the above-mentioned inter-channel copy operation, conventionally, the same switch circuit as that described above and a complicated switching operation were required.

On the other hand, the applicant of the present application has previously proposed a device which facilitates channel switching by rearranging digital signals using a random access memory (RAM) (Japanese Patent Laid-Open No. 63-228471). Referenced.

That is, in this prior application, as shown in FIG. 5, multi-channel digital signals independently recorded in a plurality of (for example, 48) tracks on the tape 1 are
The data is reproduced by, for example, 48 reproducing heads 2 provided so as to face each track. The reproduced signals are supplied to the PLL 4 through the reproducing and equalizer amplifiers 3, respectively, and a data clock is generated to be digital data.

Each of these digital signals is supplied to a decoder 6 through a time base collector 5 for eliminating fluctuations in the tape running system, and interleave demodulation and error correction are performed. The signal from the decoder 6 is supplied to the input a of the crossfader 7. Here, normally, the selector 8 is switched to the lower side of the figure, and the other signal supplied to the input terminal 9 is supplied to the AD conversion circuit 10 to be a digital signal, and this digital signal is fed to the fader 7.
Of the signal from the decoder 6 and is cross-faded with the signal from the decoder 6 described above.

The signal from the fader 7 is taken out to the output terminal 12 through the DA conversion circuit 11. Further, the signal from the fader 7 is supplied to the encoder 13 to interleave and add an error correction code. The signal from the encoder 13 is supplied to the recording head 15 through the recording amplifier 14 and recorded on each track on the tape 1. The above circuits are provided in parallel for each track (= channel) on the tape 1, and signal processing is performed in parallel for each channel.

Further, in the above-mentioned device, the 48-channel signal from the decoder 6 is supplied in parallel to the parallel-serial (PS) conversion circuit 21, and the conversion circuit 21 reads serially with a clock signal which is 48 times the data clock. Then, a time-division serial signal of 1 channel is formed. This signal is supplied to the random access memory (RAM) 22.

On the other hand, the address counter 23 forms write addresses in a predetermined order. A signal from the keyboard 24 is supplied to the address setting circuit 25, and addresses set in an arbitrary order are supplied to the parallel-serial conversion circuit 26 to form read addresses in an arbitrary order. These addresses are supplied to the selector 27. The address counter 23 and the parallel-serial conversion circuit 26 are also controlled by a clock signal which is 48 times as high as the data clock as in the conversion circuit 21 described above.

Further, the write / read (W / R) control signal corresponding to each half cycle of the above 48 times clock signal is applied to the terminal 2.
8 and the selector 27 is controlled by this signal. Then, the signal from the selector 27 is supplied to the address input of the RAM 22, and the control signal from the terminal 28 is supplied to the RAM 22. The write / read control signal is, for example, the clock signal itself formed with a duty ratio of 50%.

The signal read from the RAM 22 is supplied to the serial-parallel (SP) conversion circuit 29. Further, the conversion circuit 29 is read in parallel with the above-described data clock, and a 48-channel parallel signal is formed. This signal is supplied to the selector 8, and the other signal supplied to the input terminal 9 is selected from the digital signal supplied to the AD conversion circuit 10 and supplied to the input b of the crossfader 7.

Therefore, in this device, when the serial signal as shown in A of FIG. 6 is supplied to the data input of the RAM 22, the counter 23 writes data in a predetermined order as shown in B of FIG. Address is supplied. On the other hand, the conversion circuit 26 supplies read addresses in an arbitrary order as shown in C of FIG.

Then, the selector 29 is switched by the control signal from the terminal 28 as shown in D in the figure, whereby the address as shown in E in the figure is supplied to the RAM 22. Further, by supplying a control signal from the terminal 28 to the RAM 22, a serial signal in which the order of the data of each channel is changed is taken out from the data output of the RAM 22.

The conversion circuit 29 performs serial-parallel conversion on this signal, so that the data of each channel is exchanged. Further, this signal is supplied to the fader 7 through the selector 8 and cross-faded with the original signal, whereby digital signal copying between desired channels is performed.

That is, in the above example, for example, the third channel is copied to the first channel, the first channel is copied to the second channel, and so on, the respective channels can be simultaneously copied. Further, by setting the same read address to a plurality of channels, for example, the first channel is copied to the sixth channel together with the second channel, and it is possible to copy to the plurality of channels simultaneously.

However, in the above-mentioned device, when the third channel is copied to the first channel, for example, when the channel is restored to the original first channel, digital signal copying can be performed by crossfading. However, for example, when the third channel is copied to the first channel and a channel other than the first channel is further copied to the third channel, digital signal copying cannot be performed by crossfade.

That is, when there are first, second and third channels as shown in A, B and C of FIG.
By switching the first and second channels so that the second channel can be taken out at M22, the first and second channels are supplied to the inputs a and b of the fader 7 as shown by D and E in FIG. This allows crossfading from the first channel to the second channel as shown on the left side of F in FIG. Also, this can be returned to the original first channel by crossfading.

However, when the second channel is copied to the first channel and the third channel is further copied to the first channel, the channel supplied to the input a of the fader 7 is changed to a channel other than the first channel. I can't. For this reason, the channel supplied to the input b of the fader 7 is changed as shown by E in the same figure. In this case, crossfade cannot be performed, and F in the same figure is shown.
The switching is instantaneous as shown in the center of. After this, when returning to the first channel again, crossfading can be performed as shown on the right side of F in FIG.

That is, in this apparatus, when the digital signal copy between desired channels is performed by cross-fade, it is necessary to restore the original channel once before performing the copy. For this reason, the channels to which digital signals can be copied are restricted, which impedes the user's freedom of work.

[0021]

The problem to be solved is that the conventional technology limits the channels that can be used to copy digital signals, which impedes the user's freedom of work.

[0022]

The first means of the present invention reproduces the digital signals recorded for each of the multi-channels (head 2 to decoder 6) and reproduces each of the reproduced channels. The digital signals of are written to respective addresses of the first and second random access memories 22 and 32 in a predetermined order (counters 23 and 33), and written to respective addresses of the first and second random access memories. The digital signals are read out in an arbitrary order (setting circuits 25 and 35),
The read digital signals are combined for each channel (crossfader 7) and recorded for each channel of the multi-channel (encoder 13 to
It is a digital multi-channel recorder adapted to perform head 15).

According to a second means of the present invention, in the digital multi-channel recorder described in the first means, the reproduced digital signals for the respective channels are respectively parallel-serial converted in a predetermined order (circuits 21 and 31). ) To write to each address of the first and second random access memories, and to serial-parallel convert the digital signals read from the first and second random access memories in arbitrary order (circuit 29, 39) and a digital multi-channel recorder characterized by separating each channel.

According to a third aspect of the present invention, in the digital multi-channel recorder according to the first aspect, the synthesis for each of the channels is a crossfade, and the crossfade is performed between any of the channels. This is a digital multi-channel recorder characterized by the above.

According to a fourth aspect of the present invention, in the digital multi-channel recorder according to the first aspect, the digital signal read from at least one of the first and second random access memories is a digital signal from the outside. The digital multi-channel recorder is characterized in that a means (selector 8, 80) for replacing the

[0026]

According to this, the channels to be combined can be arbitrarily exchanged, and the degree of freedom of work can be made extremely high.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, in the present invention, the circuit corresponding to the parallel-serial conversion circuit 21 to the serial-parallel conversion circuit 29 in the system of the signal directly supplied from the decoder 6 to the crossfader 7 in the conventional apparatus shown in FIG. Is provided.

Therefore, in the configuration of the present application shown in FIG. 1, first, the signal from the decoder 6 is the parallel-serial conversion circuits 21 to 21 described above.
Another signal supplied to the selector 8 through the serial-parallel conversion circuit 29 and supplied to the above-mentioned input terminal 9 is the AD conversion circuit 1.
The digital signal supplied to 0 is selected and supplied to the input b of the crossfader 7.

At the same time, the 48-channel signal from the decoder 6 is supplied in parallel to the parallel-serial (PS) conversion circuit 31, and the conversion circuit 31 is serially read out with a clock signal that is 48 times the data clock and 1 A time division serial signal of the channels is formed. This signal is supplied to the random access memory (RAM) 32.

On the other hand, the address counter 33 forms write addresses in a predetermined order. Further, a signal from the keyboard 34 is supplied to the address setting circuit 35, and addresses set in an arbitrary order are supplied to the parallel-serial conversion circuit 36 to form read addresses in an arbitrary order. These addresses are supplied to the selector 37. The address counter 33 and the parallel-serial conversion circuit 36 are also controlled by a clock signal that is 48 times the data clock as in the conversion circuit 31 described above.

Further, the write / read (W / R) control signal corresponding to each half cycle of the above 48 times clock signal is applied to the terminal 3.
8 and the selector 37 is controlled by this signal. The signal from the selector 37 is supplied to the address input of the RAM 32, and the control signal from the terminal 38 is supplied to the RAM 32. The write / read control signal is, for example, the clock signal itself formed with a duty ratio of 50%.

The signal read from the RAM 32 is supplied to the serial / parallel (SP) conversion circuit 39. Further, the conversion circuit 39 is read in parallel with the above-mentioned data clock, and a 48-channel parallel signal is formed. This signal is supplied to the selector 80, and another signal supplied to the input terminal 9 is selected from the digital signal supplied to the AD conversion circuit 10 and supplied to the input a of the crossfader 7. The other structure is the same as that of FIG. 5 described above.

Therefore, in this device, when the serial signal as shown in A of FIG. 2 is supplied to the data input of the RAM 32, the counter 33 writes data in a predetermined order as shown in B of FIG. Address is supplied. On the other hand, the conversion circuit 36 supplies read addresses in an arbitrary order as shown in C of FIG.

Then, the selector 39 is switched by the control signal from the terminal 38 as shown in D of the same figure, whereby the address as shown in E of the same figure is supplied to the RAM 32. Further, by supplying the control signal from the terminal 38 to the RAM 32, a serial signal in which the order of the data of each channel is exchanged is taken out from the data output of the RAM 32, as shown in F of FIG.

The signals of the respective channels are exchanged by serial-parallel conversion of this signal by the conversion circuit 39. Further, this signal is supplied to the fader 7 through the selector 80 and cross-faded with the signal from the selector 8 to perform digital signal copying between desired channels.

That is, when there are first, second and third channels as shown in A, B and C of FIG.
By switching the first and second channels so that the second channel can be taken out at M22, the first and second channels are supplied to the inputs a and b of the fader 7 as shown by D and E in FIG. This allows crossfading from the first channel to the second channel as shown on the left side of F in FIG.

Then, with the second channel being copied to the first channel, the first channel is stored in the RAM 32 described above.
By changing the channel so that the third channel is taken out, the inputs a and b of the fader 7 are supplied with the third and second channels as shown by D and E in FIG. As a result, as shown in the center of F in FIG.
A crossfade can be performed from the channel to the third channel.

Further, in the state where the third channel is copied to the first channel, the first data is stored in the RAM 22 described above.
By changing the channels so that the first channel is taken out, the inputs a and b of the fader 7 are supplied with the third and first channels as shown by D and E in FIG. As a result, as shown on the right side of F in FIG.
A crossfade can be performed from the channel to the first channel.

That is, in this device, digital signals can be copied from the first channel to the second channel and further to the third channel by crossfading, and digital signals between arbitrary channels can be copied. For this reason, there is no restriction on the channels to which digital signals can be copied, and the degree of freedom of work for the user can be greatly increased.

Thus, according to the above-mentioned apparatus, the channels to be combined can be arbitrarily exchanged, and the degree of freedom of work can be made extremely high.

In the above apparatus, the system of the time base collector 5 to the encoder 13 can also be processed by the time-division serial signal. In that case, the parallel-serial conversion circuit and the encoder are provided on the input side of the time base collector 5. A serial / parallel conversion circuit is provided on the output side of the conversion circuit 13, and the conversion circuit 2 described above is provided.
1, 29, 31, and 39 are unnecessary.

Further, according to the above-mentioned apparatus, even if the number of channels is increased, it is only necessary to add the addresses of the RAMs 22 and 32, and it is possible to easily cope with a desired multi-channel recorder.

[0043]

According to the present invention, the channels to be combined can be arbitrarily exchanged, and the degree of freedom of work can be made extremely high.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a digital multi-channel recorder according to the present invention.

FIG. 2 is a diagram for explaining the operation.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a diagram for explaining a conventional technique.

FIG. 5 is a block diagram of a conventional digital multi-channel recorder.

FIG. 6 is a diagram for explaining the operation.

FIG. 7 is a diagram for explaining the operation.

[Explanation of symbols]

 1 Tape 2 Playback Head 3 Playback and Equalizer Amplifier 4 PLL 5 Time Base Collector 6 Decoder 7 Crossfader 8, 27, 37, 80 Selector 9 Input Terminal 10 AD Conversion Circuit 11 DA Conversion Circuit 12 Output Terminal 13 Encoder 14 Recording Amplifier 15 Recording Head 21, 26, 31, 36 Parallel / serial conversion circuit 22, 32 Random access memory 23, 33 Address counter 24, 34 Keyboard 25, 35 Address setting circuit 28, 38 Write / read control terminal 29, 39 Serial / parallel conversion circuit

Claims (4)

[Claims] 1. A digital signal recorded for each channel of a multi-channel is reproduced, and the reproduced digital signal for each channel is reproduced in a predetermined order in each of the first and second random access memories. Addresses are written, the digital signals written to the addresses of the first and second random access memories are read out in an arbitrary order, and the read digital signals are combined for each channel. A digital multi-channel recorder adapted to record each of the above multi-channels. 2. The digital multi-channel recorder according to claim 1, wherein the reproduced digital signals of the respective channels are parallel-serial-converted in a predetermined order and stored in the first and second random access memories. A digital multi-channel recorder, characterized in that the digital signals written in respective addresses and read out from the first and second random access memories in arbitrary orders are serial-parallel converted and separated for each channel. 3. The digital multi-channel recorder according to claim 1, wherein the synthesis for each of the channels is a crossfade, and the crossfade is performed between any of the channels. Digital multi-channel recorder. 4. The digital multi-channel recorder according to claim 1, further comprising means for replacing the digital signal read from at least one of the first and second random access memories with a digital signal from the outside. Characteristic digital multi-channel recorder.