JP2834277B2 - Digital signal transmission method and circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a digital signal processing device such as a DAT, and more particularly to a digital signal transmission method suitable for connecting to an AD, DA, digital filter and a four-channel system. Circuit.

[Conventional technology]

As shown in FIG. 2 (A), a conventional digital input / output method of AD, DA, digital filter uses, for example, a 16-bit / sample L, R, 2-channel data based on a sampling frequency (hereinafter abbreviated as Fs) signal. Was serially transmitted at 32 Fs (hereinafter, n times Fs signal is abbreviated as nFs). However, in the fields of AD, DA, and digital filters, higher performance has been advanced, and a filter that transmits data at a clock rate of (number of channels x number of bits of 1 sample data) times Fs or more has appeared for higher bit rate and oversampling processing. Was. FIG. 2 (B) is a timing diagram for inputting / outputting 2-channel 2-sample data at 64 Fs and after the Fs signal, based on the Fs signal. This makes it possible to support transmission of a high-bit system in which one sample data has 16 to 20 bits.

Further, for the same reason as described above, a system in which two-channel data is transmitted with the 64 Fs clock and left justified, as shown in FIG. 2C, may appear.

[Problems to be solved by the invention]

The above prior art is not considered in terms of uniformity. When constructing a system corresponding to each of the transmission methods shown in FIGS. 2A to 2C, the transmission clock is set to 32 Fs.
In addition to enabling switching between 64Fs and output, 64Fs transmission requires a process of masking the second half or first half of the 64Fs clock with a gate in response to left justification and left justification, leading to an increase in circuit size and a corresponding transmission system. Therefore, it is necessary to provide a unique configuration on the hardware, thereby complicating the system. Also, in multi-channel transmission where the transmission data exceeds two channels, for example, in a four-channel system, it is necessary to provide a plurality of input and output terminals for the input and output of the main channel and for the input and output of the sub-channel. In the case of inputting / outputting sub-channel data to / from the main channel input / output terminal or inputting / outputting only the signal of the main channel or sub-channel, the channel switching input to AD, DA, digital filter, etc. There is a problem in that it is necessary to change the signal connection, and it is not possible to switch the input and output signals of the main and sub channels with one switch.

A first object of the present invention is to provide a transmission method and a circuit that can avoid the increase in the number of circuits, do not require control for taking measures, and can cope with all the transmission systems.

A second object of the present invention is to provide a multi-channel data transmission system in which only one of each can be used for transmission without increasing the number of input and output terminals, and the output signals of the main channel and sub-channel can be switched without changing the connection. It is an object of the present invention to provide a transmission method and a circuit which can perform the transmission.

[Means for solving the problem]

The first object is to provide feedback wiring between a serial output and a serial input of a shift register circuit for data output, and to make a transmission clock a signal of (number of sample data bits × 2 channels × n) × Fs times. This is achieved by:

Further, the second object is to provide a first output shift register circuit wired in a feedback manner between a serial output and a serial input, a second shift register circuit, and a first shift register circuit controlled by a 4-channel mode selection signal. A signal switching circuit, a second signal controlled by a main sub-channel selection signal, and a third switching circuit controlled by a left and right justification selection signal, wherein the first signal switching circuit includes the first and second signals. 2 while switching the output of the second shift register circuit.
, The second signal switching circuit switches the output of the first and second shift register circuits, and the third signal switching circuit switches the first and second identification signals. And at the same time, switching and outputting the second and first identification signals.
This is achieved by outputting a (4 channels) × Fs signal.

[Action]

It is assumed that the same sample data is serially output n times repeatedly during the "L" or "H" period of the channel identification signal by the first means, and is input as (1 sample data bit number x 2 channels) x Fs signal. (1 sample data bit number × 2 channels ×
When data is transmitted by n) × Fs signal, there is no problem since the same sample data transmitted last remains in the input circuit. Also, if the transmission clock is (number of sample data bits x
Even for an input circuit that is a 2-channel × n) × Fs signal and is assumed to be left-justified or left-justified, the same data is repeatedly output n times in response to the identification signal. It can be transmitted. In addition, the second means (1) repeats the main channel signal n times, (2) repeats the sub channel signal n times, and (3) repeats the main-sub signal in response to the main / sub selection signal and the 4-channel mode selection signal. , And the first and second types of identification signals correspond to the left-justified and left-justified timings, respectively. In the 4-channel mode, each of the first and second identification signals is determined by the main / sub channel selection signal. By alternately outputting the signals, the main channel signal or the sub-channel signal can be switched and output.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, reference numeral 1 denotes an m-bit shift register circuit, in which SI is a serial data input terminal, CK and A are shift clock input terminals, SP and B are serial / parallel switching signal input terminals, and SO is a serial data output terminal. , Pi
And D are input terminals for m-bit parallel data.
In this circuit, the same data is output n times repeatedly when m × n clocks are input to the terminal A in one cycle in which the SO output terminal is fed back to the SI input terminal and the load signal is input from the terminal B. Will be done. For example, if this embodiment is used as a DAT or a CD player,
This will be described with reference to the timing chart of FIG. 3 as 2-channel 16-bit data / 1 sample. FIG. 3A is a timing chart of outputting twice and FIG. 3B is a timing chart of outputting repeatedly four times. Here, MPX is the identification signal of the L and R2 channels, and the cycle is the sampling frequency Fs. (2) is a shift clock, and the period is (1)
The number of sample data bits m × L, the number of R channels 2 × the number of repetitions n) × Fs, that is, when m = 16, n = 2, the Fs is 64 times, and is input to the clock input terminal A in FIG. I do. Also, as shown in FIG. 3 (4), the load signal to be input to FIG. 1B has a timing corresponding to one cycle of the shift clock and such that the change point of the MPX signal is exactly at the center. After the data loaded once at the transition point of the MPX signal is output for 16 bits, the same 16-bit data is further output twice by the feedback loop of FIG. The case where the number of repetitions is n = 4 as shown in FIG. 3B can be similarly realized by making the period of the shift clock proportional. This is because the sample data that is justified and the data that is left justified with respect to the MPX signal are the same, and the left and right justification transmissions as shown in FIGS. 2B and 2C are performed. The result is that both input circuits assumed can be handled. In addition, as shown in FIG.
For input circuits that use signals as clocks, 16
When a shift clock is transmitted at 64 Fs as shown in FIG. 3A, 32-bit data is input to a 16-bit register. The 16-bit data is discarded, and the remaining 16-bit data remains. However, since the data of the previous 16 bits and the data of the subsequent 16 bits are the same, the remaining 16-bit data in the register of the input circuit is L,
The R channel is valid sample data that has been identified. The transmission method shown in FIGS. 2A, 2B, and 2C is performed by the circuit shown in FIG. 1 and the transmission method shown in FIG. Can be applied to all input circuits on the premise of.

When the above embodiment is used for an output circuit of a digital signal processing device such as a CD or a DAT, the A based on various transmission methods is assumed.
It can be connected to a D / DA converter or a digital filter.On the contrary, by using the output circuit of the present embodiment for an AD / DA converter or a digital filter, any digital signal based on the various transmission methods described above can be used. It can be connected to processing circuits and devices.

Next, an input / output circuit and a transmission method of a four-channel system according to one embodiment of the present invention will be described with reference to FIGS. Conventionally, in the case of 4-channel transmission, the main 2
Dedicated input and output terminals are provided for the channel and the sub 2 channel, respectively. The present embodiment is a method and a circuit in which one data input terminal and one data output terminal are used, and two main channels and two sub channels are simultaneously transmitted.

In FIG. 4, reference numerals 7 and 8 denote the same shift register circuit having a read function as in FIG. 1, 2 and 3 denote 2-input and 1-output signal switching circuits, 4 denotes a 4-input and 2-output signal switching circuit, and 5 denotes Latch circuit, 6 is a 7-bit counter, B is a load signal input terminal, C is a serial data output terminal, D is a first channel identification signal output terminal, E is a phase-shifted second channel identification signal output terminal, and F is Shift clock output terminal for data output, G is clock input terminal for counter, M1 ~
M3 is a switching control signal input terminal of the above-mentioned signal switching circuits 2 to 4, H is a parallel data input terminal for a main channel, and I is a parallel data input terminal for a sub-channel.

Counter 6 uses 128Fs as input clock and
_{From 7} , an MPX-1 signal with a period Fs divided by 128 is obtained.
Also, latched by the latch circuit 5 the MPX-1 at the rising edge of the signal with outputs 2Fs signal peripheral 64 minutes from Q _6, obtain MPX-2 signal. The bit Q ₂ is becomes divided-by-two 64Fs signals, along with the shift clock of the shift register 1 and 2 which are output from the terminal F as a shift clock for the output data. Further, the terminal B has 64Fs centered on the changing point of the MPX-1 signal.
A timing signal for one cycle of the signal is input as a load signal.

As described above, the timings of the MPX-1, MPX-2, 64Fs (SCK) signal and the load signal are as shown in FIGS. 5 (1) to (4). Of course, the load signal is a signal that can be generated by decoding the output of the counter 6. Here, by configuring the shift register circuits 7, 8 and the signal switching circuits 2 to 4 with the connections shown in FIG. 4, when the control method of the terminals M1 to M3 is changed, the data output from the terminal C and the The fact that the timing can be as shown in FIGS. 5 (5) to (7) will be described. First, when the main channel data and the sub-channel data of the four-channel signal are simultaneously output from the terminal C (example of FIG. 5 (5)), the 16-bit shift register 8 is used for the main L and R channel output, and If the bit shift register 7 is a sub-L, R channel output register, control is performed such that the terminal M1 selects the B1 input of the signal switching circuit 2 and the terminal M2 selects the B1 of the signal switching circuit 3. I do. This allows the shift clock to
Since this is 64Fs, during the “L” period of MPX-1, first, the register 8 for the subchannel loaded at the falling edge of MPX-1
That is, the sub-channel L data is output in 16 bits, and subsequently, the main channel L data loaded in the register 7 is output. The timing of the rising edge of MPX-1 just after the output of the 32-bit data of two samples is described above. The next main channel R data and subchannel R data are loaded into the registers 7 and 8, and the "H" level of the MPX-1 signal is output. During the period, 32-bit serial data of 16 bits each is output in the order of the sub and main channels.

This is the case where only the L and R data of the main channel is output from the second terminal C (example of FIG. 5 (6)). The terminal M1 of the signal switching circuit 2 is controlled to select the A1 input, and the terminal M2 of the signal switching circuit 3 is controlled to select the B1 input. In this case, the output signal of the output terminal SO is fed back to the input terminal SI of the shift register 8, and the main channel data is repeatedly output twice as described with reference to FIG. Similarly, in the third case, when only the L and R data of the sub-channel is output from the terminal C (FIG. 5 (7)), the shift register 7 is feedback-connected and the input terminal of the signal switching circuit 3 is connected. By controlling M2 and selecting the A1 input, the sub-channel side register 7
Is selected, and the sub-channel data is repeatedly output twice each time. The transmission method assumed by the DA and digital filter connected to the output circuit shown in the present embodiment, the signal processing circuit for four channels, and the like is as follows. , As shown in FIGS. 2 (A) to 2 (C), but with terminals D and E in FIG.
As shown in (2), by providing two MPX-1 signals and two MPX-2 signals, it becomes possible to cope with any of the above-mentioned transmission methods. FIG. 6 shows an embodiment of the present invention in which a 4-channel system is configured using an AD converter presuming left-justified transmission and a DA converter presuming left-justified transmission. In the figure, 10 is a digital signal processing circuit for 4 channels, 11 is a 16-bit shift register circuit for main channel data input, 12 is a 16-bit shift register circuit for sub-channel data input, 13 is a 4-channel signal processing circuit, and 14 is the fourth The output circuit shown in the figure, 20 and 21 are AD conversion circuits on the assumption of left-justified transmission, 22 is a 2-input / 1-output signal switching circuit, 23 and 24 are DA conversion circuits on the assumption of rear-justified transmission, and terminal C ~F terminals C~F same terminal shown in FIG. 4, the terminal K, for example 2Fs cycle of the signal output terminal that is output from the bit Q ₆ in FIG. 4 counter 6, the terminal H is the input terminal of the serial data Yes, register circuits 11 and 12 in the figure
Constitutes an input circuit. Here, the output circuit 14 is the same as that of FIG. 4, and controls the terminal M3 of FIG. 4 so that the D terminal and the E terminal output the MPX-1 shown in FIGS. 5 (1) and (2).
And output the MPXP-2 signal. In this way, the output of the main channel L / R data AD conversion circuit 20 is output as a left-justified transmission based on the MPX-2 signal at the E terminal, as shown in FIG. 7 (4). The A / D conversion circuit 21 for sub-channel L and R data is driven by the MPX-1 signal output from the terminal D, and the MSX-1 signal is left-justified transmission (FIG. 7 (5)). The outputs of both AD conversion circuits are input to the switching circuit 22, the input selection is switched by the Fs2 signal (FIG. 7, (3)), and the serial data input to the terminal H
As shown in FIG. Assuming that the input circuit of the digital signal processing circuit 10 is configured to input, for example, the left-justified sub-channel data and the left-justified main channel data based on the MPX-1 signal (in the opposite case, the AD conversion circuit 20, 21 input MPX-1 and 2
3), or by changing the connections of the E terminal and the D terminal.) The sub-channel data is just input to the sub-channel data input shift register circuit 12, and the main channel data is input to the main shift register circuit 11. Will be entered. that's all,
For example, a method and a circuit for inputting 4-channel data typified by 4-channel recording of a DAT have been described. Next, an output method and operation of 4-channel data as seen when reproducing the same DAT will be described. The operation of the output circuit 14 is as described above. DA conversion circuit used in Fig. 6
Assume that 23 and 24 are based on postscript transmission.

The output circuit 14 controls the terminals M1 to M3 shown in FIG. 4 to output the MPX-1 signal shown in FIG. 5 (1) from the terminal D, and outputs the MPX-1 signal shown in FIG. ) Is output, and the output data shown in FIG. 5 (5) is obtained from the terminal C. At this time, the DA conversion circuit 23 uses the MPX-1 signal output from the D terminal as a reference signal, as shown in FIG.
The R data is DA-converted, and the main L and R channel audio signals are output to an output terminal M. At the same time, the DA conversion circuit 24 uses the MPX-2 signal output from the E terminal as a reference signal, thereby providing a left-justified signal. The sub-channel R and L data are DA-converted, and the sub-L and R channel audio signals can be output to the output terminal S. From the above,
The input / output system enables data transmission for four channels with one input terminal H and one output terminal C. In the control by the above method, the L and R data output of the main channel is output to the output terminal M, and the L and R data of the sub channel is output to the output terminal S.
In a channel device, it is not always necessary to output four channels. Depending on the contents of data to be input (recorded), only the same main channel data is output to output terminals M and S, or only sub-channel data is output. It is also required when outputting. For example, this is the case where the four channels are configured as a multi-recording / reproducing apparatus using two independent L and R stereo signal sources. In this case, rather, the MPX-1, MPX connected to the DA conversion circuits 23, 24
It is more functional to switch the data output simultaneously to the terminals M and S to the main or sub channel by one switch operation without changing the connection of the -2 signal. This embodiment can be realized by controlling the terminals M1 and M2 in FIG. 4 so that the data output from the terminal C is as shown in FIG. 5 (6) or (7). Similarly, in order to output the sub-channel signal to the output terminal M and the main channel signal to the terminal S, the terminal M3 in FIG. 4 is controlled to output the MPX-2 signal from the D terminal and the MPX-signal from the E terminal. 1
The data that is output by the DA conversion circuit 23 after the signal is relatively left-justified are the sub-channel R and L data.
The data that the A conversion circuit 24 is relatively left-justified is the main channel L and R data, and the sub-channel is output from the terminal M, and the main channel signal is output from the terminal S. As described above, the AD conversion circuits 20, 21 and DA
By controlling the input signals of the terminals M1 to M3 linked to the switches without changing the wiring of the conversion circuits 23 and 24, simultaneous main and sub four-channel output or main and sub switching output can be realized.

In the present embodiment, the AD conversion circuit 2 shown in FIG. 6 is used to output the MPX-1 and MPX-2 signals simultaneously and to alternately input and output the main and sub data.
0, 21 and the DA conversion circuits 23, 24, regardless of the transmission method shown in FIGS. 2 (A), 2 (B) and 2 (C), and in any combination. Even if it is used, it can be used by associating the input channel identification signals with each other, that is, by associating with the terminals D and E.

〔The invention's effect〕

According to the present invention, L, R2 channel data can be repeatedly output as the same data a plurality of times on one side of the channel identification signal, so that the DA conversion circuit to be connected, the digital filter, etc. This has the effect of being able to respond regardless of the situation. The implementation circuit can be realized only by providing a feedback loop in the shift register circuit for the number of effective sample data bits, so that there is no increase in the number of circuits and no complicated timing. According to the four-channel data transmission method of the present invention, the main channel L and R data and the sub channel L and R data can be alternately input and output, and the main channel L and R data are repeated and the sub channel L and R data are repeated. It is possible to switch to a repetitive output, and it is possible to freely set the main and sub-channels to be left-justified or left-justified by the two channel identification signals.

As described above, one input and one output terminal can be shared with each other, and it can be used for all DA conversion circuits, digital filters, and four-channel signal processing circuits that assume various transmission methods for left and right justifications, and the connections can be changed. However, there is an effect that three output methods such as main and sub simultaneous output, main channel signal only output, and sub channel signal output can be selected and realized by one switch control.

[Brief description of the drawings]

FIG. 1 is a transmission circuit diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a timing chart of a conventional data transmission method, FIG. 3 is a timing chart showing one embodiment of the present invention, FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. FIG. 6 is a circuit diagram showing still another embodiment of the present invention, and FIG. 7 is a timing chart showing still another embodiment of the present invention. 1,7,8 ... m-bit shift register circuit 2,3,4 ... signal switching circuit MPX, MPX-1, MPX-2 ... channel identification signal SCK ... shift clock signal

Claims (6)

(57) [Claims] 1. A sampling frequency Fs, 2 channels, m
In the transmission of digital data consisting of bits / sample, the frequency of the transmission clock is set to 2 × m × n ×
Fs, one channel data within 1/2 × Fs time
A digital signal transmission method characterized by performing serial transmission repeatedly n times in bit units. 2. An m-bit shift register circuit, comprising:
A channel identification signal generation circuit that repeats “L” and “H” at intervals of time; feeds back a serial output signal of the shift register circuit to a serial input terminal of the shift register circuit; Each time, m bits of digital data are loaded in parallel into the shift register circuit, and serial data is output from a serial output of the shift register circuit using a signal having a frequency of 2 × m × n × Fs as a shift clock. A digital signal transmission circuit. 3. The digital signal transmission circuit according to claim 1,
3. The digital signal transmission circuit according to claim 2, wherein m = 16 and n = 2. 4. A sampling frequency Fs, 4 channels, m
In the transmission of digital data consisting of bits / sample, the digital data of the four channels is divided into a first pair and a second pair, and the frequency of the transmission clock is set to 4 × m.
× Fs, and a channel identification signal that repeats “L” and “H” every 1 / 2Fs is provided. During the “L” period of the channel identification signal, one m-bit data of the first or second pair is “H”
In the period, the other m-bit data of the first or second pair is
A digital signal transmission method characterized in that the signal is output repeatedly. 5. A sampling frequency Fs, 4 channels, m
In the transmission of digital data consisting of bits / samples, a first channel identification signal that repeats "L" and "H" every 1 / 2Fs time and the same period as the first channel identification signal and 1/4 Fs or A second channel identification signal phase-shifted by 3 / 4Fs is provided, and the four-channel digital data is divided into a first pair and a second pair. Period 1
Alternatively, two samples of the second pair data are arranged, and during the "H" period of the first channel identification signal, two samples of the second or first pair data are arranged and transmitted. Transmission method. 6. A digital signal transmission circuit for performing transmission according to the digital signal transmission method according to claim 4 or 5, wherein the first and second m-bit shift register circuits and the first signal are provided. A switching circuit; and a second signal switching circuit for selecting the first pair or the second pair, wherein a serial output signal of the first shift register circuit is connected to a serial input terminal of the first shift register circuit. The first signal switching circuit selects and outputs one of the serial output signals of the first or second shift register circuit, and the output of the first signal switching circuit is the second signal. Is input to the serial input terminal of the shift register circuit of FIG.
Alternatively, one of the serial output signals of the second shift register circuit is selected and output to the output terminal, and the first and second serial output signals are selected.
Wherein the shift register circuit outputs serial data using a signal having a frequency of 4 × m × Fs as a shift clock.