JPH02252173A - Sound digital signal recording and reproducing device - Google Patents

Sound digital signal recording and reproducing device

Info

Publication number
JPH02252173A
JPH02252173A JP7458889A JP7458889A JPH02252173A JP H02252173 A JPH02252173 A JP H02252173A JP 7458889 A JP7458889 A JP 7458889A JP 7458889 A JP7458889 A JP 7458889A JP H02252173 A JPH02252173 A JP H02252173A
Authority
JP
Japan
Prior art keywords
circuit
signal
read
digital signal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7458889A
Other languages
Japanese (ja)
Other versions
JP2789656B2 (en
Inventor
Shigeo Ejima
惠嶋 繁雄
Nobuyoshi Kihara
木原 信義
Shinzo Kashiwagi
柏木 伸造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1074588A priority Critical patent/JP2789656B2/en
Publication of JPH02252173A publication Critical patent/JPH02252173A/en
Application granted granted Critical
Publication of JP2789656B2 publication Critical patent/JP2789656B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To make the tape speed freely variable at a variable reproducing speed and to find a variation point by storing a regenerated sound digital signal in memory circuits, reading it by a variable speed signal, making an address counter up and down and stop and providing a digital interpolation circuit. CONSTITUTION:The sound digital signal of the recording and reproducing device is written as a data in a specified place of the memory circuits 1 and 2 as specified in address by a memory write control circuit 3. And, a clock frequency of a read address counter of the circuits 1 and 2 respectively is controlled by a memory read-out control circuit 4 with the variable speed signal. And, the up-and-down and stop operation of a read address value of the circuits 1 and 2 is performed by the circuit 4 with the variable speed signal, and such an alternate operation is carried out that while the circuit 1 is under the write operation, the circuit 2 is operated for the write, and while the circuit 1 is under the read operation, the write takes place in the circuit 2. Then, the read- out signal from the circuits 1 and 2 is freely varied in speed of the sound digital signal by the interpolation circuit 5 to be inputted with the variable speed signal.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はPCM録音、再生機等の音声デジタル信号の記
録再生装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an audio digital signal recording and reproducing apparatus such as a PCM recording and reproducing machine.

従来の技術 従来において録音、再生装置の記録方法とじては、固定
ヘッドを用いてテープにアナログ信号のまま記録する方
法が一般的であった。この方法で記録された音声信号を
リニアオーディオ信号という。
2. Description of the Related Art In the past, the common recording method for recording and reproducing devices was to record analog signals directly onto a tape using a fixed head. Audio signals recorded using this method are called linear audio signals.

オーディオ偏集を行う場合の偏集点の頭出しは、可変速
再生スピードダイヤルによってテープスピードを自由に
可変させ、テープ上のリニアオーディオ信号の変化点に
よって見つけていた。
When performing audio decentralization, the decentralized point was found by freely varying the tape speed using a variable speed playback speed dial and by looking at the changing points of the linear audio signal on the tape.

一方、音声信号を一旦デシタル信号に変換して、記録す
る方法が、高品質な音声信号の記録再生を可能とするこ
とから、近年性なわれるようになってきた。1986年
6月19日の電子通信学会磁気記録研究会MR−86−
5にも発表されているように、音声信号をデジタル信号
に変換して記録再生する方法が行なわれている。第4図
にこの場合の磁気テープ上の記録信号フォーマットを示
す。
On the other hand, a method of first converting an audio signal into a digital signal and then recording it has become popular in recent years because it enables recording and reproduction of high-quality audio signals. Institute of Electronics and Communication Engineers Magnetic Recording Study Group MR-86- June 19, 1986
5, a method for recording and reproducing audio signals by converting them into digital signals has been used. FIG. 4 shows the recording signal format on the magnetic tape in this case.

PCMオーディオ信号は1フィルド期間中のデジタルオ
ーディオ信号を時間軸圧縮した信号である。
The PCM audio signal is a signal obtained by time-base compressing the digital audio signal during one field period.

発明が解決しようとする課題 しかしながら上記した従来の構成では、テープ2ピード
を変化させたときに、変化点を見つけることができない
という課題を有していた。
Problems to be Solved by the Invention However, the conventional configuration described above has a problem in that it is not possible to find the point of change when changing the tape 2 peed.

本発明は前記の音声デジタル信号を用いた、録音再生装
置の頭出しをリニアオーディオ信号と同様に、可変速再
生スピードダイヤルによってテープヌピードを自由に可
変させ、変化点を見つけるととができる音声デジタル信
号の記録再生装置を提供することを目的とする。
The present invention uses the above-mentioned audio digital signal to locate the beginning of a recording/playback device in the same way as a linear audio signal, and allows the tape nuppedo to be freely varied using a variable speed playback speed dial to find a change point. The purpose of the present invention is to provide a recording/playback device.

課題を解決するための手段 この目的を達成するために本発明の音声デジタル信号の
記録、再生装置は、再生した音声デジタル信号を記録す
るメモリ回路と、このメモリ回路の読み出し、書き込み
を制御する読み出し書き込み制御回路と、可変速再生ス
ピード信号によって音声デジタル信号のメモリ回路より
の読み出しを制御する読み出し制御回路と、前記メモリ
回路より読み出した音声デジタル信号を可変速再生スピ
ード信号によって補間する補間回路とを備えた構成を有
している。
Means for Solving the Problems To achieve this object, the audio digital signal recording and reproducing device of the present invention includes a memory circuit for recording the reproduced audio digital signal, and a readout circuit for controlling reading and writing of the memory circuit. A write control circuit, a read control circuit that controls readout of the audio digital signal from the memory circuit using a variable playback speed signal, and an interpolation circuit that interpolates the audio digital signal read from the memory circuit using the variable playback speed signal. It has the following configuration.

作  用 この構成によって音声デジタル信号をメモリ回路に記録
して、可変速再生速度信号によってメモリ回路の読み出
しを自由に減速及び停止させ、可変速再生速度信号によ
って補間させる事によってリニアオーディオ信号と同様
に変化点を容易に見つけだすことができる。
Function: With this configuration, an audio digital signal is recorded in the memory circuit, the readout of the memory circuit is freely slowed down and stopped by the variable speed playback speed signal, and the reading is interpolated by the variable speed playback speed signal, so that it can be recorded in the same way as a linear audio signal. Change points can be easily found.

実施例 以下本発明の一実施例について、図面を参照しながら説
明する。第1図は本発明の第1の実施例における音声デ
ジタル信号の記録再生装置のブロック図で、1,2はメ
モリ回路で、再生された再生音声デジタル信号を1フレ
ーム毎にメモリされる。このメモリ回路1,2は一般に
ランダムアクセスメモリ(RAM)で構成され、指定さ
れたアドレスにデータをメモリする。3は語込みアドレ
ス指定と書込み許可を制御するメモリ書込み制御回路で
、上記メモリ回路1.2に列してデータをメモリするア
ドレス指示と、メモリ回路1,2に対し、メモリ1,2
のいずれに書込みを許可するかを制御する。4は読出し
アドレス指定と読出し許可を制御するとともに、速度デ
ータで読出しアドレスカウンタとクロック周波数を制御
するメモリ読出し制御回路で、メモリ読出し制御回路4
は、上記メモリ回路1,2にメモリされているデータを
、そのメモリされた順番に読出すように上記メモリ回路
1,2に対してアドレスを指示するとともに、メモリ回
路1.2のいずれに対し、読出しを許可するかどうかを
制御する。5はメモリ回路1.2より読出したデータを
可変速速度信号によって補間を行う。以上のように構成
された音声デジタル信号の記録再生装置について、以下
その動作を説明する。
EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a recording and reproducing apparatus for audio digital signals according to a first embodiment of the present invention. Reference numerals 1 and 2 are memory circuits, in which the reproduced audio digital signals are stored frame by frame. The memory circuits 1 and 2 are generally composed of random access memories (RAMs) and store data at designated addresses. Reference numeral 3 designates a memory write control circuit that controls word address designation and write permission.
Controls which ones are allowed to write. Reference numeral 4 denotes a memory read control circuit that controls read address designation and read permission, and also controls a read address counter and clock frequency using speed data.
Instructs the memory circuits 1 and 2 to read the data stored in the memory circuits 1 and 2 in the order in which they were stored, and also instructs the memory circuits 1 and 2 to read out the data stored in the memory circuits 1 and 2 in the order in which they were stored. , controls whether reading is permitted. 5 interpolates the data read from the memory circuit 1.2 using a variable speed signal. The operation of the audio digital signal recording and reproducing apparatus configured as described above will be described below.

まず、再生された音声デジタル信号を、メモリ書込み制
御回路3でアドレス指定されたメモリ回路1,2の所定
場所にデータとして書込む。可変速速度信号によってメ
モリ読出し制御回路4はメモリ回路1.2の読出しアド
レスカウンタのクロック周波数を制御させる。また可変
速速度信号によってメモリ読出し制御回路4はメモリ回
路12の読出しアドレヌ値のアップ、ダウン、停止を6
・\−・ 行う。メモリ回路1に書込中は、メモリ回路2が読出し
、メモリ回路1に読出し中はメモリ回路2が書込みとい
うように交互に動作する。第2図は本実施例の磁気記録
再生装置の動作を示すもので、以下第2図を用いてその
動作を説明する。1フイルド毎に時間軸圧縮されたPC
Mオーディオ信号について、1フイルド毎に時間軸伸長
を行なった信号を音声デジタル信号入力とする。可変速
速度信号が1倍速時、まず音声デジタル信号入力をメモ
リ回路1,2に書込み、書込み時と同一サンプルクロッ
クでメモリ回路2.1より読出しを行う。
First, the reproduced audio digital signal is written as data to a predetermined location of the memory circuits 1 and 2 addressed by the memory write control circuit 3. The variable speed signal causes the memory read control circuit 4 to control the clock frequency of the read address counter of the memory circuit 1.2. In addition, the memory read control circuit 4 controls up, down, and stop of the read address value of the memory circuit 12 by the variable speed signal.
・\-・ Do. While writing to the memory circuit 1, the memory circuit 2 reads, and while reading to the memory circuit 1, the memory circuit 2 writes, and so on. FIG. 2 shows the operation of the magnetic recording/reproducing apparatus of this embodiment, and the operation will be explained below using FIG. 2. PC with time axis compressed for each field
For the M audio signal, a signal obtained by time axis expansion for each field is used as an audio digital signal input. When the variable speed signal is at 1x speed, the audio digital signal input is first written into the memory circuits 1 and 2, and then read from the memory circuit 2.1 using the same sample clock as when writing.

その場合、補間回路は動作を行なわない。In that case, the interpolator will not operate.

第2図Bに示すように可変速速度信号が%倍速時は、回
転ヘッドにおいて同一トラックを2度走査するためにP
CMオーディオ信号は同一信号が2度づつ出る。よって
音声デジタル信号入力も同一信号が2度づつ出る。その
1フィルドの音声デジタル信号をメモリ回路に1倍速時
と同一サンプルクロックで書込み、メモリ回路の読出し
アドレスカウンタのクロックをサンプルクロックの%り
ロックでメモリ回路より読出す。
As shown in Figure 2B, when the variable speed signal is % double speed, P
As for the CM audio signal, the same signal is output twice. Therefore, the same signal is output twice in the audio digital signal input. The 1-field audio digital signal is written to the memory circuit using the same sample clock as at 1x speed, and the clock of the read address counter of the memory circuit is read out from the memory circuit by locking the sample clock.

第3図に%倍速時の補間回路の動作を示す。上記の場合
、メモリ回路より読出したデータの周期はサンプルクロ
ックの〆になっている為、D/A変換後のローパスフィ
ルりのカットオフ周波数も%にする必要がある。それを
補う為に、可変速速度信号で%倍速のデジタル補間を行
う。
FIG. 3 shows the operation of the interpolation circuit at % double speed. In the above case, since the period of the data read from the memory circuit is the limit of the sample clock, the cutoff frequency of the low-pass fill after D/A conversion must also be set to %. To compensate for this, digital interpolation of % double speed is performed using the variable speed signal.

可変速速度信号が%倍速時は、第3図Cの%倍速時の動
作に示す様に、回転ヘッドにおいて同一トラックを4度
走査するために、PCMオーディオ信号は同一信号が4
度づつ出る。よってデジタル信号も同一信号が4度づつ
出る。その1フイルドの音声デジタル信号をメモリ回路
に1倍速時と同一サンプルクロックで書込み、メモリ回
路の読出しアドレスカウンタのクロックをサンプルクロ
ックの%クロッでメモリ回路より読出す。第4図Cに%
倍速時の補間回路の動作を示す。上記の場合メモリ回路
より読出したデータの周期はサンプルクロックの%にな
っている為にD/A変換後のローバヌフィルタのカット
オフ周波数も%にする必要がある。それを補うために可
変速速度信号%倍速のデジタル補間を行う。可変速速度
信号が〆。
When the variable speed signal is at % double speed, as shown in the operation at % double speed in Figure 3C, the same track is scanned four times in the rotary head, so the PCM audio signal is
It comes out one by one. Therefore, the same digital signal is output four times each. The 1-field audio digital signal is written into the memory circuit using the same sample clock as at 1x speed, and the clock of the read address counter of the memory circuit is read from the memory circuit at % clock of the sample clock. % in Figure 4 C
The operation of the interpolation circuit at double speed is shown. In the above case, since the cycle of data read from the memory circuit is % of the sample clock, the cutoff frequency of the Laubanu filter after D/A conversion must also be %. To compensate for this, digital interpolation of the variable speed signal % double speed is performed. Variable speed speed signal is closed.

%r ’A2+は上記同様にメモリ回路の読出しアドレ
スカウンタのクロックをサンプルクロックの%。
%r'A2+ is the clock of the read address counter of the memory circuit as a percentage of the sampling clock.

に、  1152 に変化させてメモリ回路より続出す
Then, it is changed to 1152 and output from the memory circuit.

またメモリ回路より読出したデータの周期が%。Also, the period of data read from the memory circuit is %.

%、  1/32 になっているためにD/A変換後の
ローパスフィルりのカットオフ周波数モ%、に、 1/
32にする必要があるそれを補うために速度に応じたデ
ジタル補間を行う。また可変速速度ダイヤルを右回シ、
左回シ、停止の状態を可変速速度信号によって伝送し、
メモリ回路の読出しアドレスカウンタを右回シ時はアッ
プ、左回シ時はダウン、停止時はカウント動作を止める
%, 1/32, so the cutoff frequency of low-pass filter after D/A conversion is 1/32.
To compensate for the need to increase the speed to 32, digital interpolation is performed according to the speed. Also, turn the variable speed dial clockwise.
The state of counterclockwise rotation and stop is transmitted by a variable speed signal,
When the read address counter of the memory circuit is turned clockwise, it goes up, when it is turned counterclockwise, it goes down, and when it stops, it stops counting.

以上のように本実施例によれば可変速速度信号によって
メモリ回路の読出しアドレスカウンタのクロックを可変
させ、メモリ回路の読出しアドレスカウンタのアップ、
ダウン、停止を行い、デジタル補間を行うことを設ける
ことにより、リニアオーディオ信号と同様に変化点を見
つけることができる。
As described above, according to this embodiment, the clock of the read address counter of the memory circuit is varied by the variable speed signal, and the clock of the read address counter of the memory circuit is increased.
By providing down, stop, and digital interpolation, changing points can be found in the same way as with linear audio signals.

発明の効果 以上のように本発明は、音声デジタル信号をメモリ回路
に記録して可変速速度信号によってメモリ回路の読出し
アドレスカウンタをアップ、ダウン、停止を行い、デジ
タル補間を設けることにより、リニアオーディオと同様
に可変速再生スピードダイヤルによってテープスピード
を自由に可変させ変化点を見つけることができる優れた
音声デジタル信号の記録再生装置を実現できるものであ
る。
Effects of the Invention As described above, the present invention records an audio digital signal in a memory circuit, and uses a variable speed signal to increment, decrement, and stop the read address counter of the memory circuit, and provides digital interpolation. Similarly, it is possible to realize an excellent audio digital signal recording and reproducing apparatus in which the tape speed can be freely varied and changing points can be found using a variable speed reproduction speed dial.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における音声デジタル信号の
記録再生装置のブロック図、第2図は同動作を示すタイ
ミングチャート、第3図は同波形図、第4図は磁気テー
プの信号トランクを示す記録パターン図である。 1.2・・・・・・メモリ回路、3・・・・・・メモリ
書込み制御回路、4・・・・・・メモリ読出し制御回路
、5・・・・補間回路。
FIG. 1 is a block diagram of an audio digital signal recording and reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart showing the same operation, FIG. 3 is a waveform diagram of the same, and FIG. 4 is a signal trunk of a magnetic tape. FIG. 1.2... Memory circuit, 3... Memory write control circuit, 4... Memory read control circuit, 5... Interpolation circuit.

Claims (1)

【特許請求の範囲】[Claims] 記録媒体に記録された音声デジタル信号を再生し、前記
音声デジタル信号を記録するメモリ回路と、該メモリ回
路の読み出し書き込みを制御する読み出し書き込み制御
回路と、可変速再生スピード信号によって音声デジタル
信号のメモリ回路よりの読み出しを制御する読み出し制
御回路と、前記メモリ回路より読み出した音声デジタル
信号を前記可変速再生スピード信号によって補間する補
間回路とを備えたことを特徴とする音声デジタル信号の
記録再生装置。
a memory circuit for reproducing an audio digital signal recorded on a recording medium and recording the audio digital signal; a read/write control circuit for controlling reading/writing of the memory circuit; A recording and reproducing apparatus for audio digital signals, comprising: a readout control circuit that controls reading from the circuit; and an interpolation circuit that interpolates the audio digital signal read from the memory circuit using the variable reproduction speed signal.
JP1074588A 1989-03-27 1989-03-27 Audio digital signal recording and playback device Expired - Lifetime JP2789656B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1074588A JP2789656B2 (en) 1989-03-27 1989-03-27 Audio digital signal recording and playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1074588A JP2789656B2 (en) 1989-03-27 1989-03-27 Audio digital signal recording and playback device

Publications (2)

Publication Number Publication Date
JPH02252173A true JPH02252173A (en) 1990-10-09
JP2789656B2 JP2789656B2 (en) 1998-08-20

Family

ID=13551472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1074588A Expired - Lifetime JP2789656B2 (en) 1989-03-27 1989-03-27 Audio digital signal recording and playback device

Country Status (1)

Country Link
JP (1) JP2789656B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162203A (en) * 1990-10-26 1992-06-05 Hitachi Ltd Digital-signal recording/reproducing device
WO1994020960A1 (en) * 1993-03-05 1994-09-15 Sony Corporation Digital speech sound reproduction apparatus and digital speech sound edition apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223075A (en) * 1984-04-18 1985-11-07 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing device
JPS63166088A (en) * 1986-12-26 1988-07-09 Mitsubishi Electric Corp Editing device for pcm signal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223075A (en) * 1984-04-18 1985-11-07 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing device
JPS63166088A (en) * 1986-12-26 1988-07-09 Mitsubishi Electric Corp Editing device for pcm signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162203A (en) * 1990-10-26 1992-06-05 Hitachi Ltd Digital-signal recording/reproducing device
WO1994020960A1 (en) * 1993-03-05 1994-09-15 Sony Corporation Digital speech sound reproduction apparatus and digital speech sound edition apparatus
CN1072827C (en) * 1993-03-05 2001-10-10 索尼公司 Digital speech sound reproduction apparatus and digital speech sound edition apparatus

Also Published As

Publication number Publication date
JP2789656B2 (en) 1998-08-20

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