JPH04339361A - Digital recording and reproducing device - Google Patents

Abstract

PURPOSE:To perform recording and reproducing at twice or more recording and reproducing rate by utilizing an LSI operating at a data transmission rate of an existing LSI. CONSTITUTION:When recording is performed at a twice recording and reproducing rate in a so-called R-DAT standard mode, an output from a digital signal processing circuit 10 is converted into that at twice rate in a compression conversion circuit 11 and passed to a recording amplifier 12, and recorded in a magnetic tape 14 via a rotating head 13. At the time of reproduction, the signal is passed from a recording medium to a expansion conversion circuit 17 via the rotating head 15 and a reproducing amplifier 16 and converted into the signal at half rate. The obtained signal from the expansion conversion circuit 17 is processed in PCM, ATF signal detection parts 18 and outputted to output terminals 19 and 20.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording and reproducing apparatus such as a so-called digital audio tape recorder.

0002

2. Description of the Related Art A rotary head type digital audio tape recorder (so-called R-DAT) has been commercialized as a consumer digital audio recording and reproducing device. Since this so-called R-DAT is manufactured as a system capable of supporting a plurality of sampling frequencies, it has various system standards.

Among these various system standards, R-DAT
The standard drum specification uses a φ30 drum. This φ30 drum has a tape wrapping angle of 9
At 0°, recording and reproduction are performed intermittently by two heads (A and B channels).

For example, this will be explained with reference to a timing chart shown in FIG. The switching signal SWP (Fig. 5 (D)), which is one of the control signals that corresponds to the rotational phase of this φ30 drum, switches each head according to the rotation of the drum. For example, when it is at "L" level, The switching signal “H” is sent to the head of the A channel.
" level, the B channel heads are switched to each other.Next, the REPB signal (FIG. 5(C)) indicates a recording/reproduction control signal, and recording or reproduction is performed at half the cycle of the above switching signal. That is, recording (Rec) is performed during the "H" level period of the REPB signal, which is the recording/reproduction control signal, and reproduction (PB) is performed during the "L" level period.

When recording, since the drum wraps the tape at a 90° angle, recording of each channel is performed on the drum 1.
Recording is performed during a period of 1/4 (or 90°) of rotation (360°). Since this drum has two rotating heads facing each other (180°), the recording start phases of each channel are shifted by 180° from each other, and the recording signal with a 180° cycle as shown in Fig. 5(A) Become.

[0006] When performing playback, the wrap angle is 90° as in the above-mentioned recording, so each channel is played back during a period of 1/4 (or 90°) of one rotation (360°) of the drum. . This drum has two rotating heads facing each other (1
80°), the phases of the reproduction start of each channel are shifted from each other by 180°, resulting in a reproduction signal with a period of 180° as shown in FIG. 5(B). Note that the reproduction phase of each channel is set to have a deviation of, for example, 90° from the recording phase of each channel.

As mentioned above, at this wrap angle of 90°,
In a φ30 drum equipped with two rotating heads, the recording (or reproducing) time is shortened due to the intermittent recording (or reproducing) operation as shown in FIG. 5(A) (or (B)). It is 1/2. Therefore,
The instantaneous recording/reproducing rate during the period in which each channel is actually being recorded or reproduced is twice the average recording/reproducing rate including the period in which no recording or reproduction is performed.

Among the various modes of the so-called R-DAT, for example, the standards regarding the standard mode are as follows. In this standard mode,
As audio PCM data, the number of channels is 2C.
H, the standard is that the sampling frequency is 48 kHz and the number of quantization bits is 16 bits. This standard mode is 4
It is also called 8k-mode. Therefore, the transmission rate (data transmission rate) of audio PCM data of this so-called R-DAT is 1.536 Mbit/sec. Next, when error correction and synchronization signals are added to this audio PCM data, it becomes 2.4576 Mbit/sec. This 2
．． The data transmission rate of 4576 Mbit/s is 8/1
By performing 0 conversion modulation, it becomes 3.072 Mbit/sec. Furthermore, in the recording format on tape,
One track consists of 196 blocks of main area and sub area, and in this one track, main data including audio PCM data is divided into one block of main area.
Since the data is recorded in 28 blocks, the recording rate of all data is 4.704 Mbit/sec.

Here, as mentioned above, the standard drum of φ30 has a rotation rate of 90° per 180° of head rotation (1
/2), it is necessary to double the instantaneous recording and reproducing rate, and this instantaneous recording and reproducing rate becomes 9.408 Mbit/sec. The drum rotation speed at this time is (200/6) Hz.

On the other hand, a drum of φ15 is sometimes used. For this φ15 drum, the drum rotation speed is φ30
(200/6) Hz, the tape wrapping angle (wrap angle) is 180°, and the rotating head 2
Recording and playback is performed using the Therefore, for every 180° of head rotation, recording or playback is performed for the same 180°, so this data transmission rate is the original 4.704M
You can leave it as bits/second. FIG. 5 shows a block diagram of a recording system and a reproducing system using these drums of φ30 and φ15. The input signal is supplied from a digital signal processing circuit 51 to a recording amplifier 52, and is recorded on a magnetic tape 54, which is a recording medium, via a rotary head 53. Also, magnetic tape 5
4 is sent to a reproducing amplifier 56 via a rotary head 55. The reproduction signal output from the reproduction amplifier 56 is supplied to a PCM, ATF (automatic track following) signal detection section 57. This detection section 5
7 outputs pilot signals and RF detection signals through terminals 58 and 5.
9, respectively.

[0011] In the digital recording and reproducing apparatus, data transmission is performed at the recording and reproducing rate as described above. Currently, it is desired to further increase the recording and reproducing rate. In the audio field, there is little need for such speed increases, such as double speed dubbing, but the above functions are desired in data streamers for computer backup memory and digital audio tape recorders as analog data recorders. There is.

0012

[Problems to be Solved by the Invention] As mentioned above, when trying to further improve the recording and reproducing rate of so-called R-DAT, it is necessary to increase the drum rotation speed and speed up the tape feed at the same rate, thereby improving the track pitch, etc. It is possible to improve the recording and reproducing rate while ensuring the standards of the tape recording formats included. If the rotational speed of a φ15 drum is doubled to (400/6) Hz, the recording/reproduction rate on the magnetic tape, which is a recording medium, will be 9.408 Mbit/sec. This is the instantaneous recording and reproducing rate of a φ30 drum. From this, in this case, the current L
This can be easily realized using SI.

However, when attempting to double the speed using this φ30 drum, the instantaneous recording and reproducing rate is twice the recording and reproducing rate of 9.408 Mbit/s, which is 18
．． This is 816 Mbit/sec. This recording/reproduction rate cannot be easily realized because current LSI modulation/demodulation circuits, PLLs, etc. are not compatible with this rate. That is,
It is very difficult to manufacture an LSI that can support this double speed increase immediately due to cost and technical aspects.

In view of the above-mentioned circumstances, the present invention adds a circuit for compressing and converting the recording signal and a circuit for decompressing and converting the reproduced signal to each of the recording system and the reproduction system, thereby increasing the data transmission rate in the signal processing means. It is an object of the present invention to provide a digital recording and reproducing apparatus that can perform recording and reproducing on a recording medium at a high recording and reproducing rate even at an average transmission rate.

[0015]

[Means for Solving the Problems] A digital recording and reproducing apparatus according to the present invention includes a compression conversion means for time-base compressing an input signal supplied from a digital signal processing circuit to increase a data transmission rate; a recording amplifier for amplifying the output signal of the recording amplifier, a recording head for recording the signal from the recording amplifier onto a recording medium, a playback head for reproducing the signal recorded on the recording medium, and a recording head for reproducing the signal recorded on the recording medium; The above-mentioned problem is solved by providing a reproducing amplifier for amplification and an expansion converting means for time-axis expanding the signal from the reproducing amplifier width means and returning it to the data transmission rate of the input signal.

[0016]

[Operation] The digital recording/reproducing device according to the present invention compresses an input signal at the data transmission rate of the currently used LSI and records it on a recording medium, and when reproducing a reproduced compressed signal read from the recording medium. It is expanded and reproduced at the data transmission rate of the input signal.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. An embodiment of a digital recording/reproducing apparatus according to the present invention will be described with reference to the block diagram of FIG.

First, in the 1x standard mode as described above, the data transmission rate (data transmission rate) of audio PCM data is 1.536 Mbit/sec. When error correction and synchronization signals are added to this signal, the data transmission rate becomes 2.4576 Mbit/sec, and further becomes 3.072 Mbit/sec by modulation of 8/10 conversion. Next, since one track has 196 blocks and digital data is recorded in 128 blocks of the main area, the recording/reproduction rate (average rate) of all data on the tape is 4.704 Mbit/sec. Therefore, when recording and reproducing at twice the above-mentioned recording and reproducing rate (average rate), the recording and reproducing rate of all data on this tape is twice as high as 9.408 Mbit/sec.

The recording signal having the average recording/reproducing rate is supplied from the digital signal processing circuit 10 to a compression converter 11 which is a compression conversion means for compressing the time axis and increasing the data transmission rate. The recording signal having this average recording/reproducing rate is converted by this compression converter 11 to a recording/reproducing rate twice as high as 18.816 Mbit/sec.

This time-base compressed data is supplied to a recording amplifier 12 which is a recording amplifier that amplifies the output signal from the compression conversion means. This signal is sent to the rotary head 1, which is a recording head that records the signal from the recording amplifier onto the recording medium.
3 to a magnetic tape 14 which is a recording medium. Furthermore, the data recorded on this magnetic tape 14 is
The signal is sent via a rotary head 15, which is a reproducing head that reproduces the signal recorded on the recording medium, to a reproducing amplifier 16, which is a reproducing amplifier that amplifies the output signal from the reproducing head. The output signal from the reproducing amplifier 16 has a recording/reproducing rate of 18.816 Mbit/sec. The expansion converter 17 is an expansion converter that expands the time axis of the signal from this reproduction amplifier and returns it to the data transmission rate of the input signal.
By releasing the time axis compression, the recording/reproducing rate (average rate) of all data on the twice as large tape is returned to 9.408 Mbit/sec.

This expansion converter 17 expands and converts the supplied signal in an analog manner, so it includes an A/D converter 17a,
A memory circuit section 17b and a D/A converter 17c are provided. Through these circuits, the reproduced signal converted to the data transmission rate of the input signal at the time of recording is transmitted to the PCM, which is a signal processing means for digital signal processing.
The signal is supplied to the ATF signal detection section 18. This detection section 18 outputs a pilot signal and an RF detection signal to output terminals 19 and 20, respectively. By adding the compression converter 11 to the recording system and the decompression converter 17 for decompressing and converting the compressed and recorded data to the reproduction system, it is possible to record and reproduce data that can be processed by the current LSI using the current LSI. rate(
In other words, digital recording and reproduction can be performed in correspondence with a recording and reproduction rate exceeding 9.408 Mbit/sec.

The principle of compressing and expanding the time axis using the current LSI will be explained with reference to FIG.

As mentioned above, the recording and reproducing rate (average rate) of all data on the tape in the standard mode (1x speed) is 4.704 Mbit/sec. When recording and reproducing at twice the above recording and reproducing rate (average rate), the recording and reproducing rate of all data on this tape is twice as high as 9.40.
This is 8 Mbit/sec. A recording signal having this recording/reproduction rate is output from the digital signal processing circuit 10 shown in FIG. 1 to the compression conversion circuit 11.

This digital signal processing circuit 10 is shown in FIG.
As shown in (A), recording signals are supplied continuously (180 degrees each) corresponding to each channel, and the recording/reproduction rate is 9.408 Mbit/
This is an LSI that can process signals up to seconds. The recording compression signal shown in FIG. 2(B) corresponds to the recording of the recording signal (FIG. 2(A)) corresponding to the case where one track corresponds to one block and the supplied recording signal is compressed by dividing it into blocks. It compresses the time in half. This drum is (400/6)H
The switching signal SWP, which is a control signal, and the ×2REPB signal, which is a recording and reproducing control signal, are controlled at double speed in accordance with the above rotation (see Fig. (See 2(C) and (F)). The input signal of each channel is controlled according to the level of the switching signal SWP. When the level of the switching signal SWP is “L”, it is connected to the A channel, while “H”
"The level is controlled so that it becomes the B channel (see Figure 2 (F)). At this time, the instantaneous recording and playback rate of each channel is twice the recording and playback rate that current LSIs can support. The recording compression signal output from the compression converter 11 is sent to the rotary head 13 via the recording amplifier 12. The information is recorded on a magnetic tape 14 which is a medium.

Similarly, during reproduction, data compressed and recorded on the magnetic tape 14, which is a recording medium, is taken out via the rotary head 15 and supplied to the reproduction amplifier 16. This reproduced compressed signal is input to the expansion converter 17. This playback compressed signal indicates the instantaneous recording and playback rate. This instantaneous recording/reproducing rate is 18.816 Mbit/sec.

This expansion converter 17 extracts the recording compression signal during the period in which the level of the ×2REPB signal, which is the recording/reproduction control signal, is "L" (see FIG. 2(D)).
)reference). That is, in this decompression converter 17, an operation opposite to that of the compression converter 11 described above is performed, and at the same time the regenerated compressed signal is taken out via the rotary head 15 and the regenerative amplifier 16, the rate is reduced to 1/2. The time axis is expanded. As a result, as shown in Fig. 2(E), the playback signal is made to correspond to each channel continuously (in 180° increments), and at a recording and playback rate of 9.408 Mbit/s, which is the rate that current LSIs can support. converted. During playback, the A channel and B channel are alternately and continuously outputted as playback signals. This reproduced signal is passed through an analog equalizer, PLL, etc. to a digital signal processing LSI, P.
CM and ATF are supplied to the detection unit 18.

The above is the timing relationship of compression and expansion conversion used in the digital recording/reproducing apparatus according to the present invention. In this method, for example, the winding angle (wrap angle) of the tape used during recording is 90°, and the φ
This is done for 30 drums.

On the other hand, the φ15 drum can handle a conversion rate twice as high as 9.408 Mbits/sec, which allows the current LSI to operate even if the recording/reproducing rate is doubled as described above.

Next, a method of converting the recording/reproduction rate by compression or expansion using the timing described above will be explained. As described above, the recording signal in the recording system digital signal processing circuit 10 is processed and output at 9.408 Mbit/sec, which is twice the recording/reproduction rate of all data on the tape. Therefore, the compression conversion circuit 11
The required RAM capacity is 7. If you import one track's worth of data, the time required to read one track is 7.
Since it is 5ms, 9.408MHz x 7.5ms = 7
0560 bits (=1 field) are required. However, in this compression conversion circuit 11, the recording signal is converted to an average recording/reproducing rate (4.7
The rate is converted to 18.816 Mbit/sec, which is four times the rate of 0.04 Mbit/sec), and output. Since the output signal from the compression conversion circuit 11 is read out at twice the rate of the input signal, if reading is started when half of the writing to the RAM is completed, the required RAM capacity is:
Memory capacity for half a field of one track (35.28
k bits = 4410 words). In this way, in the compression conversion circuit 11, the memory sequentially writes data for one track into the memory, and
This is because when half of the track has been written, data is sequentially read out at a double speed rate from the start address of the memory where it has already been written while continuing writing. In this way, the compression conversion circuit 11 converts the rate of the recording signal into a recording compressed signal, and converts the rate of the recording signal into a recording compressed signal.
I am sending it to

In addition, in the reproduction system, according to the basic block circuit diagram described above, the reproduction compressed signal from the reproduction amplifier 16 (the recording and reproduction rate is 4 times higher than the average recording and reproduction rate at 1x speed in the standard mode). 18.816 Mbit/
seconds) is supplied to the decompression converter 17. This reproduced compressed signal is written into the memory circuit section 17b via the A/D converter 17a in the expansion converter 17. By the way, when the reproduced compressed signal is supplied at an instantaneous recording/reproducing rate of 18.816 Mbit/sec, the waveform when viewed as a repetition period has a maximum frequency of 9.408 MHz. In this case, it is known from Nyquist's sampling theorem that the sampling frequency of the A/D converter 17a etc. needs to be twice as high as 18.816 MHz or more. However, in the actual circuit configuration, LPFs are placed before and after the A/D converter 17a, etc.
The digital waveform generated by PF causes phase rotation, etc. In order to keep this digital waveform linear in terms of phase, a good error rate can be obtained by setting the lower limit sampling frequency at 27 to 28 MHz when taking into account this phase rotation and the like.

[0031] The data A/D converted at this sampling frequency is sequentially written to the memory. At the same time, this data is read from the top address of the memory at a frequency that is half the sampling frequency, thereby reducing the data transmission rate to 1/2. In other words, this memory circuit section 17
The recording and reproducing rate of the data read from b is the recording and reproducing rate on the writing side (18.816 Mbit/
It is 9.408 Mbit/sec, which is half of Writing to the memory is completed in 1/4 of the time of one revolution of the drum, but since the rate of reading is set to 1/2, it is completed in the time of 1/2 of one revolution of the drum.

The memory used in this reproduction system is an A/D
Although it varies depending on the sampling frequency of the converter, a capacity that can write half of the data capacity of one track is required. For example, when decompressing and converting 8-bit A/D converted data at the sampling frequency of 28 MHz using two memories, the required RAM capacity per memory is 2.
8MHz x 8 bits x 7.5ms/2/2 = 42000
0 bit = 52.5k words are required. However, the number of quantization bits of the A/D converter required for sufficient accuracy is
A minimum of 6 bits is required. The output from the expansion converter 17 that has been expanded and converted in this manner is supplied to a PCM and ATF signal detection section 18.

Note that the charge-coupled device CCD can convert digital information into analog information and handle it as it is due to the nature of the device, so a D/A converter is not necessary in this case.

Based on the method described above, a block circuit section for compression conversion in the recording system and a block circuit section for expansion conversion in the reproduction system are shown in FIGS. 3 and 4, respectively. The compression conversion block circuit section in the recording system shown in FIG. 3 receives the recording signal, clock CLK1, clock CLK
0 and switching signals, which are control signals, are input.

First, a recording signal (average rate is 9.408 Mbits/sec, which is the double speed) is input to the shift register 23 via the input terminal 21, and is input to the shift register 23 via the input terminal 22 at the double speed average rate. According frequency 9.408M
Hz is input to the shift register 23 as the clock CLK1. In addition, the frequency 18.8 corresponding to a rate that is further twice the above-mentioned double speed average rate is input via the input terminal 26.
16MHz shift register 27 and address generator 29
The clock CLK0 is input to the clock CLK0. At least three types of switching signals, a REPB signal and a PiPc signal, which are recording/reproduction control signals, are input to the address generator 29 in parallel. Based on these various signals and the clock CLK0, the address generator 29 supplies control signals for controlling each circuit as described above. The shift register 23 to which the recording signal is input converts the serial data into 8-bit parallel data in order to write it into the static RAM 25 via the enable buffer 24. When the signal supplied from the address generator 29 to the write enable terminal WE is at "L" level, 8-bit parallel data is written. Also, this static RA
The M25 writes data in response to an address signal at a slow timing of 1/8 of the clock CLK1 via an input terminal A connected to an address bus composed of 13 bits from the address generator 29.

In addition to the above control signals, the address generator 2
Reference numeral 9 supplies a load signal for controlling data loading into the shift register 27, and an enable signal indicating whether the final output buffer 30 of the conversion rate circuit in this recording system is in an operating state. Further, the address generator 29 generates a double-speed recording/reproduction control signal ×2RE.
Outputs PB signal and ×2PiPc signal. The data written in the memory of the static RAM 25 is sequentially written from the first address to 1/1 of the write cycle during a period other than when the signal supplied to the write enable terminal WE is active.
8-bit data is supplied to the shift register 27 using the second cycle as a read cycle.

When the load signal supplied from the address generator 29 is at the "L" level, the shift register 27 loads 8-bit parallel data and outputs the frequency 18.
The serial data is shifted by a clock CLK0 of 816 MHz and sent to the enabled buffer 30 as a recording compression signal at a rate four times the average recording/reproducing rate in the standard mode (1x speed). The enable buffer 30 outputs this recording compression signal to the output terminal 31 when the level of the enable terminal is "L". The static RAM 25 used here has a RAM capacity of 70 per field.
Although 560 bits are required, the read address can be halved by reading at twice the rate, so if there are 35,280 bits or more, the capacity is satisfied. Therefore, a 64k bit memory chip is used as the actual RAM. Further, the first address is calculated using the capacity in which the last address of the addresses displayed in 13 bits is all "1" as one unit, and data corresponding to the address is sequentially written. Read data starts to be read at twice the rate when half of the total write data has been written. In other words, this read address is supplied from the address generator and requires only half the address, and this read address corresponds to the write address and becomes the same.

On the other hand, the expansion/conversion circuit section in the reproduction system will be explained with reference to FIG. Memory during playback is A
As mentioned above, it changes depending on the sampling frequency of the /D converter. Therefore, it is conceivable that the configurations of the memory circuit units used may vary widely. A reproduced compressed signal is input via the input terminal 40. This regenerated compressed signal is applied to L, which is a pre-filter of the A/D converter 42.
Send to PF41. Here, LPF41 has a passband of 14M
It is composed of (7th order + 2nd order phase shifter) of Hz. This reproduced compressed signal is input to the A/D converter 42. The clock generator 48 is a crystal oscillator 49 with a frequency of 28.6 MHz.
have. The clock generator 48 has a frequency of 28.
6 MHz is supplied as the sampling frequency of the A/D converter 42. This A/D converted signal is output in 8 bits. The 8-bit data output from this A/D converter 42 is sent to a memory forming a memory circuit section.

If a dynamic RAM is used in which the cycle time of the memory operation is longer than the time required for the output of the A/D converter 42, the data may be accessed alternately one clock at a time supplied to the memory. In order to guarantee the required time, it is necessary to configure two sets of memories. The memories 43 and 44 shown in FIG. 4 correspond to this example. At this time, the required RAM capacity per set is 28
．． 6MHz x 8 bits x 3.75ms/2 = 42900
A capacity of 0 bits or more is required. In the expansion/conversion circuit section of FIG. 4, a total of four 1M bit FIFO dynamic RAMs are used. This 1M bit FIF
Since O's dynamic RAM has only 4 data bits, two of the above memories are arranged in parallel so that it can handle 8-bit data. That is,
The memories 43 and 44 in FIG. 4 each represent a set of two 1M bit dynamic RAMs. The 8-bit signal supplied from this A/D converter 42 is transmitted to input terminals D of the dynamic RAMs 43 and 44.
is supplied to i. This dynamic RAM 43 is supplied with a 14 MHz clock from a clock generator 48 to take in data. Similarly, dynamic RA
M43 also receives the above dynamic R from the clock generator 48.
A 14 MHz clock whose phase is delayed by half compared to the 14 MHz clock supplied to AM43 is supplied to take in data.

The clock generator 48 also supplies an address reset signal to the dynamic RAMs 43 and 44. The data output from the 1M bit FIFO dynamic RAMs 43 and 44 is performed when the output enable signal OE supplied from the clock generator 48 is "L".
" level, and simultaneously outputs from the output terminal DO in accordance with the condition of the read clock gate supplied from the clock generator 48.

Although not shown in the figure, since the memories 43 and 44 are accessed alternately, the read clock gate conditions for the memories 43 and 44 are as follows: is inverted. Dynamic R of this 1M bit FIFO
The two AMs 43 and 44 alternately access and retrieve 8-bit data and send it to the input terminal D of the D flip-flop 45. This D flip-flop 45 is supplied with a clock having a frequency of 14.3 MHz from the clock generator 48 and holds data. This D flip-flop 45 switches from the output terminal Q to the D flip-flop at the rising edge of the next clock.
/A converter 46 to output data. This D/A converter 46 has a frequency of 14 supplied from a clock generator 48.
．． Converts to analog signal using 3MHz clock.

In this way, the analog signal is sampled at half the frequency of the instantaneous recording/reproduction rate of the reproduced compressed signal, so that the reproduced compressed signal is expanded twice on the time axis. Ru. As a result, the analog signal becomes a reproduction signal at the data transmission rate of the input signal at the time of recording. The output signal from the D/A converter 46 is sent to an LPF 47 which is a post filter. Here, the LPF 47 has a pass band of 7 MHz (5th order). This signal outputted via this LPF 47 becomes a high frequency signal with a band limited to 7 MHz. This high frequency signal is outputted as a reproduction signal via the output terminal 50.

With the above configuration, recording and reproduction can be performed at a high recording and reproduction rate even when using an LSI that has only a normal data transmission rate at which existing signal processing LSIs can operate.

[0044] Developing a new LSI that performs signal processing at a recording and reproducing rate twice the data transmission rate of existing signal processing LSIs has been difficult in terms of cost and technology. However, this digital recording/playback device adds compression and expansion conversion circuits to the time axis.
Recording and playback can be performed at a recording and playback rate that is twice the data transmission rate using an existing LSI without developing a new LSI that is compatible with double the recording and playback rate.

It should be noted that the present invention is not limited to the above-described embodiments; for example, in order to cope with a further increase in the instantaneous recording and reproducing rate, the circuit of the data transmission rate (average recording and reproducing rate) can be modified. The same signal processing circuits may be added to the recording system and the reproduction system, one set at a time, depending on the rate magnification (see FIG. 1). Additional circuits corresponding to this magnification are shown by broken lines. In the recording system, a digital signal processing circuit 61 is added to send recording signals at an average recording/reproduction rate to the compression converter 11. In the reproduction system, the reproduction signal converted to the average recording and reproduction rate from the memory circuit section 17b in the decompression converter 17 is transferred to the same D/A converter as the D/A converter 17c in the same converter 17. The circuit is configured such that the reproduced signal is sent to the PCM/ATF detection section 62 and further sent to the added PCM/ATF detection section 63, and the signal is outputted via the output terminals 64 and 65. Furthermore, if the above-mentioned compression converter 11 and expansion converter 17 are also made to correspond to a rate conversion magnification of 4 times, this digital recording/playback device can record or play back at an instantaneous recording/playback rate of 4 times. Become.

In this way, even for an instantaneous recording/reproducing rate (or transmission rate) that is more than three times the recording/reproducing rate of the LSI that performs signal processing,
By adding each signal processing circuit section of the recording system and playback system according to the magnification and performing time axis compression and time axis expansion of rate conversion at the average recording and playback rate, recording and playback can be performed at the required recording and playback rate. can do.

[0047]

As is clear from the above description, the digital recording and reproducing apparatus of the present invention comprises compression conversion means for compressing an input signal, and recording signal amplification means for amplifying the recorded signal from the compression conversion means. , digital recording means for digitally recording the signal from the signal amplifying means on a recording medium, digital recording and reproducing means for extracting the digital record recorded on the recording medium as a reproduction signal, and from the digital recording and reproducing means. By providing reproduced signal amplification means for amplifying the signal and expansion conversion means for expanding the signal from the reproduced signal amplification means, it is possible to operate at the data transmission rate (average transmission rate) possessed by existing LSIs. Even if an LSI is used, recording and playback can be performed at a recording and playback rate that is more than twice as high. Further, by the means described above, a high recording/reproducing system can be realized without waiting for the development of an LSI having a high recording/reproducing rate.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a digital recording/reproducing device according to the present invention.

[Figure 2] Timing chart when a φ30 drum is used in the present invention

[Figure 3] Compression conversion rate circuit diagram of the recording system of a digital recording/playback device

[Figure 4] Expansion conversion rate circuit diagram of the playback system of a digital recording and playback device

[Figure 5] Timing chart when using a conventional φ30 drum

[Fig. 6] Block circuit diagram of a conventional digital recording/reproducing device

[Explanation of symbols]

11...Compression converter 12... Recording amplifier 13, 15... Rotating head 16・・・・・・Regenerative amplifier 17......Extension converter

Claims (1)

[Claims] 1. Compression conversion means for time-base compressing an input signal supplied from a digital signal processing circuit to increase a data transmission rate; a recording amplifier for amplifying an output signal from the compression conversion means; a recording head that records the signal recorded on the recording medium, a playback head that plays back the signal recorded on the recording medium, a playback amplifier that amplifies the output signal from the playback head, and a signal from the playback amplifier that converts the signal from the playback amplifier over time. 1. A digital recording/reproducing apparatus comprising: an expansion/conversion means for axially expanding the input signal and returning the data transmission rate to the data transmission rate of the input signal.