JPH0294175A - Picture recording and reproducing device - Google Patents

Abstract

PURPOSE:To perform excellent synchronous reproduction by delaying the recording operations of digital sound signals on a recording medium until digital video signals of one screen quantity are recorded on the recording medium. CONSTITUTION:An address generation circuit 35 outputs a write address for storing digital sound signals latched by a shift register 29 to a memory 31 by performing increment at every sampling clock period. The circuit 35 along outputs a value which is obtained by subtracting a prescribed numeral 'N' from the write address to the memory 31 as the readout address of the digital sound signals outputted to a shift register 32. Therefore, digital sound signals supplied to an input terminal 28 are delayed and obtained from an output terminal 34. When the delay time is correlated with the time required for recording digital video signals of one screen quantity in the sub-code data area of a tape, the time lag between a picture and sounds at the time of reproduction can be compensated. Therefore, synchronous reproduction becomes possible.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to an image recording and reproducing device, and in particular, to a digital audio tape recorder or the like for recording and reproducing still image information in its subcode data area. Regarding what is suitable for the case.

(Prior Art) As is well known, in the field of audio equipment, information signals such as audio signals are subjected to RCM (pulse code modulation) in order to record and reproduce information with as high density and high fidelity as possible.
2. Description of the Related Art Digital recording and reproducing systems that use technology to convert data into digitized data, record it on a recording medium, and reproduce it are becoming widespread.

Among these, those that use magnetic tape as a recording medium are called digital audio chip recorders.
At present, the mainstream is a rotary head type in which a tape is wound around a cylindrical drum that is provided so that the head rotates along the circumference to perform helical scanning.

By the way, such a digital audio TV recorder has a main data area in which digitized audio signals are recorded in one helical track formed on the tape, and various controls such as song number and address information. A subcode data area in which information is recorded is provided. Recently, attempts have been made to record still image information in this subcode data area so that users can enjoy audio playback without looking at still images.

FIG. 2 shows such a conventional digital audio recorder. That is, numeral 11 in the figure is a video input terminal to which an analog video signal is supplied. The analog video signal supplied to this video input terminal 11 is connected to the A/D
After being supplied to the (analog/digital) conversion circuit 12 and converted into a digital video signal, it is output to the memory control circuit 13.

Further, the analog video signal supplied to the video input terminal 11 is supplied to the signal generation circuit 14. This signal generation circuit 14 extracts vertical synchronization signals, subcarriers, etc. from the input analog video signal, generates reset signals, system clocks, etc. necessary for operating the system from these extracted data, and generates the above-mentioned It is output to the memory control circuit 13.

Then, the memory control circuit 13 generates an address signal for the memory 15 based on the system clock output from the signal generation circuit 14, and a digital video signal output from the A/D conversion circuit 12 in synchronization with the reset signal. Memorize it on January 5th. In addition, memory 15
has a storage capacity of 1M bits and can store digital video signals for one screen.

In this case, the switches 1 perform switching operations in conjunction with each other.
6 and 17 are in the switching state shown in FIG. memory 18 having
It is also remembered.

When one screen worth of digital video signals is stored in each memory 1518, the switch 1617 is reversed to the opposite state as shown. Therefore, based on the address signal output from the address generation circuit 19, the digital video signals stored in the memory 18 are sequentially read out to the microprocessor 20 at regular intervals. Then, the microprocessor 20 controls the recording/reproducing circuit 21 of the digital audio tape recorder to record the digital video signal read from the memory 18 into the subcode data area.

Further, reference numeral 22 in FIG. 2 is an audio input terminal to which an analog audio signal is supplied. The analog audio signal supplied to the audio input terminal 22 is supplied to the A/D conversion circuit 23 and converted into a digital audio signal, and then supplied to the microprocessor 20. And microprocessor 20
However, the recording/reproducing circuit 21 is controlled to record the digital audio signal in the main data area, where the audio signal and video signal are recorded.

On the other hand, during playback, the microprocessor 2o supplies data (digital audio signal) in the main data area of the playback data obtained from the recording/playback circuit 21 to the D/A (digital/analog) conversion circuit 24 to produce analog audio. It is converted into a signal and output to the audio output terminal 25.

The microprocessor 2o also has switches 16 and 17.
is switched to the opposite state as shown in the figure, and out of the reproduced data obtained from the recording/reproducing circuit 21, the data (
The digital video signal) is sequentially stored in the memory 8 based on the address signal output from the address generation circuit 19.

Then, when the digital video signal for one screen is stored in the memory 18, the microprocessor 20 switches the switch L6
．． 17 is set to the switching state shown, and the digital video signal for one screen stored in the memory 18 is transferred to the memory 15 based on the address signal output from the memory control circuit 13.

Thereafter, the digital video signal for one screen transferred to the memory 15 is read out based on the AT 17 signal output from the memory control circuit 13, and converted into an analog video signal by the D/A conversion circuit 2G. Rear video output terminal 2
7, where the audio signal and video signal are reproduced.

However, in conventional digital audio tape recorders such as those mentioned above, the following problems occur.

That is, in general, the sampling frequency of A/D conversion by the A/D conversion circuit 12 is 10.7 MHz, and the bit length is 6 bits, so the memory 15 for storing one screen worth of digital video signals is As mentioned above, the storage capacity of .18 is 1 Mbit.

By the way, since the screen of a television receiver, video tape recorder, etc. is transmitted at a rate of 60 fields/second, a storage capacity of 60 Mbit/second is required to record all of this digital video signal. However, the maximum recording capacity of the subcode data area of a digital audio tape recorder is ND - NB - NT - NS (where ND is the maximum data length in one batch and is 52, and NB is one block). The maximum number of backs per track is 3.5, NT is 16 blocks per track, and NS is 66 to 68 tracks per second.) = 52X 3.5X16X6G = 1.99 .6 x 1.03 bits/sec, which makes it impossible to record the entire digital video signal mentioned above.

Moreover, in order to record the digital video signal for one screen, that is, one field, it takes 1 Mbit ÷ 1.99. [ik bits/sec - 5 seconds is required. That is, when recording a 1 Mbit digital video signal corresponding to one screen in the subcode pig area, it takes about 5 seconds. For this reason,
During playback, it takes about 5 seconds for 1M bits of digital video signals corresponding to one screen to be stored in the memory 18.

On the other hand, even if a digital audio signal read from a tape is subjected to signal processing such as error correction, it is D/A converted and output as an analog audio signal in an extremely short time. Therefore, by the time all the digital video signals for one screen have been stored in the memory 18, the audio corresponding to that screen has already been input five seconds ago, and when played back, There is a time lag between the audio and the audio.

(Problem to be solved by the invention) As described above, conventionally, it takes time for one screen's worth of digital video signals to be stored in memory during playback, resulting in a time lag between the screen and the sound signal. There is a problem.

Therefore, the present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide an extremely good image recording and reproducing device that compensates for the time lag between the screen and audio during playback and enables synchronized playback. purpose.

[Structure of the Invention] (Means for Solving the Problems) An image recording and reproducing apparatus according to the present invention first digitizes a video signal and an audio signal and records them on a recording medium, and then converts the digital video signal from the recording medium into a digital video signal and an audio signal. and devices that read and reproduce audio signals. The recording medium is configured to delay the recording operation of the digital audio signal onto the recording medium until one screen worth of digital video is recorded on the recording medium.

Further, the image recording and reproducing apparatus according to the present invention reads and reproduces digital video signals and audio signals from a recording medium in which the video signals and audio signals are respectively digitized and recorded. It is intended for devices that store digital video signals in a memo, and then read out the data from the memory when the screen worth of data is complete and use it for image display. The apparatus is configured to delay the reproduction operation of the digital audio signal read from the recording medium until the digital video signal for one screen is stored in the memory.

(Function) According to the configuration described in item 1, first, the recording operation of the digital audio signal to the recording medium is delayed until the digital video signal for one screen is recorded on the recording medium. Therefore, during playback, the digital video signal for one screen is stored and the sound is played when a still screen is displayed. This compensates for the time difference between the screen and the sound during playback, and synchronized playback. can be made possible.

In addition, the playback operation of the digital audio signal read from the recording medium is delayed until the digital video signal for one screen is stored in the memory. The audio will not be played back until the screen is displayed, and the time difference between the screen and the audio during playback can be compensated for and synchronized playback can be made possible.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 28 denotes an input terminal to which a digital audio signal output from the A/D conversion circuit 23 is supplied. The digital audio signal supplied to this input terminal 28 is supplied to a shift register 29 formed by cascadingly connecting 32 D-type flip-flop circuits (hereinafter referred to as D-FF circuits) 291 to 2932.

Here, each D-FF constituting this shift register 29
The clock input terminals C of the circuits 291 to 2932 are supplied with the clock signal supplied to the clock terminal 30. This clock signal has the same frequency fS as the sampling clock generated by the A/D conversion circuit 23.

In addition, the output terminal Q of each of the above D-FF circuits 291 to 2932
Each output generated from 1. It is supplied to a 32-bit memory 31 with a storage capacity of 2 OM bits, and is also supplied to a 32-bit memory 31 that has a storage capacity of about OM bits.
Preset end P of two D-FF circuits 321 to 3232
are supplied respectively.

(7) The clock signal supplied to the clock terminal 30 is inverted by the NOT circuit 33 and supplied to the clock input terminal C of each DFF circuit 321 to 3232 constituting the shift register 32. shift register 32
The output of the final stage D-FF circuit 3232 is output from output terminal 3.
4 to the microprocessor 20.

Here, the memory 31 is supplied with an address signal generated by the address generation circuit 35. This address generation circuit 35 increments at every Zumbling clock cycle and outputs a write address to the memory 31 for storing the digital audio signal latched in the shift register 29, and also outputs a write address to the memory 31 for storing the digital audio signal latched in the shift register 29. The value obtained by subtracting the numerical value "N" is output to the memory 31 as the read address of the digital audio signal to be output to the shift register 32.

According to the above configuration, the digital audio signal supplied to the input terminal 28 is delayed by Nx (1/fs) seconds and is then obtained from the output terminal 34.

If this delay time is made to correspond to the time (approximately 5 seconds) it takes for one screen's worth of digital video signals to be recorded in the subcode data area of the tape, then one screen's worth of digital video signals can be recorded. After being recorded in the subcode data area,
A digital audio signal is output from the output terminal 34 and recorded in the main data area of the tape.

Therefore, during playback, audio is played when one screen worth of digital video signals is stored in the memory 18 or a still screen is displayed, thereby compensating for the time lag between the screen and audio during playback. and enable synchronous playback.

Here, as a specific example, the sampling frequency fS is 48
kHz and a delay time of 5 seconds, 48 kHzX
5 = 240X 103, and the required storage capacity of the memory 31 is 24[lX103X32=7.6
It becomes 8M bits. Further, the bit length of the address generation circuit 35 is log 2240 x to 3 #17.9, which is 17 bits.

Here, the memory having the storage capacity as described in ``1'' has conventionally been a RAM (Random Access
However, in recent years, it has been constructed using a single-chip IC (integrated circuit), and can be realized with a simple configuration.

On the other hand, in the embodiment shown in FIG. 1, the input terminal 28 may be connected to the output terminal of the digital audio signal of the microprocessor 20, and the output terminal 34 may be connected to the input terminal of the D/A conversion circuit 24. . According to such a configuration, during playback, the digital audio signal obtained from the recording/playback circuit 21 via the microprocessor 20 is delayed by the delay time connected to - and is supplied to the D/A conversion circuit 24. become.

In other words, audio reproduction is not performed until digital video signals corresponding to ] screen are stored in the memory 18 and a still screen is displayed. Therefore, it is possible to compensate for the time difference between the screen and the sound during playback, and to enable synchronized playback.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide an extremely good image recording and reproducing device that compensates for the time lag between the screen and the audio during reproduction and enables synchronized reproduction. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image recording and reproducing apparatus according to the present invention, and FIG. 2 is a block diagram showing a conventional digital audio tape recorder. 11...Video input terminal, 12.A/D conversion circuit, 13
・Memory control circuit, 14...signal generation circuit,]
6 15...Memory, 16. 1.7...Switch, 18
...Memory, 19...Address generation circuit, 20...
・Microprocessor, 21.・Recording/reproducing circuit, 22.
...Audio input terminal, 23...A/D conversion circuit, 24...
D/A conversion circuit, 25...audio output terminal, 2G...D
/A conversion circuit, 27...Video output terminal, 28...Input terminal, 29...Shift register, 30...Clock terminal, 31...Memory, 32...Shift register, 33...
Not circuit, 34...output terminal, 35...address generation circuit.

Claims (2)

[Claims] (1) In an image recording and reproducing apparatus that digitizes a video signal and an audio signal and records them on a recording medium, and reads and reproduces each of the digital video signal and audio signal from the recording medium, the recording medium has one screen worth of data. An image recording and reproducing apparatus comprising: a delay means for delaying the recording operation of the digital audio signal on the recording medium for a period until the digital video signal is recorded. (2) A device that reads and reproduces the digital video signal and audio signal from a recording medium on which the video signal and audio signal are each digitized and recorded, and stores the digital video signal read from the recording medium in a memory. In an image recording and reproducing apparatus that stores data for one screen and then reads it from the memory and displays the image in a state in which data for one screen is complete, the digital video signal for one screen is stored in the memory. An image recording and reproducing apparatus comprising a delay means for delaying a reproduction operation of the read digital audio signal.